MM74HC4066
MM74HC4066
MM74HC4066
February 2008
MM74HC4066
Quad Analog Switch
Features General Description
■ Typical switch enable time: 15ns The MM74HC4066 devices are digitally controlled
■ Wide analog input voltage range: 0V–12V analog switches utilizing advanced silicon-gate CMOS
■ Low “ON” resistance: 30 typ. (MM74HC4066)
technology. These switches have low “ON” resistance
and low “OFF” leakages. They are bidirectional switches,
■ Low quiescent current: 80µA maximum (74HC)
thus any analog input may be used as an output and
■ Matched switch characteristics visa-versa. Also the MM74HC4066 switches contain
■ Individual switch controls linearization circuitry which lowers the “ON” resistance
and increases switch linearity. The MM74HC4066
devices allow control of up to 12V (peak) analog signals
with digital control signals of the same range. Each
switch has its own control input which disables each
switch when LOW. All analog inputs and outputs and
digital inputs are protected from electrostatic damage by
diodes to VCC and ground.
Ordering Information
Package
Order Number Number Package Description
MM74HC4066M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
MM74HC4066SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4066MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
MM74HC4066N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Top View
Schematic Diagram
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
TA = –40°C TA = –55°C
TA = 25°C to 85°C to 125°C
Symbol Parameter VCC (V) Conditions Typ. Guaranteed Limits Units
tPHL, tPLH Maximum Propagation 2.0V 25 50 30 75 ns
Delay Switch In to Out 4.5V 5 10 13 15
9.0V 4 8 10 12
12.0V 3 7 11 13
tPZL, tPZH Maximum Switch Turn 2.0V RL = 1kΩ 30 100 125 150 ns
“ON” Delay 4.5V 12 20 25 30
9.0V 6 12 15 18
12.0V 5 10 13 15
tPHZ, tPLZ Maximum Switch Turn 2.0V RL = 1kΩ 60 168 210 252 ns
“OFF” Delay 4.5V 25 36 45 54
9.0V 20 32 40 48
12.0V 15 30 38 45
fMAX Minimum Frequency 4.5V RL = 600Ω, 40 MHz
Response (Figure 7) VIS = 2 VPP at
9.0V 100
20 log (VO/VI) = –3dB (VCC/2)(5)(6)
Crosstalk Between 4.5V RL = 600Ω, –52 dB
any Two Switches F = 1MHz(6)(7)
9.0V –50
(Figure 8)
Peak Control to Switch 4.5V RL = 600Ω, F = 1MHz, 100 mV
Feedthrough Noise CL = 50pF
9.0V 250
(Figure 9)
Switch OFF Signal 4.5V RL = 600Ω, F = 1MHz, –42 dB
Feedthrough V(CT)VIL(6)(7)
9.0V –44
Isolation (Figure 10)
THD Total Harmonic 4.5V RL = 10kΩ, CL = 50pF, .013 %
Distortion (Figure 11) F = 1kHz, VIS = 4 VPP,
9.0V .008
VIS = 8 VPP
CIN Maximum Control 5 10 10 10 pF
Input Capacitance
CIN Maximum Switch 20 pF
Input Capacitance
CIN Maximum Feedthrough VCTL = GND 0.5 pF
Capacitance
CPD Power Dissipation 15 pF
Capacitance
Notes:
5. Adjust 0dBm for F = 1kHz (Null RL/RON Attenuation).
6. VIS is centered at VCC/2.
7. Adjust input for 0dBm.
Figure 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
Special Considerations
In certain applications the external load-resistor current
may include both VCC and signal line components. To
avoid drawing VCC current when switch current flows into
the analog switch input pins, the voltage drop across the
switch must not exceed 0.6V (calculated from the ON
resistance).
7.62
14 8
B
5.60
6.00 4.00
3.80
0.90
SEATING PLANE
0.50
(1.04)
DETAIL A
SCALE: 20:1
Figure 12. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Figure 13. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
1.65
0.45 6.10
Figure 14. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
19.56
18.80
14 8
6.60
6.09
1 7
0.38 MIN
3.81 0.58
3.17 0.35 8.82
2.54
Figure 15. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.