STM32L4+ vs STM32L4

Revision 2.0

This module presentation presents the key differences

between the STM32L4+ and the STM32L476/L486 devices.

1
 STM32L4Rxxx/Sxxx and
2
STM32L4P5xx/Q5xx Block Diagram
• Up to 120MHz, 406 CoreMark
Parallel Interface Connectivity
FSMC 8-/16-bit Cortex-M4
• Up to 2MB Flash / 640KB SRAM for (TFT-LCD, SRAM, NOR, 120 MHz USB OTG, 1x CAN,
2x SD/SDIO/MMC(2), 3x SPI,
STM32L4Rxxx/Sxxx devices NAND) FPU 4x I²C, 2xOctoSPI,
MPU 5x USART + 1x ULP UART
Display ETM
• Up to 1MB Flash / 320KB SRAM for MIPI-DSI(1) 2 Lanes 500Mps 2xDMA
STM32L4P5xx/Q5xx devices LCD-TFT Controller
ART Digital
Accelerator™ AES (256-bit), SHA 256,
Timers
• MIPI-DSI 2 Lanes 17 timers including: Up to PKA (3),TRNG, 2x SAI,
2-Mbyte Flash DFSDM (8 channels)
2 x 16-bit advanced motor
control timers with ECC
• LCD-TFT controller 2 x ULP timers Dual Bank
7 x 16-bit-timers Analog
Chrom-ART ™
2 x 32-bit timers
• Chrom-ART I/Os
Chrom-GRC ™(1) 2x 12-bit ADC(4), 2x DAC,
2x comparators, 2x op amps
Up to 114 I/Os 1x temperature sensor
Up to 640-Kbyte
• Chrom-GRC Touch-sensing controller RAM
Camera Interface

• 2xOctoSPI (1)
(2)
MIPI-DSI and Chrom-GRC are available only on STM32L4Rxxx/Sxxx devices
2x SDMMC for STM32L4P5xx/Q5xx devices and 1x SDMMC for STM32L4Rxxx/Sxxx devices
(3) PKA only for STM32L4P5xx/Q5xx devices
(4) 2x ADC for STM32L4P5xx/Q5xx devices and 1x ADC for STM32L4Rxxx/Sxxx devices

The STM32L4+ series stretches the STM32L4 technology

by offering higher performance, that is to say 120 MHz/406
CoreMark executing from internal Flash memory

The new STM32L4+ embeds up to 2 Mbytes of dual-bank

Flash memory and up to 640 Kbytes of embedded SRAM.

It also embeds advanced graphic features enabling state-

of-the-art Graphic User Interfaces.:

• The Chrom-ART Accelerator™, the ST proprietary 2D

hardware graphic accelerator, efficiently handles
repetitive graphic operations releasing the main CPU
capabilities for real-time processing or even more

2
 advanced graphic operations.

• The Chrom-GRC™ round display memory optimizer,

allowing up to 20% of graphic resources optimization

• The LCD-TFT controller and MIPI DSI controller

supporting 2 lanes.

• 2 x Octo SPI supporting Flash and PSRAM memories.

The system frequency is increased up to 120 MHz while

keeping state of the art ultra-low power figures.

2
 STM32L4+ & STM32L4 Series Pin Compatibility 3

STM32L4P5xx/Q5xx STM32L4R5xx/S5xx/R7
STM32L4P5xx/Q5xx STM32L4P5xx/Q5xx STM32L4R9xx/S9xx
vs. xx/S7xx
Package STM32L4R5xx/S5xx/R
vs. vs.
vs.
vs.
STM32L4R9xx/S9xx STM32L4 Series STM32L4 Series
7xx/S7xx STM32L4 Series

LQFP48
- - compatible - -
UFQFPN48

LQFP64 - - compatible - -

LQFP100 compatible incompatible compatible compatible incompatible

WLCSP100 - - compatible - -

UFBGA132 compatible - compatible compatible -

LQFP144 compatible incompatible compatible compatible incompatible

WLCSP144 - - - - -

UFBGA144 - - - - incompatible

UFBGA169 compatible incompatible compatible compatible incompatible

For more details about pin to pin compatibility refer to AN5017 “Migrating between STM32L476xx/486xx and STM32L4+ Series microcontrollers”

The STM32L4+ series is fully pin to pin compatible with the

STM32L4 series except for the STM32L4R9xx/S9xx lines.

3
 STM32L4+ & STM32L4 Series 4
Pin Compatibility
• Pin difference notification for board design with STM32L4S9xx/4R9xx

Pin 19 to pin 98
LQFP100 UFBGA169 Ball-out not compatible
are not compatible

Pin 20 to pin 129

are not compatible LQFP144

Balls in Blue are

not compatible

The three figures illustrate the LQFP100, LQFP144 and

UFBGA169 pinout/ball-out differences between
STM32L476/486, STM32L4Q5xx/P5xx and the
STM32L4R9/4S9 lines.

4
System Architecture

Let’s have a look at the System architecture changes that

we see with the STM32L476/486 microcontrollers.

5
 STM32L4+ System Architecture 6

32-bit multilayer AHB bus matrix, 9 Masters, 11 Slaves

GFXMMU(1)
Cortex-M4 DMA1 DMA2 DMA2D LCD-TFT SDMMC1
SDMMC2(2)
D-Bus

S-Bus
I-Bus

ICode

ACCEL
FLASH
DCode up to 2 MB

SRAM1

SRAM2

SRAM3

GFXMMU(1)

AHB1
Peripheral
AHB2
Peripheral

FMC

OCTOPI1

OCTOPI2

BusMatrix-S
(1) GFXMMU is only available on STM32L4P5xx/4Q5xx devices
(2) SDMMC2 is only available on STM32L4Rxxx/4Sxxx devices

The STM32L4+ main system architecture consists of 32-bit

multilayer AHB bus matrix that interconnects 9 masters and
11 slaves. The main differences with STM32L476/486
devices are highlighted in pink square.
System Control

The STM32L4+ brings some new features in clock

configuration management.

7
 Clock Scheme - New Features 8

The STM32L4+ series features additional clock

configuration - the main differences with the
STM32L476/486 devices are highlighted with the pink
squares.

8
 Clock Scheme New Features 9

STM32L476xx/486xx STM32L4+
PLLM divider PLLM:1 to 8 PLLM: 1 to 16
PLLN factor PLLN:8 to 86 PLLN: 8 to 127
PLLP divider PLLP: 7 or 17 PLLP: 2 to 31
PLLSAI1M divider NA PLLSAI1M: 1 to 16
PLLSAI1N factor PLLSAI1N: 8 to 86 PLLSAI1N: 8 to 127
PLLSAI1P divider PLLSAI1P: 7 or 17 PLLPSAI1P: 2 to 31
PLLSAI2M divider NA PLLSAI2M: 1 to 16
PLLSAI2N factor PLLSAI2N: 8 to 86 PLLSAI2N: 8 to 127
PLLSAI2P divider PLLSAI2P: 7 or 17 PLLSAI2P: 2 to 31
PLLSAI2Q divider NA PLLSAI2Q: 2, 4, 6 or 8
HSI16 HSITRIM[4:0] HSITRIM[6:0]
HSI48 NA RC with clock recovery used for
USB/RNG/SDMMC

This table highlights the differences related to the Reset

and Clock Control (RCC) mainly for PLL dividers and
factors between STM32L4+ and STM32L476xx/486xx
microcontrollers.

9
 System Clock Selection 10

• Switching from Low to High speed or from High to Low speed system
clock, it is recommended to use a transition state with a medium speed
clock for at least 1us.

• Clock source switching conditions:

• Switching from HSE or HSI or MSI to PLL with AHB frequency ( HCLK) higher than
80MHz.
• Switching from PLL with HCLK higher than 80MHz to HSE or HSI or MSI

• Transition state:
• Set the AHB prescaler HPRE[3:0] bits to divide System frequency by 2
• Switch system clock to PLL
• Reconfigure AHB prescaler bits to needed HCLK frequency

In STM32L4+ Series devices, it is recommended to use a

transition state while switching from Low to High speed or
from High to Low speed system clock. This slide presents
the recommended sequence for the transition state.

10
Memory Mapping and NVIC

These slides show the embedded SRAM memory mapping

differences between STM32L4+ and STM32L476xx/486xx
microcontrollers and the interrupt vector table as well.

11
 Embedded SRAM Memory Mapping 12

• Up to 640KB, All SRAMs are contiguous

0x4000 0000 0x4000 0000 0x4000 0000
GFXMMU Virtual Buffer GFXMMU Virtual Buffer
0x3000 0000 0x3000 0000

0x200A 0000 0x2005 0000

SRAM3 (384 Kbyte) SRAM3 (128 Kbyte)
0x2004 0000 0x2003 0000
SRAM2 (64 Kbyte) SRAM2 (64 Kbyte)
0x2003 0000 0x2002 0000 0x2001 8000
SRAM1 (192 Kbyte) SRAM1 (128 Kbyte) SRAM1 (96 Kbyte)
0x2000 0000 0x2000 0000 0x2000 0000

0x1001 0000 0x1001 0000 0x1000 8000

SRAM2 ( 64 Kbyte) SRAM2 ( 64 Kbyte) SRAM2 ( 32 Kbyte)
0x1000 0000 0x1000 0000 0x1000 0000

STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476/L486

(640 Kbytes) (320 Kbytes) (128 Kbytes)

The STM32L4+ Series devices feature an additional

SRAM3. Compared to STM32L476xx/486xx devices, the
SRAM2 is contiguous to the SRAM1 and it is still mapped
at 0x1000 0000 address.

12
 External Memory Mapping 13

0xA000 1800 0xA000 1400

OCTOSPI Registers QuadSPI registers
0xA000 1000 0xA000 1000
FSMC Registers FSMC Registers
0xA000 0000 0xA000 0000
OCTOSPI1 bank QuadSPI1 bank

0x9000 0000 0x9000 0000

FSMC NAND bank FSMC NAND bank
0x8000 0000 0x8000 0000
OCTOSPI2 bank Reserved
0x7000 0000 0x7000 0000

FSMC NOR/PSRAM bank FSMC NOR/PSRAM bank

0x6000 0000 0x6000 0000

STM32L4+ Series STM32L476/486

This slide presents the external memory mapping

differences between STM32L4+ Series and
STM32L476xx/486xx devices.

13
 NVIC Interrupt Vectors 14

Position STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476xx/486xx

18 ADC1 ADC1_2 ADC1_2

41 RTC_ALARM RTC_ALARM_SSRU RTC_ALARM

42 DFSDM1_FLT3 Reserved DFSDM1_FLT3

47 Reserved SDMMC2 ADC3

63 DFSDM1_FLT2 Reserved DFSDM1_FLT2

71 OCTOSPI1 QUADSPI

76 OCTOSPI2 SWPMI

78 DSIHOST Reserved LCD

82 HASH and CRS Reserved

83 I2C4_EV Reserved

84 I2C4_ER Reserved

85 DCMI DCMI_PSSI Reserved

90 DMA2D Reserved

91 LCD-TFT Reserved

92 LCD-TFT_ER Reserved

93 GFXMMU Reserved Reserved

94 DMAMUX1_OVR Reserved

This slide presents the interrupt vector differences between

STM32L4Rxxx/4Sxxx, STM32L4P5xx/4Q5xx and
STM32L476xx/486xx devices.

14
Embedded FLASH

Let’s now go through the key new aspects of the flash

memory between STM32L4+ Series and
STM32L476xx/486xx devices.

15
 STM32L4+ Flash Memory 16

• Up to 2 Mbytes : 256 pages

• Single Bank: Page size = 8 Kbytes,
• Dual Bank: Page size = 4 Kbytes

• 1 Kbyte OTP (one-time programmable)

• Flash memory read operations with two data width modes :

• Single bank mode DBANK=0: read access of 128 bits
• Dual bank mode DBANK=1: read access of 64 bits

• Protections:
• Single Bank: 4 WPR areas, 2 PCROP areas
• Dual Bank: 2 WPR areas per bank, 1 PCROP area per bank

The flash memory can be configured by option byte

(DBANK) in single bank mode with 128-bit read access or
in dual bank mode with 64-bit read access.

16
 Flash Memory Organization 17

DBANK Dual Bank

Single Bank
Mode (STM32L4 Series Compatible)

Size
Flash area Flash memory addresses Page# Flash memory addresses Size (bytes) Page#
(bytes)

0x0800 0000 – 0x0800 0FFF 4K Page 0 0x0800 0000 – 0x0800 1FFF 8K Page 0

0x0800 1000 – 0x0800 1FFF 4K Page 1 0x0800 2000 – 0x0800 3FFF 8K Page 1
Bank 1
Main memory

- - - -

Single Bank
0x080F F000 – 0x080F FFFF 4K Page 255

0x0810 000 – 0x0810 0FFF 4K Page 0

0x0810 1000 – 0x010 1FFF 4K Page 1

Bank 2
- - -

0x081F E000 – 0x081F FFFF 8K Page 255

0x081F F000 – 0x081F FFFF 4K Page 255

This slide presents the flash memory organization in single

bank and in dual bank mode.
In dual bank mode, the main memory is divided into two 1-
Mbyte banks, and each bank is split in 256 pages of 4
Kbytes.
In single bank mode, the main memory is a single 2-Mbyte
bank split in 256 pages of 8 Kbytes.

17
 Option Bytes New Features 18

STM32L4+ STM32L476xx/486xx

nBOOT0 NA

nSWBOOT0 NA

DBANK ( Dual bank mode) NA

Option bytes DB1M DUALBANK

(1MB/512KB dual-Bank) (256/128 Dual-Bank)

PCROP1_STRT[16:0] PCROP1_STRT[15:0]
PCROP2_STRT[16:0] PCROP2_STRT[15:0]

PCROP1_END[16:0] PCROP1_END[15:0]
PCROP2_END[16:0] PCROP2_END[15:0]

This slide presents the differences regarding the option

bytes between STM32L4+ and STM32L476xx/486xx
devices.

18
 Flash Memory Wait States 19

STM32L4+ Series
Max frequency (MHz)
CPU Power Typical value
VCORE range
performance performance (V)
0WS 1WS 2WS 3WS 4WS 5WS

Range1: boost mode 1.28 100 120

High Low 20 40 60 80
Range1: normal mode 1.2 NA NA

Medium High Range 2 1.0 8 16 26 - - -

STM32L476xx/486xx
Max frequency (MHz)
Typical value
CPU performance Power performance VCORE range
(V)
0WS 1WS 2WS 3WS 4WS 5WS
High Low Range1 1.2 16 32 48 64 80 -

Medium High Range 2 1.0 6 12 18 26 -

In order to read the Flash memory, it is necessary to

configure the number of wait states to be inserted in a read
access, depending on the clock frequency. The number of
wait states also depends on the voltage scaling range.
The two tables present the differences in wait states
between STM32L4+ Series devices and
STM32L476xx/486xx devices.

19
Power Controller (PWR)

More features are also added into the STM32L4+

microcontroller, which gives the user more flexibility.

20
 Power Supply 21

• DSI power supply for STM32L4R9xx/S9xx VDDA domain

A/D converter

• DSI (Display Serial Interface) power supply pins VDDA

D/A converter
Comparators
OPAMP
VSSA Voltage reference
• VDDDSI an independent DSI power supply dedicated to buffer
VDDUSB
the DSI regulator and MIPI DPHY VSS
USB transceivers

VDDIO2 domain
• It must be connected to VDD VDDIO2
I/O ring
VDDIO2
• VCAPDSI the DSI regulator (1.2V) output VSS PG[15:2]
VDDDSI DSI
• It must be connected to VDD12DSI. VCAPDSI Voltage regulator

DSI PHY
• VDD12DSI used to supply the MIPI D-PHY, clock and VDD12DSI
VDD domain
data lanes VDDIO1 I/O ring

Reset block
• A 2.2 µF must be connected to VDD12DSI Temp. sensor
3 x PLL, HIS, MSI VCORE domain
VSS
• VSSDSI is an isolated ground supply used for DSI sub- VDD
Standby circuitry
(Wakeup logic, IWDG)
Core
SRAMs
system Voltage regulator VCORE Digital
peripherals

Low voltage detector

Flash memory
Backup domain
• If DSI is not used: VBAT LSE crystal 32K osc
BKP registers
RCC BDCR registers
• VDDDSI must be connected to VDD RTC

• VCAPDSI and VDD12DSI can be left floating

• VSSDSI must be grounded

The STM32L4R9xx/S9xx devices feature the DSI (Display

Serial Interface) sub-system and it uses several power
supply pins which are independent from the other supply
pins: VDDDSI, VCAPDSI and VDD12DSI.
If DSI peripheral is not used, the VDDDSI must be
connected to VDD while VCAPDSI and VDD12DSI can be
left floating.

21
 Main Regulator: Voltage Scaling Range 22

SYSCLK
(max frequency)

• Main regulator output voltage: 120 MHz

• Range 1 :
• Boost mode: 1.28V
80 MHz
• Normal mode: 1.2V (default after reset)
Range 1
• Range 2: 1.0V Range 1 boost mode
normal 1.28V
26 MHz
mode
• Power consumption optimization up Range 2 1.2V
to 10% in range1 normal mode vs 1.0V

boost mode Voltage scaling

Caution: To use USB or DSI, range 1 boost mode must be selected.

The main regulator output voltage can be programmed by

software in two power ranges Range 1 and Range 2.
In range1, the main regulator operates in two modes that
can be selected by software :
• Range 1 normal mode: provides a typical output voltage
at 1.2 V, allowing a system clock up to 80 MHz.
• Range 1 boost mode: provides a typical output voltage
at 1.28 V, allowing a system clock up to 120 MHz.

The range 1 normal mode optimizes the power

consumption up to 10% comparing to range 1 boost mode.
When you are using the USB or DSI peripheral, the range 1
boost mode must be selected.

22
 Low Power Modes 23

STM32L4+ STM32L476/486xx
STOP0
STOP1
STOP2 SRAM3 OFF
Low Power STOP2
STOP2 SRAM3 ON
Modes
Standby SRAM2 (64 Kbytes) OFF(1) Standby
Standby SRAM2 (64 Kbytes) ON(1)
Shutdown
(1) On STM32L4P5xx/4Q5xx devices SRAM2 can be fully (64 Kbytes) or partially (4 Kbytes) retained in Standby

The STM32L4+ series features the same Low Power mode

as the STM32L4 series with a new option to switch OFF or
ON the SRAM3 during STOP2 mode and to switch OFF or
ON the SRAM2 in Standby mode.

23
 ULP Bench Score Differences 24

• The ULP Bench score is also impacted by the difference in consumption:

L49x/4Ax L47x/48x L45x/46x L43x/44x L4Rxx/L4Sxx L4P5xx/L4Q5xx

ULP Bench score 145 153 174.5 176.7 233 285

The ULP Bench score on STM32L4+ series devices is

higher compared to the one on STM32L4 series devices.

24
Communication & Peripherals

The next tables detail the changes between the series

concerning communications and peripherals.

25
STM32L476/486 Versus STM32L4+ Series 26

STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476/486

Power supply
1.71 ~ 3.6V with VBAT 1.71 ~ 3.6V with VBAT

Maximum Frequency 120MHz 80MHz

Up to 2MB Up to 1MB 1MB

Flash Dual Bank (RWW)
Dual Bank ( RWW)
or Single Bank

SRAM1: 192KB SRAM1: 128KB SRAM1: 96KB

SRAM2: 64KB SRAM2: 32KB
System
SRAM3: 384KB SRAM3: 128KB NA

Backup-registers 32 x32-bit
8-,16-bit NOR, PSRAM, SRAM , FRAM and NAND memories
• New data hold timing 8-,16-bit NOR, PSRAM, SRAM and NAND
External Memory FSMC
• New NBL setup timing memories
• Clock divider =1
2x OctoSPI: Octal flash + Octal
External Memory
2x OctoSPI: Octal flash memories PSRAM + HyperRAM memories 1x QuadSPI in single Flash mode
QuadSPI/OctoSPI
Multiplexed mode

New clock source HSI48 for USB,RNG and SDMMC

RCC New PLLx divider, NA
RTC APB clock gating

This table summarizes the key differences for system

peripherals between the STM32L4+ series and
STM32L476/786 devices.

26
STM32L476/486 Versus STM32L4+ Series 27

STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476/486

ANASWVDD bit: GPIO analog switch control voltage selection :

- VDDA or booster
SYSCFG - VDD
NA
I2C4 Fast-mode Plus driving capability activation
PWR: New range 1 mode ( Normal mode/ Boost mode)
LP Mode: STOP2 + SRAM3 ON/OFF
PWR
- Standby + 64KB SRAM2 ON/OFF
Standby + 64KB SRAM2 ON/OFF
- Standby + 4KB SRAM2 ON/OFF
1x SDMMC 2x SDMMC 1x SDMMC
Data transfer up to 104 Mbyte/s Data transfer up to 104 Mbyte/s for Data transfer up to 50 MHz for the 8- bit
for the 8- bit mode. the 8- bit mode. mode.
Peripheral Summary DFSDM ( 4x Channels, 2x Filters)
DFSDM ( 8x Channels, 4x Filters)
(DFSDM audio, beamforming,
(DFSDM audio, beamforming,
internal ADC inputs, new trigger DFSDM ( 8x Channels, 4x Filters)
internal ADC inputs, new trigger
source)
source)

OTG_FS with clock recovery OTG_FS without clock recovery

This slide continues the presentation of the key differences

between STM32L476/786 devices and STM32L4+ Series
devices – again the differences are highlighted in pink.

27
STM32L476/486 Versus STM32L4+ Series 28

STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476/486

4 x I2C 3 x I2C

- PSSI

2x SAI ( PDM mode on SAI1), new clock source ( HSI) 2x SAI

5x U(S)ART + 1x LPUART
5x U(S)ART + 1x LPUART
(FIFO, SPI slave transmission)
1xCAN 2xCAN

1x ADC (12-bit) 2x ADC (12-bit) 3x ADC (12-bit)

2x 12-bit DAC channels (updated triggers) 2x 12-bit DAC channels
Peripheral Summary
2xOPAMP, 2xCOMP

CRC/ 2x DMA / RTC / FIREWALL/ WWDG / IWDG / TIMx / LPTIMx /TSC/RNG

DMAMUX -

AES -

- PKA -

HASH -

- LCD

- SWPMI

And here are some more peripheral updates between the

two product lines.

28
STM32L476/486 Versus STM32L4+ Series 29

STM32L4Rxxx/4Sxxx STM32L4P5xx/4Q5xx STM32L476/486

DMA2D with byte swap bytes tow by two ( SB bit added) to support -
18/24-bit mode (RGB888)
MIPI-DSI Host ( 2 lanes) - -

Graphic Peripherals Chrom-GRC (GFXMMU) - -

LCD-TFT -

Digital Camera interface (14-bit) -

As already said in introduction, STM32L4+ embeds

advanced graphic features enabling state-of-the-art
Graphic User Interfaces.

29
Ecosystem

And finally, even though the STM32L4+ series embeds

many upgraded key features, the working environment
remains the same!

30
 STM32L4Plus Ecosystem 31

STM32CubeMX
• Initialization Code generation based on user choices

STM32CubeL0
STM32CubeF4

STM32CubeL1 STM32CubeF2

STM32CubeL4
STM32CubeF3
STM32CubeF0 STM32CubeF1

STM32Cube HAL: Portable API within all series - Middleware stacks when applicable:
RTOS, USB, TCP/IP, Graphics, …

So the STM32L4 and STM32L4+ product family share the

same software package known as the STM32Cube.
The STM32Cube HAL is a common library which
addresses the entire STM32 microcontrollers family.
Specifically, the STM32L4 firmware package offers a
standard HAL as well as Low Layer drivers and examples.
So if you are already using our STM32L4Cube, you just
need to upgrade it from www.st.com to get the latest
version.

31
 References 32

• For more details, please refer to following sources

• AN5017: Migrating between STM32L476xx/486xx and STM32L4+ Series microcontrollers

For more details, please refer to application note AN5017

about the migration from STM32L476xx/486xx to
STM32L4+ Series microcontrollers.

32