STM 32 MP 257 F

STM32MP251C/F STM32MP253C/F
STM32MP255C/F STM32MP257C/F
Datasheet
Arm® based dual Cortex®-A35 1.5 GHz + Cortex®-M33 MPU, AI, 3D GPU,
video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto
Features
Includes ST state-of-the-art patented technology.
VFBGA361 (10 × 10 mm) pitch 0.5 mm Cores

VFBGA424 (14 × 14 mm) pitch 0.5 mm
TFBGA436 (18 × 18 mm) pitch 0.8 mm • Up to 64-bit dual-core Arm® Cortex®-A35
– Up to 1.5 GHz
– 32-Kbyte I + 32-Kbyte D level 1 cache for each core
– 512-Kbyte unified level 2 cache
– Arm® NEON™ and Arm® TrustZone®
• 32-bit Arm® Cortex®-M33 with FPU/MPU
Prerelease product(s)
Product summary – Up to 400 MHz

STM32MP251C, – L1 16-Kbyte I / 16-Kbyte D
STM32MP251F,
STM32MP253C, – Arm® TrustZone®
STM32MP25xC/F
STM32MP253F, • 32-bit Arm® Cortex®-M0+ in SmartRun domain
STM32MP255C,
STM32MP255F, – Up to 200 MHz (up to 16 MHz in autonomous mode)
STM32MP257C,
STM32MP257F Memories
• External DDR memory up to 4 Gbytes
– Up to DDR3L-2133 16/32-bit
– Up to DDR4-2400 16/32-bit
– Up to LPDDR4-2400 16/32-bit
• 808-Kbyte internal SRAM: 256-Kbyte AXI SYSRAM, 128-Kbyte AXI video RAM
or SYSRAM extension, 256-Kbyte AHB SRAM, 128-Kbyte AHB SRAM with
ECC in backup domain, 8-Kbyte SRAM with ECC in backup domain, 32 Kbytes
in SmartRun domain
• Two Octo-SPI memory interfaces
• Flexible external memory controller with up to 16-bit data bus: parallel interface
to connect external ICs, and SLC NAND memories with up to 8-bit ECC
Security/safety
• Secure boot, TrustZone® peripherals, active tamper, environmental monitors,

display secure layers, hardware accelerators
• Complete resource isolation framework
Reset and power management

• 1.71 to 1.95 V and 2.7/3.0 to 3.6 V multiple section I/O supply
• POR, PDR, PVD, and BOR
• On-chip LDO and power-switches for RETRAM, BKPSRAM, VSW, and
SmartRun domains
• Dedicated supplies for Cortex®-A35 and GPU/NPU (if present)
• Internal temperature sensors
• Low-power modes: Sleep, Stop, and Standby
• DDR memory retention in Standby mode
DS14284 - Rev 2 - June 2024 www.st.com

For further information contact your local STMicroelectronics sales office.
STM32MP251C/F STM32MP253C/F STM32MP255C/F
STM32MP257C/F
• Controls for PMIC companion chip
Low-power consumption
Clock management
• Internal oscillators: 64 MHz HSI, 4/16 MHz MSI, 32 kHz LSI
• External oscillators: 16-48 MHz HSE, 32.768 kHz LSE
• Up to 8× PLLs with fractional mode
General-purpose inputs/outputs
• Up to 172 secure I/O ports with interrupt capability
– Up to 6 wake-up inputs
– Up to 8 tamper input pins + 8 active tampers output pins
Interconnect matrix
• Bus matrices
– 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz

– 32-bit Arm® AMBA® AHB interconnect, up to 400 MHz
4 DMA controllers to unload the CPU

• 48 + 4 physical channels in total
• 3× dual master port, high-performance, general-purpose, direct memory access controller (HPDMA), 16
channels each
• 1× low-power DMA controller with 4 channels in SmartRun domain
Up to 51 communication peripherals
• 8× I2C FM+ (1 Mbit/s, SMBus/PMBus®)

• 4× I3C (12.5 Mbit/s)
• 5× UART + 4× USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI) + 1× LPUART
• 8× SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy via internal audio PLL or external
clock)(+2 with OCTOSPI + 4 with USART)
• 4× SAI (stereo audio: I2S, PDM, SPDIF Tx)
• SPDIF Rx with 4 inputs
• 3× SDMMC up to 8-bit (SD/e•MMC™/SDIO)
• Up to 3× CAN controllers supporting CAN FD protocol, out of which one supports time-triggered CAN
(TTCAN)
• 1× USB 2.0 high-speed Host with embedded 480 Mbits/s PHY
• 1× USB 2.0/3.0 high-speed/SuperSpeed dual role data with embedded 480 Mbits/s and 5 Gbits/s PHY
(5 Gbits/s PHY shared with PCI Express)
• 1× USB Type-C® Power Delivery control with two CC lines PHY
• 1 × PCI Express with embedded 5 Gbits/s PHY (PHY shared with USB 3.0 SuperSpeed)
• Up to 3× Gigabit Ethernet interfaces
– 1× Gigabit Ethernet GMAC with one PHY interface (optional)
– 1× Gigabit Ethernet GMAC with one external PHY interface, optionally internally connected to one
embedded Ethernet switch providing two external PHY interfaces
– TSN, IEEE 1588v2 hardware, MII/RMII/RGMII
DS14284 - Rev 2 page 2/234

STM32MP257C/F
• Camera interface #1 (5 Mpixels @30 fps)

– MIPI CSI-2®, 2× data lanes up to 2.5 Gbit/s each
– 8- to 16-bit parallel, up to 120 MHz
– RGB, YUV, JPG, RawBayer with Lite-ISP
– Lite-ISP, demosaicing, downscaling, cropping, 3 pixel pipelines
• Camera interface #2 (1 Mpixels @15 fps)
– 8- to 14-bit parallel, up to 80 MHz
– RGB, YUV, JPG
– Cropping
• Digital parallel interface up to 16-bit input or output
7 analog peripherals
• 3 × ADCs with 12-bit max. resolution (up to 5 Msps each, up to 23 channels)
• Internal temperature sensor (DTS)
• 1× multifunction digital filter (MDF) with up to 8 channels/8 filters
• 1× audio digital filter (ADF) with 1 filter and sound activity detection
• Internal (VREFBUF) or external ADC reference VREF+
Graphics
• Optional 3D GPU: VeriSilicon® - Up to 900 MHz

– OpenGL® ES 3.1 - Vulkan 1.3
– OpenCL™ 3.0, OpenVX™ 1.3
– Up to 150 Mtriangle/s, 900 Mpixel/s
• LCD-TFT controller, up to 24-bit // RGB888
– Up to FHD (1920 × 1080) @60 fps
– 3 layers including a secure layer
– YUV support, 90° output rotation
• Optional MIPI DSI®, 4× data lanes, up to 2.5 Gbit/s each
– Up to QXGA (2048 × 1536) @60 fps
• Optional FPD-1 and OpenLDI JEIDA/VESA (LVDS), up to 2× links of 4× data lanes, up to 1.1 Gbit/s per
lane
– Up to QXGA (2048 × 1536) @60 fps
Artificial intelligence
• Optional NPU: VeriSilicon® - Up to 900 MHz

– TensorFlowLite - ONNX - Linux NN
Video processing
• Optional hardware video encoder and decoder up to 600 MHz
– H264/VP8 up to FHD (1920×1080) @60 fps
– JPEG up to 500 Mpixel/s
– 128 Kbytes of video RAM
Up to 34 timers and 7 watchdogs

• 4× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
• 3× 16-bit advanced motor control timers
• 10× 16-bit general-purpose timers (including 2 basic timers without PWM)
• 5× 16-bit low-power timers
• Secure RTC with subsecond accuracy and hardware calendar
• Up to 2× 4 Cortex®-A35 system timers (secure, non-secure, virtual, hypervisor)
DS14284 - Rev 2 page 3/234

STM32MP257C/F
• 2× SysTick Cortex®-M33 timer (secure, non-secure)

• 1× SysTick Cortex®-M0+ timer
• 7× watchdogs (5× independent and 2× window)
Hardware acceleration
• AES-128, -192, -256, DES/TDES
• Secure AES-256 with SCA
• RSA, ECC, ECDSA with SCA
• HASH (SHA-1, SHA-224, SHA-256, SHA3), HMAC
• True random number generator
• CRC calculation unit
• “On-the-fly” DDR encryption/decryption (AES-128)
• “On-the-fly” OTFDEC Octo-SPI flash memory decryption (AES-128)
Debug mode
• Arm® CoreSight™ trace and debug: SWD and JTAG interfaces

12288-bit fuses including 96-bit unique ID
All packages are ECOPACK2 compliant
DS14284 - Rev 2 page 4/234

STM32MP251C/F STM32MP253C/F STM32MP255C/F STM32MP257C/F
Introduction
1 Introduction
This document provides information on STM32MP25xC/F devices, such as description, functional overview, pin
assignment and definition , electrical characteristics, packaging and ordering information.
It must be read in conjunction with the STM32MP25xC/F reference manual (RM0457).
For information on the device errata with respect to the datasheet and reference manual, refer to the
STM32MP25xC/F errata sheet (ES0598).
For information on the Arm® Cortex®- M33 core, refer to the Cortex®- M33 Technical Reference Manual, available
from the www.arm.com website.
Note: Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
DS14284 - Rev 2 page 5/234

Description
2 Description
STM32MP25xC/F devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC
core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each
CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 processor uses a
highly efficient 8-stage in-order pipeline that has been extensively optimized to provide full Armv8-A features while
maximizing area and power efficiency.
STM32MP25xC/F devices also embed a Cortex®-M33 32-bit RISC core operating at up to 400 MHz frequency.
The Cortex®-M33 core features a floating point unit (FPU) single precision which supports Arm® single-precision
data-processing instructions, and data types. The Cortex®-M33 supports a full set of DSP instructions,
TrustZone®, and a memory protection unit (MPU) which enhances application security.
The devices also embed a Cortex®-M0+ 32-bit RISC core operating at up to 200 MHz frequency (16 MHz when
running from backup regulator). This processor is located in the SmartRun domain, and can be used to ensure
very-low-power peripheral activity when all other processors and domains are stopped.
STM32MP25xC/F devices can also embed a 3D graphic processing unit (VeriSilicon®, OpenGL ES 3.1,
Vulkan 1.3, OpenCL 3.0, OpenVX 1.3) running at up to 900 MHz, with performances up to 150 Mtriangle/s,
900 Mpixel/s.
The graphic processing unit can provide a neural processor unit (VeriSilicon®, TensorFlowLite, ONNX, Linux NN)
running at up to 900 MHz.

STM32MP25xC/F devices provide an external SDRAM interface supporting external memories up to 32‑Gbit
density (4 Gbytes), 16- or 32-bit DDR3L up to 1066 MHz, 16- or 32-bit LPDDR4 or DDR4 up to 1200 MHz. The
SDRAM content can be encrypted with AES-128.
The devices incorporate high-speed embedded memories: 808 Kbytes of internal SRAM (including 256-Kbyte AXI
SYSRAM, 128-Kbyte AXI video SRAM (which can be used as general purpose), two banks of 128 Kbytes each of
AHB SRAM, three banks of 8, 8, and 16 Kbytes of AHB SRAM in SmartRun domain, 128 Kbytes of AHB SRAM in
backup domain, and 8 Kbytes of SRAM in backup domain), as well as an extensive range of enhanced I/Os and
peripherals connected to APB buses, AHB buses, a 32-bit multi-AHB bus matrix, and a 128/64-bit multi-layer AXI
interconnect supporting access to internal and external memories.
Each device offers three ADCs, a low-power secure RTC, 12 general-purpose 16-bit timers, 4 general-purpose
32-bit timers, three PWM timers for motor control, five low-power timers, and a true random number generator
(RNG) , and cryptographic acceleration cells.
STM32MP25xC/F devices offer a video encoder and a video decoder.
The devices support 8 multi-function digital filters (MDF), and one dedicated audio-digital filter with sound-activity
detection (ADF).
The devices feature the following standard and advanced communication interfaces.
Standard peripherals
• eight I2Cs
• four I3Cs
• four USARTs and five UARTs
• one low-power UART
• eight SPIs, three I2Ss full-duplex master/slave. The I2S peripherals can be clocked via a dedicated internal
audio PLL or via an external clock.
• four SAI serial audio interfaces
• one SPDIF Rx interface
• three SDMMC interfaces
• an USB 2.0 Host with embedded Hi-Speed PHY
• an USB 2.0/3.0 dual-role data with both Hi-Speed and 5Gbits/s SuperSpeed PHYs
• three FDCAN interfaces, including one supporting TTCAN mode (optional)
• two Gigabit Ethernet Interface, with TSN support (optional)
• one Gigabit Ethernet Switch connected to ETH1 and providing two external PHY interfaces, with TSN
support (optional)
Advanced peripherals including
• a flexible memory control (FMC) interface
DS14284 - Rev 2 page 6/234

Description
• two Octo-SPI flash memory interface , with on-the-fly content decryption

• two camera interfaces for CMOS sensors, one with basic ISP, demosaicing and parallel or MIPI CSI
interface
• an LCD-TFT display interface
• a MIPI DSI display interface (optional)
• an LVDS display interface (optional)
A comprehensive set of power-saving mode allows the design of low-power applications.
STM32MP25xC/F devices are proposed in various packages up to 436 balls with 0.5 mm to 0.8 mm pitch. The set
of included peripherals can change with the selected device.
These features make STM32MP25xC/F devices suitable for a wide range of consumer, industrial, white goods
and medical applications.
Figure 1 shows the general block diagram of STM32MP25xC/F devices.
Table 1. STM32MP25xC/F features and peripheral counts
Features STM32MP25xC/F
VFBGA361 (10×10 pitch 0.5 mm),

Package VFBGA424 (14×14 pitch 0.5 mm),
TFBGA436 (18×18 pitch 0.8 mm)(1)

Up to dual-core Cortex-A35 FPU Neon
CPU processor
TrustZone, up to 1500 MHz(1)
ROM 128 Kbytes (only for Cortex-A35)
GPU Optional VeriSilicon GC8000UL up to
NPU 900 MHz(1)
- Cortex-M33 FPU TrustZone

16-Kbyte data cache
MCU processor Caches size
16-Kbyte instruction cache
Frequency 400 MHz
- Cortex-M0+
SmartRun processor
Frequency 16 MHz
Decoder (VDEC) H264/VP8 up to 1080p60
Video Encoder (VENC) JPEG 500 Mpixel/s(1)
Video RAM Up to 128 Kbytes(1)
CPU system Up to 384 Kbytes(1)

MCU system 256 Kbytes (128 Kbytes tamper protected)
Embedded SRAM (808 Kbytes) MCU retention 128 Kbytes
SmartRun domain 32 Kbytes
Backup 8 Kbytes (tamper protected)
DDR3L 1066 MHz
SDRAM DDR4 1200 MHz Up to 4 Gbytes(1)
LPDDR4 1200 MHz
Backup registers 512 bytes (128 × 32-bits, tamper protected)
Advanced 16 bits 3
16 bits 8
Timers General purpose
32 bits 4
Basic 16 bits 2
DS14284 - Rev 2 page 7/234

Description
Low power 16 bits 5

24 bits 2 (Cortex-M33, secure and non-secure)
SysTick
24 bits 1 (Cortex-M0+)
Timers
Up to 2 × 4 (secure, non-secure, Virtual,
Cortex-A35 (CNT) 64 bits
Hypervisor)(1)
RTC 1
Watchdog 7 (5× independent, 2× window)
Total 8
SPI
having I2S 3
I2C (with SMB/PMB support) 8
I3C 4
USART (Smartcard, SPI, IrDA, LIN) + UART (IrDA,
4+5
LIN)(2)
LPUART 1
4 (up to 8 audio channels), with I2S master/

SAI slave, PCM input,
Communication
Peripherals SPDIF-TX
PCI Express (PCIE) Yes, 1× TX + 1× RX, embedded 5 Gbit/s PHY
USB 2.0 Host (USBH) 1 port, embedded Hi-Speed PHY
USB 2.0/3.0 Dual Role Yes, embedded Hi-Speed and SuperSpeed
USB (USB3DR)(2) 5 Gbps PHY
Embedded PHYs 3 (2× Hi-Speed + 1x SuperSpeed 5 Gbps)

Type-C support (UCPD) Yes, includes two CC-lines embedded PHY
SPDIFRX 4 inputs
FDCAN Up to 3(1)
SDMMC (SD, SDIO, e•MMC)(2) 3 (8 + 8 + 4 bits).
OCTOSPI(2) 2, with AES-128 (CTR) decryption (OTFDEC)
Parallel address/data 8/16 bits 4× CS, up to 4x 64 Mbytes(1)
FMC Parallel AD-Mux 8/16 bits 4× CS, up to 4x 64 Mbytes(1)
NAND 8/16 bits(2) Yes, 4 x CS, SLC, BCH4/8(1)
Gigabit Ethernet interfaces Up to 3(1)

Up to 314 MHz pixel clock (when used with DSI
-
or LVDS)
LCD-TFT (LTDC)
Up to 24-bits 150 MHz pixel clock (up to
Parallel interface
1080p60)
Display serial interface (DSI) 4× data lanes 2.5 Gbit/s each (up to 1536p60)(1)
Up to dual-link of 4× data lanes 1.1 Gbit/s each
LVDS display interface (LVDS)
(up to 1536p60)(1)
- CSI-2 + RGB/RawBayer parallel
2× data lanes 2.5 Gbit/s each, path shared with
CSI-2 serial (CSI + DCMIPP)
DCMIPP
Camera interface
Parallel RGB/RawBayer (DCMIPP) Up to 120 MHz, path shared with CSI.
Image signal processing (ISP) Yes, embedded inside DCMIPP
Parallel RGB (DCMI) Up to 80 MHz
DS14284 - Rev 2 page 8/234

Description
16-bit input or output, path shared with DCMI

Parallel interface (PSSI)
and DCMIPP
HPDMA 3 instances, 48 physical channels in total
LPDMA 1 instance, 4 physical channels
DES/TDES (ECB, CBC), AES-256 (ECB, CBC,
CRYP (two instances)
CTR, GCM, GMAC, CCM)
AES-256 (ECB, CBC, CTR, GCM, GMAC,
Cryptography Secure AES (SAES) CCM), hardware attack protections, keys
sharing to CRYP
Public key primitives for RSA, DH, and ECC
Public key accelerator (PKA)
over GF(p). 64-bit core
SHA-1, SHA-2 and SHA-3 (up to 512), MD5,
Hash (HASH)
HMAC
True-RNG. FIPS 140-2 NDRNG (NIST
Random number generator (RNG)
SP800-90B certifiable)
Fuses (one-time programming) 12288 effective bits
Multi-function digital filter (MDF) 8 input channels with 8 filters

1 input channel with 1 filter and sound-activity
Audio digital filter (ADF)
detection
with interrupt (total count) Up to 172(1)
GPIOs Wake-up pins Up to 6(1)
Tamper input/active output pins Up to 8 inputs and 8 outputs(1)

Up to 12 bit ADC 3 (up to 5 Msps each)
ADC channels in total (differential) Up to 23 channels (or 11 differential)(1)

- VREF generation (VREFBUF) 1.21 V, 1.5 V, or VREF+ input
VREF+ input pin Yes
1. See next tables for details.

2. Can be a boot source.
Table 2. STM32MP25xC/F differences per product lines
Feature STM32MP251x STM32MP253x STM32MP255x STM32MP257x
Cortex-A35 FPU Neon TrustZone Single-core Dual-core

L1 data +
32 + 32 Kbytes 2 x (32 + 32) Kbytes
Cache size instruction
CPU
L2 unified 512 Kbytes 512 Kbytes
STM32MP25xC Up to 1200 MHz
Frequency
STM32MP25xF Up to 1500 MHz
VeriSilicon GC8000UL -
For 3D graphics No
Open GL ES 3.2.8 - Vulkan 1.2
GPU 800 MHz, up to 133 Mtriangle/s or

STM32MP25xC -
Performance(1) / 800 Mpixel/s
frequency 900 MHz, up to 150 Mtriangle/s or
STM32MP25xF -
900 Mpixel/s
VeriSilicon GC8000UL - TensorFlowLite
For AI processing No
- ONNX - Linux NN
NPU
Performance(1) / STM32MP25xC - 800 MHz, 1.2 TOPS
frequency
DS14284 - Rev 2 page 9/234

Description
Feature STM32MP251x STM32MP253x STM32MP255x STM32MP257x

Performance(1) /
NPU STM32MP25xF - 900 MHz, 1.35 TOPS
frequency
Decoder (VDEC) No H264/VP8 up to 1080p60 - JPEG 500
Video Encoder (VENC) No Mpixel/s(2)
Frequency - 600 MHz

128 Kbytes, shared between VDEC and
Video RAM No
Embedded SRAM VENC(3)
CPU system 256 + 128 Kbytes 256 Kbytes(3)

Timers A35 (CNT) 64 bits 4 (S, NS, V, H) 2x 4 (secure, non-secure, Virtual, Hypervisor)
FDCAN No 3 (1x TT-FDCAN), 10-Kbyte shared buffer
Gigabit External interfaces 1, R(G)MII, MII 2, R(G)MII, MII 3, R(G)MII

Ethernet GMAC (ETH), TSN, PTP, EEE 1 2
interfaces 3 ports Gigabit Switch (ETHSW) No No No 2 external ports
4× data lanes 2.5 Gbit/s each (up to
Display serial interface (DSI) No
1536p60)
Up to dual-link of 4x data lanes 1.1

LVDS display interface (LVDS) No
Gbit/s each (up to 1536p60)(4)
1. GPU and NPU share performance.

2. This is the performance of either VDEC or VENC running alone. VDEC and VENC share performances as they are using
same video RAM.
3. If neither VDEC nor VENC are used, the video RAM can be used as general purpose memory, thus giving a total of 384
Kbytes for CPU system.
4. Single or dual-link depends on the package (see next table for details).
Table 3. STM32MP25xC/F differences per packages
STM32MP25xxAL STM32MP25xxAK STM32MP25xxAI

Features
VFBGA361 VFBGA424 TFBGA436
Body size (mm) 10×10 14×14 18×18

Pitch (mm) 0.5 0.5 0.8
Packages
Thickness (mm) 1 1 1.2
Ball count 361 424 436
- Up to 2 x 4.8 Gbytes/s internal buses . AES-128 encryption/decryption
16 bits 1066 MHz Up to 1 Gbyte, single rank
DDR3L
32 bits 1066 MHz - Up to 2 Gbytes, single rank
16 bits 1200 MHz Up to 4 Gbytes, single rank
SDRAM DDR4
32 bits 1200 MHz - Up to 4 Gbytes, single rank
16 bits 1200 MHz Up to 2 Gbytes, single rank
LPDDR4 Up to 4 Gbytes, single rank two channels in parallel
32 bits 1200 MHz -
(lockstep)
Parallel address.data 8/16-bits - 4× CS, up to 4× 64 MBytes
FMC Parallel AD-mux 8/16-bits 4× CS, up to 4× 64 MBytes
NAND 8/16-bits (1) Yes, 4× CS, SLC, BCH4/8
Single-link of 4× data
Dual-link of 4× data lanes 1.1 Gbit/s each (up to
LVDS display interface (LVDS) lanes 1.1 Gbit/s each (up
1536p60)(2)
to 1080p60) (2)
DS14284 - Rev 2 page 10/234

Description
STM32MP25xxAL STM32MP25xxAK STM32MP25xxAI

Features
VFBGA361 VFBGA424 TFBGA436
with interrupt (total count) 144 144 172

GPIO Wakeup pins 6 6 6
Tamper input/active output pins 8+8 8+8 8+8
ADC channels in total
ADC 23 (11)(3) 21 (10) 23 (11)(3)
(differential)
1. Can be a boot source.

2. Availability depends on device.
3. Including 2 (or 1 differential) low-noise inputs on dedicated ANA0/ANA1 pins.
DS14284 - Rev 2 page 11/234

Description
Figure 1. STM32MP25xC/F block diagram
@VDD_ANA/VDD_PLL
@VDDCPU CA35SS Device supplies
HSI (64 MHz RC) PLL4/5/6/7/8 HSE (XTAL) 2
Cortex-A35 CPU @VDDGPU
1.5 GHz + MMU GPU + NPU
128KB
600 MHz
+ FPU + NEON
async
IWDG1 HDP 8
L2$
128 bits 900 MHz 8b
512 KB L2$ + SCU

32 KB D$ PLL3
IWDG2 SERC
APB3 (200 MHz)

32 KB I$
600 MHz
async
GIC 128 bits VENC 600 MHz IWDG3 DTS (temp sensor)
600 MHz
Cortex-A35 CPU
1.5 GHz + MMU Boot ROM VDEC 600 MHz IWDG4 BSEC OTP fuses
@VDDA18
AON
+ FPU + NEON 128 KB @VDDA
RI VDERAM 128 KB WWDG1 VREFBUF 1
400 MHz
32 KB D$
RI SYSRAM 256 KB Trace port 16b 17
MLAHB: Arm 32-bit multi-AHB bus matrix (200 MHz)

32 KB I$
200 MHz 200 MHz

CNT (timer)
FIFO
PLL1 STM RCC 7
PTM
EXTI1
600 MHz 200 MHz
16ext 176
async
T interconnect (600/300/400/200 MHz)
78 DDRPHYC BOOT
RI PLL2 DDR SYSCFG pins 4
IPCC1
async
MCE
DDRCTRL @VDDA
12b ADC1 18
LPDDR4 DDR3L DDR4 CRC
ITF
@VDDIO1 12b ADC2 14
6 4b
DLYB
SDMMC1 RAMCFG
SD1
ADC3 14
ITF
4b 12b
8 @VDDIO3
10
@VDDIO2
PKA GPIOA 16
200 MHz
8b
DLYB
SDMMC2
SD2
4 @VDDIO2
CRYP1 GPIOB 16
6 4b
DLYB
SDMMC3
SD3
4
Shared keys SAES GPIOC 14
200 MHz 400 MHz
40 16b FMC RI CRYP2 GPIOD 16

RNG
MII RGMII
(R/RG) RMII /
16 ETHSW (TSN) GPIOE 16

128/64-bit STNoC
18 ETH1 GMAC (TSN) HASH GPIOF 16

300 MHz
HPDMA1
(R/RG)
18 ETH2 GMAC (TSN)

FIFO
FIFO
MII
GPIOG 16
16 streams
REFGEN
200 MHz
HPDMA2 GPIOH 14
FIFO
FIFO
2
200 MHz
PCIE RI
16 streams
HPDMA3 GPIOI 16
FIFO
FIFO
SERDES
7 COMBOPHY
PHY
or PLL
16 streams
GPIOJ 16
300 MHz
@VDDxx
MLAHB: Arm 32-bit multi-AHB bus matrix (400 MHz)
400 MHz
2 USB3DR
GPIOK 8
USB2 USB2
PHY1 PHY2
4
PLL
(USB2.0/3.0 Dual Role Data)

@VDDxx Debug timestamp
generator TSGEN OTFDEC1
3
PLL
300 MHz 200 MHz 300 MHz
@VDDIO3
USBH (Host)
200 MHz
DLYB DLYB
DAP OCTOSPI1
OS2 OS1
RI 8b 13
2 (USB2.0 OHCI/EHCI)
(JTAG / SWD)
RI OCTOSPI2 8b 13
Cortex-M33 CPU
UCPD
PHY
2 UCPD1 (USB Type-C) S-Bus @VDDIO4

400 MHz + MPU OTFDEC2
19 DCMIPP or ISP + FPU D-Fetch OCTOSPIM
PHY
6 CSI I-Fast MDF1 8ch 18

300 MHz
16KB D$
FIFO
31 24b LTDC (LCD) DCMI

16KB I$ I-Slow FIFO 14b
(// camera)
PLL
PHY PHY PHY
DSI
10@V DSI NVIC 19

PSSI
FIFO
APB4 (200MHz)
DDxx
DAP Bus
16b
10 SYSTICK (// I/O)
LVDS
PLL
LVDS DDRPERFM Smartcard

FIFO
10@V USART1 IrDA 5

DDxx SRAM1 128 KB RI
STGENC STGEN Smartcard
FIFO
(system timer
USART6 IrDA 5
SRAM2 128 KB RI
STGENR generator)
FIFO
@VSW
UART7 4
ECC
2 LSE (32 kHz XTAL) LSI (32 kHz RC) RETRAM 128 KB RI
FIFO
UART8 4
ECC
2 RTC IWDG5 BKPSRAM 8 KB RI

FIFO
UART9 4
8
TAMP / Backup registers
8 MLAHB (200/16 MHz) PWR 10
LPSRAM1 8 KB RI
2 M0P SWD
Cortex-M0+ CPU @VDD_ANA/VDD/VSW TIM1 / PWM 16b 10
200/16 MHz Voltage regulators
APBSR (200/16 MHz)
3 I2C8 / SMBUS TIM8 / PWM 16b 10
2 I3C4 Supply supervision TIM15 16b 4

MLAHB (200/16 MHz)
FIFO
5 SPI8 NVIC Resource isolation TIM16 16b 3

APB1 (200 MHz)
@VD3 SYSTICK framework (RIF)

4 LPUART1 RI TIM17 16b 3
APB2 (200 MHz)
MSI (4/16 MHz RC)

4 16b LPTIM3 TIM20 / PWM 16b 10
64 bits AXI
LPDMA1 (4 streams)
FIFO
4 16b LPTIM4 SPI1 / I2S1 6

64bits AXI master
RI LPSRAM2 8 KB
FIFO
3 16b LPTIM5 SPI4 5

32 bits AHB
RI LPSRAM3 16 KB
FIFO
WWDG2 SPI5 5
32 bits AHB master
HSEM
FIFO
176 16ext EXTI2 SPI6 5

32 bits APB
IPCC2
FIFO
2 1ch ADF1 SPI7 5

Option - not present in
all devices
FIFO
10 GPIOZ SAI1 13
SAI2
FIFO
APB1 (200 MHz) 8

FIFO
SAI3 8
FIFO FIFO FIFO FIFO FIFO FIFO FIFO
FIFO
SAI4 13
I2C1 / SMBUS
I2C2 / SMBUS
I2C3 / SMBUS
I2C4 / SMBUS
I2C5 / SMBUS
I2C6 / SMBUS
I2C7 / SMBUS
SPI2 / I2S2
SPI3 / I2S3
CCU
SPDIFRX
USART2
USART3
LPTIM1
LPTIM2
UART4
UART5
TIM10
TIM12
TIM13
TIM14
TIM11
FDCAN1 (TT) 2
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
I3C1
I3C2
I3C3
FDCAN2 2
FDCAN3 2
Smartcard
Smartcard
CANSRAM (10 KB)

32b
32b
32b
32b
16b
16b
16b
16b
16b
16b
16b
16b
16b
IrDA
IrDA
4ch
Filter Filter Filter Filter Filter Filter Filter

DT69000V3
5
DS14284 - Rev 2 page 12/234

Functional overview
3 Functional overview
3.1 Dual-core Arm Cortex-A35 subsystem (CA35SS)

Note: Features may be limited or absent in some devices or packages (see Section 2 for details).
3.1.1 Features
• Armv8-A architecture
• AArch32 for full backward compatibility with Armv7
• AArch64 for 64-bit support and new architectural features
• 32-Kbyte L1 instruction cache for each CPU
• 32-Kbyte L1 data cache for each CPU
• 512-Kbyte level2 cache
• Arm A64 + A32 + Thumb-2 instruction set
• Arm TrustZone security technology
• Arm NEON advanced SIMD
• DSP and SIMD extensions

• VFPv4 floating-point
• Hardware virtualization support
• Performance monitoring Uuit (PMU)
• Program trace macrocell (PTM) that supports instruction trace only
• Integrated generic interrupt controller (GIC) with 384 shared peripheral interrupts
• Integrated generic timer (CNT)
Note: The cryptographic extension is not supported.
3.1.2 Overview
The Cortex-A35 processor uses a highly-efficient 8-stage in-order pipeline that has been extensively optimized to
provide full Armv8-A features while maximizing area and power efficiency.
3.1.2.1 Thumb-2 technology

Delivers the peak performance of traditional Arm code, while also providing up to a 30 % reduction in memory
requirement for instructions storage.
3.1.2.2 TrustZone technology

Ensures reliable implementation of security applications ranging from digital rights management to electronic
payment. Broad support from technology and industry partners.
3.1.2.3 PMU
The PMU provides six performance monitors that can be configured to gather statistics on the operation of each
core and the memory system. The information can be used for debug and code profiling.
3.1.2.4 NEON and FPU

Advanced SIMD is a media and signal processing architecture that adds instructions primarily for audio, video,
3‑D graphics, image, and speech processing. The floating-point architecture provides support for single-precision
and double-precision floating-point operations.
All scalar floating-point instructions are available in the A64 instruction set. All VFP instructions are available in
A32 and T32 instruction sets. The same advanced SIMD instructions are available in both A32 and T32
instruction sets. The A64 instruction set offers additional advanced SIMD instructions, including double-precision
floating-point vector operations.
DS14284 - Rev 2 page 13/234

Functional overview
3.1.2.5 Hardware virtualization

Highly-efficient hardware support for data management and arbitration, whereby multiple software environments
and their applications are able to simultaneously access the system capabilities. This enables the realization of
devices that are robust, with virtual environments that are well isolated from each other.
3.1.2.6 Optimized L1 caches

Performance and power optimized L1 caches combine minimal access latency techniques to maximize
performance and minimize power consumption. There is also the option of cache coherence for enhanced inter-
processor communication, or support of a rich SMP capable OS for simplified multicore software development.
3.1.2.7 Integrated L2 cache controller

Provides low-latency and high-bandwidth access to cached memory in high-frequency, or to reduce the power
consumption associated with off-chip memory access.
3.1.2.8 Snoop control unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cachetocache and system
memory transfers, cache coherence and other capabilities for the processor.
This system coherence also reduces software complexity involved in maintaining software coherence within each
OS driver.
3.1.2.9 Generic interrupt controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach
to inter-processor communication, and the routing and prioritization of system interrupts.
Supporting up to 416 independent interrupts (including 384 shared interrupt), under software control, each
interrupt can be distributed across Cortex‑A35 cores, hardware prioritized, and routed between the operating
system and TrustZone software management layer.
This routing flexibility and the support for virtualization of interrupts into the operating system, provide one of the
key features required to enhance the capabilities of a solution utilizing an hypervisor.
3.2 Arm Cortex-M33 core with TrustZone and FPU (CM33)

The Arm Cortex-M33 core with TrustZone and FPU is a 32-bit RISC processor that features exceptional code-
efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with
8- and 16-bit devices.
It is comprise of:
• Arm TrustZone technology, using the Armv8-M main extension supporting secure and non-secure states
• floating-point extension (FPU)
• Armv8-M DSP extension
• a nested vectored interrupt controller (NVIC) closely integrated with the processor
• a memory system with memory protection unit (MPU) with up to 16 non-secure regions and 16 secure
regions
• a security attribution unit (SAU) with up to 8 regions
• an implementation defined attribution unit (IDAU)
• debug components including breakpoints (BPU), data watchpoints (DWT), instrumentation and processor
trace (ITM/ETM), cross trigger interface (CTI)
• 16-Kbyte instruction and 16-Kbyte data caches (ICACHE/DCACHE)
3.3 Arm Cortex-M0+ core (CM0P)

The Cortex-M0+ processor is built on a highly area- and power-optimized 32bit core, with a 2-stage pipeline Von
Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful
instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle
multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a
higher code density than other 8bit and 16bit microcontrollers.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
DS14284 - Rev 2 page 14/234

Functional overview
3.4 Graphic processing unit (GPU)

STM32MP25xC/F devices include a 3D graphics engine (VeriSilicon GC8000UL).
The GPU is a dedicated graphics processing unit accelerating numerous 3D graphics applications such as
graphical user interface (GUI), menu display or animations. It works together with an optimized software stack
design for industry-standard APIs with support for Android™ and Linux® embedded development platforms.
The GPU is used to accelerate parallel computing (GPGPU), via the typical OpenCL or Vulkan API, or more
image-based API like OpenVX or OpenCV. This wide support guarantees to be able to accelerate any application
up to the most recent ones, with graphic performances reaching 25.6 GFlops.
The GPU is built in a separate power domain, which allows the GPU to be switched off when not used in the long-
term, or even to play with dynamic voltage frequency scaling (DVFS).
The GPU graphic hardware acceleration is exposed through the following API:
• OpenVG 1.2 for 2D or curve drawing
• OpenGL/ES 3.1 for 3D apps (backward compatible: OES2.1 and OES1.1)
• Vulkan 1.3 for modern 3D apps
• OpenCL 3.0 for parallel programming
• OpenVX 1.3 for acceleration of computer vision applications
The GPU provides the following graphic theoretical performance (values for 800 MHz):
• Vertex: 200 MVtx/s
• Triangle: 133 MTrg/s
• Texel: 800 MTex/s
• Pixel: 800 MPix/s
• Float 16bit: 25.6 GFlops
• Float 32bit: 12.8 GFlops
3.5 Neural processor unit (NPU)

The NPU provides powerful hardware acceleration for neural network, to allow efficient artificial intelligence (AI)
applications.
The NPU acceleration is implemented by hardware neural operator inserted into the GPU. As such, it benefits of
both optimized hardware (the neural operator), and of the flexibility and efficiency of the existing GPU shaders.
The NPU neural hardware acceleration is exposed through the following API:
• TensorFlowLite-API
• ONNX
• Linux NN-API-Adapter
The NPU flexibility is used to optimally accelerate the following frameworks (nonexhaustive list)
• TensorFlow non-exhaustive hardware support
• TensorFlowLite full hardware support (including its SoftMax subset)
• Caffe, Caffe2
• CNTK, Torch, Theano, Darknet
The NPU provides the following neural theoretical performance, below values for 800 MHz (values for 900 MHz
overdrive inside parenthesis):
• Integer operations: 1.2 (1.35) TOPS (8-bit integer)
To reduce the required DDR bandwidth during neural computations, the NPU embeds natively 128 Kbytes of
memory.
3.6 Memories
3.6.1 External SDRAM

STM32MP25xC/F devices embed a controller for the external SDRAM which supports the following devices
DS14284 - Rev 2 page 15/234

Functional overview
• DDR3L, 16- or 32-bit data, up to 2 Gbytes, up to DDR3L-2133 (1066 MHz clock)

• DDR4, 16- or 32-bit data, up to 4 Gbytes, up to DDR4-2400 (1200 MHz clock)
• LPDDR4, 16- or 32-bit data, up to 4 Gbytes, up to LPDDR4-2400 (1200 MHz clock)
3.6.2 Embedded SRAM

All devices feature:
• SYSRAM in MPU domain: 256 Kbytes with half/full hardware erase mechanism on reset
• VDERAM in MPU domain: 128 Kbytes (not usable when either VDEC or VENC is used) with hardware
erase mechanism on enable as general purpose RAM
• SRAM1 in MCU domain: 128 Kbytes with hardware erase mechanism on tamper detection
• SRAM2 in MCU domain: 128 Kbytes
• LPSRAM1 in SmartRun domain: 8 Kbytes with hardware erase mechanism on reset
The content of this area can be retained in Standby or VBAT mode, and can be protected by the CRC
mechanism.
• LPSRAM2 in SmartRun domain: 8 Kbytes with hardware erase mechanism on reset
• LPSRAM3 in SmartRun domain: 16 Kbytes
• RETRAM (retention RAM): 128 Kbytes with hardware erase mechanism on reset
The content of this area can be retained in Standby or VBAT mode, and can be protected by ECC and CRC
mechanisms.
• BKPSRAM (backup SRAM): 8 Kbytes with hardware erase mechanism on tamper detection
The content of this area can be protected against possible unwanted accesses, and can be retained in
Standby or VBAT mode. The content can also be protected by ECC mechanism.
3.7 DDR3L/DDR4/LPDDR4 controller (DDRCTRL)

DDRCTRL combined with DDRPHYC provides a complete 16 /32-bit memory interface solution for DDR memory
subsystem.
• JEDEC compliant LPDDR4 SDRAM up to 2400 MT/s
• JEDEC compliant DDR4 SDRAM up to 2400 MT/s with DLL on-range
• JEDEC compliant DDR3L SDRAM up to 2133 MT/s with DLL on-range
• 2 x 128-bit AXI4 ports
– up to 16 QoS levels and up to 3 traffic classes are supported per direction.
– CID-based firewalling function with poisoning output signaling
– 1 port provided with AES- 128 encryption/decryption with programmable memory range (DDRMCE)
Low-power features:
• Linked with the RCC, ability to move the DDR memory subsystem in self refresh through automatic way,
hardware way, or software way (ASR, HSR and SSR).
3.8 Boot modes

At startup, the boot source used by the internal boot ROM is selected by BOOT pins and OTP settings.
Table 4. Default interfaces

Unless otherwise mentioned in table below.
Boot source When used by Cortex-A35 When used by Cortex-M33
SD-Card SDMMC1
e•MMC SDMMC2
Serial NOR, HyperFlash and serial NAND OCTOSPIM port1 OCTOSPIM port2
SLC NAND FMC
USB USB3DR (high-speed only) -
DS14284 - Rev 2 page 16/234

Functional overview
Boot source When used by Cortex-A35 When used by Cortex-M33
UART USART2/6 and UART5/8/9 -
Table 5. Boot sources
Alternate boot pins OTP value
BOOT[3:0] 0b00 (default) 0b01 0b10 0b11

pins Cortex-M33 master (1) Cortex-M33 master (1)
Cortex-A35 Cortex-M33 Cortex-A35 Cortex-M33
master master Cortex-A35 Cortex-M33 master master Cortex-A35 Cortex-M33
0 UART and USB(2) (3)

1 SD-Card - - - SD-Card SD-Card Serial NAND Serial NOR
2 e•MMC - - - e•MMC e•MMC e•MMC Serial NOR
3 Development boot(2)
4 Serial NOR - - - Serial NOR Serial NOR SLC NAND Serial NOR
5 Serial NAND - - - - - e•MMC(4) Serial NOR

6 SLC NAND - - - - - e•MMC(4) HyperFlash™
7 - SD-Card - - HyperFlash™ HyperFlash™ Serial NAND HyperFlash™
8 - e•MMC - - Serial NAND Serial NAND e•MMC HyperFlash™

Serial
9 - - Serial NOR - - SD-Card(5) Serial NOR
NAND
10 - - SLC NAND Serial NOR - - SD-Card(5) HyperFlash™
11 - Serial NOR - - SLC NAND SLC NAND SLC NAND(6) HyperFlash™
12 Development boot(2)
13 - - e•MMC Serial NOR SD-Card(5) SD-Card(5) SD-Card Serial NOR
14 - - SD-Card Serial NOR e•MMC(4) e•MMC(4) SD-Card HyperFlash™
15 UART and USB(3)
1. Two flash memory config. Indirect Cortex-A35 boot (from Cortex-M33) or used during Cortex-A35 D1Standby exit
2. Cannot be override by OTP.
3. Wait incoming connection on USART2/6 or UART5/8/9 on default pins and USB high-speed device on USB3DR_DP/DM.
4. e•MMC on SDMMC1
5. SD-Card on SDMMC2
6. Only 8-bit memory is supported as some FMC and OCTOSPIM port2 pins are shared (usage of FMC in 16-bit mode is exclusive of usage of
OCTOSPIM port2).
The default pins used during boot are described in Table 6 .

Note: There is few mutual exclusions with this default settings. SDMMC2 cannot be used with FMC. OCTOSPI Port2
cannot be used with FMC 16 bits. OCTOSPI port2 in 8-bit mode cannot be used with FMC.
DS14284 - Rev 2 page 17/234

Functional overview
Table 6. Minimum set of default pins used during boot ROM phase
Most can be changed using OTP settings. This table is for default OTP settings.
Interface type Signal Pin IO supply domain
FMC_NOE PE15
FMC_RNB PE13
FMC_NWE PE14
FMC_NCE1 PE12
FMC_ALE PE8 VDDIO2(1)
SLC NAND 8-bits
FMC_CLE PE11
FMC_D0 PE9
FMC_D1 PE6
FMC_D2 PE7
SLC NAND 16-bits
FMC_D3 PD15
FMC_D4 PD14
FMC
FMC_D5 PB13 VDD
FMC_D6 PD12
FMC_D7 PB14
FMC_D8 PB5
FMC_D9 PB6 VDDIO4(2)
FMC_D10 PB7
FMC_D11 PD13 VDD

-
FMC_D12 PB8
FMC_D13 PB9
VDDIO4(2)
FMC_D14 PB11
FMC_D15 PB10
OCTOSPIM_P1_CLK PD0
Serial NAND
Serial NOR,
OCTOSPIM_P1_NCS1 PD3
OCTOSPIM_P1_IO0 PD4
OCTOSPIM_P1_IO1 PD5
OCTOSPIM_P1_IO2 PD6
HyperFlash™
OCTOSPI OCTOSPIM_P1_IO3 PD7 VDDIO3

M Port1
OCTOSPIM_P1_IO4 PD8
OCTOSPIM_P1_IO5 PD9
-
OCTOSPIM_P1_IO6 PD10
OCTOSPIM_P1_IO7 PD11
OCTOSPIM_P1_NCLK PD1
OCTOSPIM_P1_DQS PD2
OCTOSPIM_P2_CLK PB10
Serial NAND
HyperFlash™
Serial NOR,
OCTOSPIM_P2_NCS1 PB8
OCTOSPI
OCTOSPIM_P2_IO0 PB0 VDDIO4(2)
M Port2
OCTOSPIM_P2_IO1 PB1
DS14284 - Rev 2 page 18/234

Functional overview
Interface type Signal Pin IO supply domain
OCTOSPIM_P2_IO2 PB2
OCTOSPIM_P2_IO3 PB3
OCTOSPIM_P2_IO4 PB4
HyperFlash™
OCTOSPI OCTOSPIM_P2_IO5 PB5
- VDDIO4(2)
M Port2
OCTOSPIM_P2_IO6 PB6
OCTOSPIM_P2_IO7 PB7
OCTOSPIM_P2_NCLK PB11
OCTOSPIM_P2_DQS PB9
SDMMC1_CK PE3
SDMMC1 SD-Card or eMMC SDMMC1_CMD PE2 VDDIO1
SDMMC1_D0 (3) PE4
SDMMC2_CK PE14
SDMMC2 SD-Card or eMMC SDMMC2_CMD PE15 VDDIO2(1)

SDMMC2_D0(3) PE13
USART2_RX PA8
USART2 VDD
USART2_TX PA4
UART5_RX PB15
UART5 VDD
UART5_TX PA0
USART6_RX PF4
USART6 VDD
USART6_TX PF5
UART8_RX PF3
UART8 VDD
UART8_TX PG3
UART9_RX PB14
UART9 VDD
UART9_TX PD13
1. Some FMC and SDMMC2 pins are shared, this means that usage of FMC is exclusive of usage of SDMMC2.
2. Some FMC and OCTOSPIM port2 pins are shared, this means that usage of FMC in 16-bit mode is exclusive of usage of OCTOSPIM Port2.
3. Only used as input by boot ROM
Although low-level boot is done using internal clocks, ST supplies software packages as well as major external
interfaces (such as DDR or USB) require a crystal or an external oscillator to be connected on HSE pins.
See the product reference manual for constrains and recommendations regarding connection of HSE pins and
supported frequencies.
3.9 Power supply management (PWR)

3.9.1 Power supply scheme

The system requires supply on VDD, VDDA18AON, VDDCPU and VDDCORE to start, and to allow independent
supplies for VDDGPU, VDDA18ADC, VBAT, VDD33USB, VDD33UCPD, VDDIO2, VDDIO3, VDDIO4, VDDIO1, and VDDQDDR.
• VDD power supply input for I/Os (1.8 V or 3.3 V typical)
• VDDA18AON power supply input for system analog such as reset, power management, oscillators and OTP
• VBAT optional power supply input for backup domain, and optionally D3 domain when VDD is not present
(VBAT mode)
DS14284 - Rev 2 page 19/234

Functional overview
• VDDCORE digital core domain supply, dependent on VDD supply. VDD must be present before VDDCORE.
– VDDCSI, VDDDSI, VDDLVDS, VDDCOMBOPHY, VDDCOMBOPHYTX, and VDDPCIECLK are usually connected
to VDDCORE.
• VDDCPU digital CPU domain supply (Cortex-A35), dependent on VDD supply. VDD must be present before
VDDCPU.
• VDDGPU digital GPU domain supply, dependent on VDD supply. VDD must be present before VDDGPU.
• VDDQDDR DDR I/O supply
• VDDA18ADC analog power supply input for ADCs and voltage reference buffers, independent from any other
supply
• VREF+ external reference voltage for ADCs, independent from any other supply
– reference voltage output when the voltage reference buffer is enabled
– independent external reference voltage input when the voltage reference buffer is disabled
• VSSA separate analog and reference voltage ground
• VDD33USB supply input for USB HS PHY, independent from any other supply
• VDD33UCPD supply input for USB Type-C CC1 and CC2 pins, independent from any other supply
• VDDIO3 supply input, mostly for OCTOSPIM_P1 I/Os, independent from any other supply
• VDDIO4 supply input, mostly for OCTOSPIM_P2 I/Os, independent from any other supply
• VDDIO2 supply input, mostly for e.MMC I/Os, independent from any other supply
• VDDIO1 supply input, mostly for SD Card I/Os, independent from any other supply
• VSS common ground for all supplies except for analog
3.9.2 Power-supply supervisor

The devices have an integrated power-on reset (POR) and power-down reset (PDR) circuitry, coupled with a
brownout reset (BOR) circuitry:
• Power-on reset (POR)
The POR supervisor monitors VDD and VDDA18AON power supplies, and compares them to a fixed
threshold. The devices remain in reset mode when VDD and VDDA18AON are below this threshold.
• Power-down reset (PDR)
The PDR supervisor monitors VDD and VDDA18AON power supplies. A reset is generated when VDD or
VDDA18AON drops below a fixed threshold.
• Brownout reset (BOR)
The BOR supervisor monitors VDD power supply. A 2.7 V BOR thresholds can be enabled through option
bytes. A reset is generated when VDD drops below this threshold. The BOR must not be enabled when
VDD = 1.8 V typ. is used.
• Power-on reset VDDCORE (POR_VDDCORE)
The POR_VDDCORE supervisor monitors VDDCORE power supply, and compares it to a fixed threshold.
The VDDCORE domain remains in reset mode when VDDCORE is below this threshold,
• Power-down reset VDDCORE (PDR_VDDCORE)
The PDR_VDDCORE supervisor monitors VDDCORE power supply. A VDDCORE domain reset is generated
when VDDCORE drops below a fixed threshold.
• Power-on reset VDDCPU (POR_VDDCPU)
The POR_VDDCPU supervisor monitors VDDCPU power supply, and compares it to a fixed threshold. The
VDDCPU domain remains in reset mode when VDDCPU is below this threshold.
• Power-down reset VDDCPU (PDR_VDDCPU)
The PDR_VDDCPU supervisor monitors VDDCPU power supply. A VDDCPU domain reset is generated when
VDDCPU drops below a fixed threshold.
• Power-on reset VSW (POR_VSW)
The POR_VSW supervisor monitors VSW power supply, and compares it to a fixed threshold. The VSW
domain remains in reset mode when VSW is below this threshold.
The devices also include monitoring which can generate tamper events, interrupt, or wake-up:
DS14284 - Rev 2 page 20/234

Functional overview
• Programmable voltage detector (PVD)

The PVD monitors the PVD_IN pin, and compares it to a fixed threshold. An interrupt or a wake-up can be
generated when PVD_IN is below or above the threshold.
• VDDCORE monitoring
Monitors VDDCORE power supply and compares it to a fixed threshold. A tamper event, an interrupt, or a
wake-up can be generated when VDDCORE is below or above the threshold.
• VDDCPU monitoring
Monitors VDDCPU power supply, and compares it to a configurable threshold. A tamper event, an interrupt,
or a wake-up can be generated when VDDCPU is below or above the threshold.
• VDDGPU monitoring
Monitors VDDGPU power supply and compares it to a configurable threshold. An interrupt or a wake-up can
be generated when VDDGPU is below or above the threshold. A GPU reset is also generated if VDDGPU is
below the threshold (VDDGPURDY = 0).
• Peripheral voltage monitoring
Monitors independently VDDIO2, VDDIO3, VDDIO4, VDDIO1, VDD33UCPD, VDD33USB and VDDA18ADC power
supplies with fixed thresholds. An interrupt or a wake-up can be generated when supplies are below or
above the thresholds.
3.10 Low-power strategy

Several low-power modes are available to save power when the Cortex-A35 and/or the Cortex-M33 do not need
to execute code (when waiting for an external event). It is up to the user to select the mode that gives the best
compromise between low-power consumption, short startup time, and available wake-up sources.
• Slowing down system clocks (see RCC section in the reference manual)
• Controlling individual peripheral clocks (see RCC section in the reference manual)
• Low-power modes:
– CSleep (CPU clock stopped)
– CStop (CPU subsystem clock stopped)
– D1 DStop1 (CPU subsystem clock stopped, normal mode signaled to external regulator)
– D1 DStandby (domain power down and wake-up via reset)
– Stop1, LP-Stop1, and LPLV-Stop1 (system clock stalled, normal or low-power mode signaled to
external regulator supplying the VDDCPU and the VDDCORE)
– Stop2, LP-Stop2, and LPLV-Stop2 (system clock stalled, powered down mode signaled to external
regulator supplying the VDDCPU, and normal or low-power mode signaled to external regulator
supplying the VDDCORE)
– Standby1 (system powered down and D3 domain in autonomous mode running with local clocks)
– Standby2 (system powered down, D3 domain also in power down)
3.11 Resource isolation framework (RIF)

The RIF is a comprehensive set of hardware blocks designed to enforce and manage the isolation of STM32
hardware resources like memory and peripherals.
Within a defined hardware execution compartment (eight are available), privileged, unprivileged, secure, and non-
secure application softwares can assign their own embedded memory buffers, external memory regions, and
peripherals thanks to the RIF hardware.
The RIF architectural framework extends to FMC, SYSCFG, IPCC, HSEM, DMA, RTC, TAMP, RCC, PWR, EXTI,
or GPIO.
3.12 Reset and clock controller (RCC)

The RCC manages the generation of all clocks, as well as the clock gating and the control of system and
peripheral resets. It provides a high flexibility in the choice of clock sources, and allows application of clock ratios
to improve the power consumption. In addition, on some communication peripherals that are capable to work with
two different clock domains (either a bus interface clock or a kernel peripheral clock), the system frequency can
be changed without modifying the peripheral activity rate.
DS14284 - Rev 2 page 21/234

Functional overview
3.12.1 Features
• RIF aware
• Reset part:
– Generation of local and system reset
– Bidirectional pad reset (NRST) to reset of external devices, or to reset the device
– Output pad reset (NRSTC1MS) to reset of external mass-storage devices used by the Cortex-A35
• Clock generation part:
– Generation and distribution of clocks for the complete system
– 5 separate PLLs (excluding external Cortex-A35, DDRCTRL, and GPU ones):
◦ Integer or fractional mode
◦ Spread-spectrum function to reduce the amount of EMI peaks
◦ Possibility to change on-the-fly the fractional ratios of the PLLs
– Smart clock gating for reduction of power dissipation
– 2 external oscillators:
◦ HSE that supports a wide range of crystals: 16 to 48 MHz
◦ LSE for 32.768 kHz crystals
– 3 Internal oscillators:
◦ HSI that runs around 64 MHz

◦ MSI that runs around 16 MHz or 4 MHz
◦ LSI that runs around 32 kHz
– Buffered clock outputs for external devices
• Two independent interrupt interfaces (one dedicated to Cortex-A35, and one dedicated to Cortex-M33)
• Two independent failure events (HSE and LSE)
• Two independent events to wake up processors (one dedicated to Cortex-A35 and one dedicated to
Cortex-M33)
3.12.2 Clock management

The RCC provides a high flexibility to the application in the choice of the clock generators:
• from HSI, high-speed internal oscillator (~ 64 MHz)
• from HSE, high-speed external oscillator (16 to 48 MHz)
• from LSE; low-speed external oscillator (32 kHz)
• from LSI, low-speed internal oscillator (~ 32 kHz)
• from MSI, low-power internal oscillator (~ 4 MHz or ~ 16 MHz)
The RCC offers a good flexibility for the application to select the appropriate clock for CPUs and peripherals.
More especially for peripherals that need a specific clock like SPI(I2S), SAI, and SDMMC.
Each clock source can be switched on or off independently in order to optimize the power consumption.
There are mainly three clock paths:
• Cortex-A35 bus matrix
• Cortex-M33 and its bus matrix
• peripheral kernel clocks
The Cortex-A35, the GPU, and DDRCTRL clocking are derived locally because of high frequency use. The RCC
manages only source clocks for their related local PLLs.
3.12.3 Reset sources

There are several sources able to generate a reset:
• supply monitors (VDD, VDDCORE, VDDCPU , VDDGPU or VSW) lower than expected values
• independent watchdogs timeout
• D1 domain exit from DStandby state
• exit from Standby mode
• external signals driving the NRST pin
DS14284 - Rev 2 page 22/234

Functional overview
• software commands
The coverage (or scope) of the resets differ according to the source initiating the reset, with the following
categories:
• power-on/off resets
• system resets
• local resets
An application reset can be generated from one of the following sources:
• reset from the NRST pin
• reset from low-voltage detection on VDD
• reset from the independent watchdogs
• software reset from RCC registers
• failure on HSE
• RETRAM CRC or ECC error
A system reset can be generated from one of the following sources:
• reset from application reset
• reset from low-voltage detection on VDDCORE
• a reset from low-voltage detection on VDDCPU
The NRST reset is activated by:

• low voltage on VDD
• failure on HSE
• reset from the independent watchdogs
• software reset from RCC registers
• RETRAM CRC or ECC error
• assertion of NRST by an external source
3.13 Hardware semaphore (HSEM)

The hardware semaphore provides 16 (32-bit) register-based semaphores.
The semaphores can be used to ensure synchronization between different processes that run on a core and
between different cores. The HSEM provides a non-blocking mechanism to lock semaphores in an atomic way.
The following functions are provided:
• Locking a semaphore can be done in two ways:
– 2-step lock: by writing CoreID and ProcessID to the semaphore, followed by a read check.
– 1-step lock: by reading the CoreID from the semaphore
• Interrupt generation when a semaphore is freed
– Each semaphore can generate an interrupt on one of the interrupt lines.
• Semaphore clear protection
– A semaphore is only cleared when CoreID and ProcessID matches.
• Global semaphore clear per CoreID
3.14 Inter-processor communication controller (IPCC1/2)

The IPCC is used to communicate data between two processors. It provides a non-blocking signaling mechanism
to post and retrieve communication data in an atomic way (signaling for 16 channels for IPPC1, and four channels
for IPCC2).
The IPCC communication data must be located in a common memory, which is not part of the IPCC.
3.14.1 Main features

• Status signaling for the four channels
– Channel occupied/free flag, also used as lock
DS14284 - Rev 2 page 23/234

Functional overview
• Two interrupt lines per processor

– One for RX channel occupied (communication data posted by sending processor)
– One for TX channel free (communication data retrieved by receiving processor)
• Interrupt masking per channel
– Channel occupied mask
– Channel free mask
• Two channel operation modes
– Simplex (each channel has its own communication data memory location)
– Half duplex (a single channel in associated to a bidirectional communication data information memory
location)
3.15 General-purpose input/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain, with or without pull-up or
pull-down), as input (with or without pull-up or pull-down), or as peripheral alternate function. Some of the GPIO
pins are shared with digital or analog alternate functions. All GPIOs are high-current-capable and have speed
selection to better manage internal noise, power consumption and electromagnetic emission.
After reset, all GPIOs are in analog mode to reduce power consumption.
The I/O configuration can be locked if needed by following a specific sequence in order to avoid spurious writing
to the I/O registers.

Access to each GPIO configuration bits can be restricted to secure‑only and/or privileged‑only. These
configuration bits can also be allocated to a specific CPU.
3.16 Bus-interconnect matrix

For more details on interconnect, see the reference manual (RM0457).
DS14284 - Rev 2 page 24/234

Functional overview
Figure 2. AXI STNoC multi-frequency network
From MCU 200MHz

400MHz MLAHB
Valid traffic path
USBH (OHCI)
USBH (EHCI)
From MCU
Cortex-A35
GPU / NPU
Secure traffic access path
SDMMC1
SDMMC2
SDMMC3
HPDMA1
HPDMA2
HPDMA3
USB3DR
DCMIPP
Non-secure traffic access path
MLAHB
VENC
VDEC
ETH1
ETH2
LTDC
PCIE
DAP
ETR
Absent on some devices

Async Async
AXI 128 AXI 128 AXI 64 AXI 64 AHB 32 AXI 64 AXI 64 AXI 64 AXI 64 AHB 32 AHB 32 AXI 64 AXI 64 AXI 64 AHB 32 AHB 32 AHB 32 AHB 32 AXI 64 AXI 64 AXI 64 AXI 64
M8 M14 M2 M3 M0 M10 M15 M16 M17 M18 M19 M20 M21 M22 M4 M5 M6 Mxx M9 M11 M12 M13
600 MHz 400 MHz 300 MHz 200 MHz
AXI 128
Sxx
600
MHz DDRCTRL
AXI 128
Sxx
To MCU 400 MHz
AHB32
Sxx
MLAHB (mem)
Sxx
AXI64
SYSRAM
400
MHz
Sxx VDERAM
AXI64
or SYSRAM extension
Sxx
AXI64
FMC
Sxx
AXI64
PCIE (out)
Sxx
AXI64
STM
To MCU 200MHz MLAHB
AHB32
Sxx
(conf)
200
MHz
AHB32
Sxx
Matrix
AHB6
ETHSW
From MCU 200 MHz

MLAHB (conf)
AHB32
Sxx
DT69005V1
MPU AHB / APB
Matrix
AHB5
peripherals
STNoC multi-frequency network From MCU 200 MHz
MLAHB (conf)
Figure 3. MCU multi-Layer AHB 400 MHz
Cortex-M33
From MPU
HPDMA1
HPDMA2
HPDMA3
matrix
DCACHE
ICACHE
Fast Slow
S-Bus
Mxx Mxx Mxx Mxx Mxx Mxx Mxx Mxx
Sxx
SRAM1
Sxx
SRAM2
Sxx
to MPU matrix
Sxx
RETRAM
Sxx OCTOSPI1/2
memory access
Sxx To MCU 200 MHz
MLAHB
Sxx OCTOSPI1/2
registers
DT69002V1
MCU MLAHB 400MHz
DS14284 - Rev 2 page 25/234

Functional overview
Figure 4. MCU multi-Layer AHB 200 MHz
From MPU matrix
400 MHz MLAHB

From MCU
HPDMA1
HPDMA2
HPDMA3
APB3
Mxx Mxx Mxx Mxx Mxx
Sxx
AHB4
Sxx
AHB3
Sxx
AHB2
Sxx
APB1
Sxx
APB2
Sxx
to SmartRun AHB matrix
Sxx
to MPU matrix
Sxx
to AHB6 matrix
Sxx
AHB5
DT69003V1
MCU MLAHB 32-bit 200 MHz
APB4
DS14284 - Rev 2 page 26/234

Functional overview
Figure 5. SmartRun multi-Layer AHB matrix
Cortex-M0+ debug
200 MHz MLAHB
Cortex-M0+
From MCU
LPDMA1
Async
Mxx Mxx Mxx Mxx
Sxx
LPDMA1 registers
Sxx
LPSRAM1
Sxx
LPSRAM2
Sxx
LPSRAM3
Sxx
APB SmartRun
Sxx
PWR
Sxx
Cortex-M0+ Debug
Sxx
IPCC2
Sxx
HSEM
Sxx
EXTI2
Sxx
ADF1
Sxx
GPIOZ
Sxx
to AHB3 RIFSC submatrix
DT69004V3
SmartRun MLAHB 32-bit 200 MHz
3.17 High-performance DMA controllers (HPDMA1/2/3)

• AXI master and AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Per channel event generation
• Per channel interrupt generation
• 16 concurrent DMA channels
• Per channel FIFO
• Linked-list support
• TrustZone support
• Privileged/unprivileged support
• Channel isolation support
DS14284 - Rev 2 page 27/234

Functional overview
3.18 Low-power DMA controller (LPDMA1)

• AHB master
• Memory-mapped data transfers from a source to a destination:
– Peripheral-to-memory
– Memory-to-peripheral
– Memory-to-memory
– Peripheral-to-peripheral
• Autonomous data transfers during Sleep and Stop modes
• Per channel event generation
• Per channel interrupt generation
• 4 concurrent DMA channels
• Linked-list support
• TrustZone support
• Privileged/unprivileged support
• Channel isolation support
3.19 Cortex-M33 nested vectored interrupt controller (NVIC)

The devices embed a NIC that can support up to 320 maskable interrupt channels, not including the Cortex®‑M33
interrupt lines.
• 16 programmable priority levels
• Closely coupled NVIC gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Tail chaining
• Processor context automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
NVIC registers are banked across secure and non-secure states.
The NVIC provides flexible interrupt management features with minimum interrupt latency.
3.20 Cortex-M0+ nested vectored interrupt controller (NVIC)

The devices embeds an NVIC that can support up to 32 maskable interrupt channels, not including the Cortex-
M0+ core interrupt lines.
• 4 programmable priority levels
• Closely coupled NVIC that gives low-latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Early processing of interrupts
• Processing of late arriving, higher-priority interrupts
• Support tail chaining
• Processor context automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This NVIC provides flexible interrupt management features with minimum interrupt latency.
3.21 Extended interrupt and event controller (EXTI1/2)

The EXTI manages individual CPU and system wake-up through configurable and direct event inputs. It provides
wake-up requests to the power control, and generates an interrupt request to the CPU NVIC or GIC, and events
to the CPU event inputs. For each CPU, an additional event generation block (EVG) is needed to generate the
CPU event signal.
The EXTI wake-up requests allow the system to be woken up from Stop mode, and CPUs to be woken up from
CStop and CStandby modes.
DS14284 - Rev 2 page 28/234

Functional overview
The interrupt request and event request generation can also be used in Run mode.
The EXTI also includes the EXTI I/Oport selection.
Each interrupt or event can be set as secure to restrict access to secure software only.
EXTI1 is shared between Cortex-A35 and Cortex-M33 while EXTI2 is shared between all cores.
3.22 Cyclic redundancy check calculation unit (CRC)

The CRC calculation unit is used to get a CRC code using a programmable polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the
scope of the EN/IEC 60335-1 standard, they offer a means of verifying the flash memory integrity.
The CRC calculation unit helps computing a signature of the software during runtime, to be compared with a
reference signature generated at link-time and stored at a given memory location.
3.23 Flexible memory controller (FMC)

The FMC main features are the following:
• Interface with static-memory mapped devices including:
– NOR flash memory
– Static or pseudo-static random access memory (SRAM, PSRAM)
– NAND flash memory with 4-bit/8-bit BCH hardware ECC

• 8-,16-bit data bus width
• Independent chip-select control for each memory bank
• Independent configuration for each memory bank
• Write FIFO
3.24 Octo-SPI memory interface (OCTOSPI1/2)

The OCTOSPI supports two protocols used by most external serial memories such as serial PSRAMs, serial
NAND and serial NOR flash memories, HyperRAMs, and HyperFlash memories:
• Indirect mode: all the operations are performed using the OCTOSPI registers.
• Automatic status-polling mode: the external memory status register is periodically read and an interrupt can
be generated in case of flag setting.
• Memory-mapped mode: the external memory is memory mapped ,and is seen by the system as if it was an
internal memory supporting both read and write operations.
The OCTOSPI supports multiple protocols:
• XSPI protocol and its various flavors (such as XCELLA, OCTABUS, HyperBus™ as defined by memory
providers)
3.25 On-the-fly decoder (OTFDEC1/2)

The OTFDEC is used to decrypt on-the-fly AHB traffic based on the read request address information. Four
independent and non-overlapping encrypted regions can be defined in the OTFDEC.
The OTFDEC uses AES-128 in counter mode to achieve the lowest possible latency. Each time the content of an
encrypted region is changed, the entire region must be re-encrypted with a different cryptographic context (key or
initialization vector). This constraint makes the OTFDEC suitable to decrypt read-only data or code, stored in
external NOR flash memory.
3.26 Octo-SPI I/O manager (OCTOSPIM)

The OCTOSPIM is an internal multiplexer:
• Efficient OCTOSPI pin assignment by allowing pin swapping
• Multiplexing two single-, dual-, quad, or octal-SPI interfaces over the same external bus: interfaces (with for
example different security attributes) share then the same memory, or access two memories embedded in
a multichip package.
DS14284 - Rev 2 page 29/234

Functional overview
3.27 Analog-to-digital converters (ADC1/2/3)

STM32MP25xC/F devices embed three analog-to-digital converters, which resolution can be configured to 12, 10,
or 8 bits. Each ADC shares up to 20 channels, performing conversions in single-shot or scan mode. In scan
mode, an automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
• simultaneous ADC1/ADC2 conversion
• interleaved ADC1/ADC2 conversion
The ADC can be served by DMA, thus allows the automatic transfer of ADC converted values to a destination
location without any software action.
In addition, an analog watchdog feature can accurately monitor the converted voltage of one, some, or all
selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
In order to synchronize A/D conversion, the ADCs can be triggered by timers.
3.28 Digital temperature sensor (DTS)

The DTS is a high-precision low-power junction temperature sensor, based on a configurable controller plus one
or multiple embedded temperature sensors. The sensor can operate in two distinct modes to provide temperature
readings:
• first mode used to a provide calibrated accurate temperature

• second mode that does not require any calibration
Main features:
• Two programmable (rise or fall) hardware alarms incorporating hysteresis
• Status registers recording the minimum and maximum data values received
• A power-up timer with IRQ to support manual operation
• A calibration sequence requiring no knowledge of die temperature.
3.29 VBAT operation

The VSW domain supplies the RTC, the TAMP, the LSI, the LSE, the IWDG5, the backup registers, the LPSRAM1,
the retention RAM, and the backup SRAM.
In order to optimize the battery duration, this power domain is supplied by VDD when available, or by the voltage
applied on VBAT pin (when VDD supply is not present). VBAT power is switched when the PDR detects that VDD
has dropped below the PDR level.
The voltage on VBAT pin can be provided by an external battery, by a supercapacitor, or directly by VDD. In the
later case, VBAT mode is not functional.
VBAT operation is activated when VDD is not present.
Note: None of these events (external interrupts, watchdog reset, TAMP event, or RTC alarm/events) can directly
restore the VDD supply, and force the device out of the VBAT operation. Nevertheless, watchdog reset (taken as
a tamper event), TAMP events, and RTC alarm/events can be used to generate a signal to an external circuitry
(typically a PMIC) that can restore the VDD supply.
3.30 Voltage reference buffer (VREFBUF)

STM32MP25xC/F devices embed a voltage reference buffer which can be used as voltage reference for ADC,
and as voltage reference for external components through VREF+ pin.
An external voltage reference must be provided through the VREF+ pin when the internal voltage reference buffer
is off.
3.31 Multifunction digital filter (MDF1)

The MDF is a high-performance module dedicated to the connection of external sigma-delta (Σ∆) modulators.
DS14284 - Rev 2 page 30/234

Functional overview
3.31.1 Features
• 8 serial digital inputs:
– configurable SPI interface to connect various digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
• 2 common clocks input/output for ΣΔ modulator(s)
• Flexible matrix (BSMX) for connection between filters and digital inputs
• 2 inputs for connecting internal ADCs
• 8 flexible digital filter paths, including
– A Configurable CIC filter:
◦ Can be split into 2 CIC filters: high resolution filter, and out-off limit detector
◦ Can be configured in Sinc4 filter
◦ Can be configured in Sinc5 filter
◦ Adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high pass filter to cancel the DC offset
– An offset error cancellation
– Gain control
– Saturation blocks
– An out-off limit detector
• Short-circuit detector,
• Clock absence detector
• 16 or 24-bit signed output data resolution,
• Continuous or single conversion,
• Possibility to delay independently each bitstream
• Various trigger possibilities
• Break generation on out-of limit or short-circuit detector events
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services
Targeted applications:
• Audio: speech capture
• Motor control
• Metering
3.32 Audio digital filter (ADF1)

The audio digital filter (ADF) is a high-performance module dedicated to the connection of external ΣΔ
modulators.
3.32.1 Features
• 1 serial digital input:
– configurable SPI interface to connect various digital sensors
– configurable Manchester coded interface support
– compatible with PDM interface to support digital microphones
• 2 common clocks input/output for ΣΔ modulators
DS14284 - Rev 2 page 31/234

Functional overview
• 1 flexible digital filter paths, including:

– A MCIC filter configurable in Sinc4 or Sinc5 filter with an adjustable decimation ratio
– A reshape filter to improve the out-off band rejection and in-band ripple
– A high pass filter to cancel the DC offset
– Gain control
– Saturation blocks
• Clock absence detector
• Sound activity detector
• 4-bit signed output data resolution
• Continuous or single conversion
• Possibility to delay the selected bitstream
• One trigger input
• Autonomous functionality in Stop modes
• DMA can be used to read the conversion data
• Interrupts services
Targeted applications:
• Audio: speech capture
• Metering
3.33 Digital camera interface (DCMI)

The devices embed a camera interface that can connect with camera modules and CMOS sensors through an 8-
to 14-bit parallel interface, to receive video data. The camera interface can support a resolution of 1 Mpixels
@15 fps.
• Programmable polarity for the input pixel clock and synchronization signals
• Parallel data communication can be 8-, 10-, 12-, or 14-bit
• 8-bit progressive video monochrome or RawBayer format, YCbCr 4:2:2 progressive video, RGB 565
progressive video or compressed data (like JPEG)
• Continuous mode or snapshot (a single frame) mode
• Capability to automatically crop the image
3.34 Parallel synchronous slave interface (PSSI)

The PSSI and the DCMI use the same circuitry.These two peripherals cannot be used at the same time: when
using the PSSI, DCMI registers cannot be accessed, and vice-versa.
The PSSI and the DCMI share also the same alternate functions and interrupt vector.
The PSSI is a generic synchronous 8/16-bit parallel data input/output slave interface. It enables the transmitter to
send a data valid signal that indicates when the data is valid, and the receiver to output a flow control signal that
indicates when it is ready to sample the data.
Main features:
• Slave mode operation
• 8-bit or 16-bit parallel data input or output
• 8-word (32-byte) FIFO
• Data enable (PSSI_DE) alternate function input, and Ready (PSSI_RDY) alternate function output
3.35 Digital camera interface with pixel processing (DCMIPP)

• Parallel input interface:
– Up to 16 bits @120 MHz, up to 2 Mpixels sensors @30 fps
– Pixel format: RGB565, 888, YUV422, RawBayer/Mono 8/10/12/14
DS14284 - Rev 2 page 32/234

Functional overview
• When connected to CSI-2 input interface:

– Up to 200 Mpixel/s, up to 5 Mpix sensors @30 fps, supports MIPI CSI-2 v1.3
– Pixel format: all MIPI CSI-2 v1.3: RGB565, 888, YUV422, RawBayer
– Features: interleaved packets, 4 virtual channels
• Flow selection and frame control
• Byte-to-pixel conversion
• Statistic removal
• Bad pixel removal (automatic detection and correction of bad pixels from sensor array)
• Decimation of one pixel every 1/2/4/8
• Integrated image processing used to connect low-cost camera module without any embedded ISP
– Color conversion to adapt to the sensor and tune the Illumination
– Contrast enhancement
– RawBayer to RGB conversion (demosaicing)
– Exposure control
– Statistics extraction
• Decimation on pipe 0 (pipe dump)
• Multiple pipelines for parallel applications:
– Pipe0 (for data dump), for a direct dump without processing

– Pipe1 (for main use), with downsize, color conversion, YUV-planar
– Pipe2 (for ancillary use), with downsize, color conversion, YUV-planar
• Downsize
– Box-filtering, with any decimal ratio, up to 8x8, on pipe1 and pipe2
• Gamma conversion
• RGB to YUV color conversion
• Output pixel format:
– Pipe0: any data as is, Y/Rb: 8/10/12/14 statistics, bitstreams
– Pipe2: RGB888, RGB565, YUV422-1, Y8, ARGB and RGBA (co-planar only)
– Pipe1: Pipe2 formats + YUV422-2, YUV420-2, YUV420-3 (multi-planar possible)
• AXI master
3.36 Camera serial interface (CSI)

The CSI provides an interface between the system and the PHY, allowing communication with a CSI-2 compliant
camera.
• Compliant with MIPI Alliance standard v1.3
• Up to two data lanes, up to 2.5 Gbit/s per lane in high-speed (HS) mode and 10 Mbit/s in low-power (LP)
mode
• Data transmission in HS and LP modes
• Escape mode (ESC), and ultra-low-power state mode (ULPS)
• CSI-2 virtual channel and data type filtering supporting interleaved data
– Up to 4 virtual channels
– Support data formats specified into the MIPI Alliance standard for CSI-2 v1.3 (18 data formats, plus
the user defined onces, up to 7 independent data types)
• Internal connection with the DCMIPP
3.37 LCD-TFT display controller (LTDC)

The LTDC handles display composition and rotation, with the following main features:
• 3 display layers with dedicated FIFO
• Input pixel flexible format, including YUV420 full-planar
• Secure layer: protected access to buffer and configuration registers
• Output rotation: 90 and 270 degrees
DS14284 - Rev 2 page 33/234

Functional overview
• Horizontal and vertical mirror

• Color lookup-table, color keying, gamma, and dithering on output
LTDC parallel interface:

• Provides a 24-bit parallel digital RGB, and delivers all signals to interface directly to a broad range of LCD
and TFT panels.
• Up to 150 Mpixel/s, which correspond up to FHD (1920 × 1080) @60 fps resolution with HDMI blankings
• Output pixel formats: RGB888, RGB666, RGB565, YUV422-16 bits
LTDC DSI interface:

• The LTDC provide pixels to the display serial interface (DSI).
LTDC LVDS interface:

• The LTDC provide pixels to the LVDS display interface (LVDS).
3.38 Display serial interface (DSI)

Note: Features may be limited or absent in some devices or packages (see Section 2: Description for details).
The DSI is part of a group of communication protocols defined by the MIPI Alliance. The MIPI DSI host controller
is a digital core that implements all protocol functions defined in the MIPI DSI specification.
It provides an interface between the system and the MIPI D-PHY that allows the communication with a DSI-
compliant display.
• Compliant with MIPI Alliance standards
• Interface with MIPI D-PHY
• Supports all commands defined in the MIPI Alliance specification for DCS
• Bidirectional communication and escape mode support through data lane 0
• Supports non-continuous clock in D-PHY clock lane for additional power saving
• Supports ultra-low-power mode with PLL disabled
• ECC and checksum capabilities
• Support for end of transmission packet (EoTp)
• Fault recovery schemes
• Configurable selection of system interfaces:
– AMBA APB for control and optional support for generic and DCS commands
– Video mode interface through LTDC
– Adapted command mode interface through LTDC
– Independently programmable virtual channel ID in video mode, adapted command mode and APB
slave
• Video mode interfaces features:
– LTDC interface color coding mappings into 16, 18 and 24-bit interface
– Programmable polarity of all LTDC interface signals
• Adapted interface features:
– Support for sending large amounts of data through the memory_write_start (WMS) and
memory_write_continue (WMC) DCS commands
– LTDC interface color coding mappings into 16, 18 and 24-bit interface
• Video mode pattern generator
• Up to 4 × data lanes, up to 2.5 Gbps each
• Up to QXGA (2048 × 1536) @60 fps
3.39 LVDS display interface (LVDS)

The LVDS supports the following high-level features:
DS14284 - Rev 2 page 34/234

Functional overview
• FPD-Link-I and OpenLDI (v0.95) protocols

• Single-link or dual-link operation
• Single-display or double-display (with the same content duplicated on both)
• Flexible bit-mapping, including JEIDA and VESA
• RGB888 or RGB666 output
• Up to 2 links of 4 data lanes, up to 1.1 Gbit/s per lane
– FPD bitrate: 784 Mbit/s per lane (112 Mpixel/s per link, 224 Mpixel/s if dual Link)
– OpenLDI bitrate: 1100 Mbit/s per lane (157 Mpixel/s per link, 314 Mpixel/s if dual link)
• Up to QXGA (2048 × 1536) @60 fps with dual link
• Up to WSXGA+ (1680 × 1050) @60 fps with single FPD link (1080p60 supported with OpenLDI)
3.40 Video encoder (VENC)

• Video encode
– H264 (MPEG4_Part10/AVC, baseline/main/high up to 5.2), VP8
– Up to 1080p60 for H264/VP8 (performance shared with the VDEC)
• Still-image encode
– JPEG (baseline interleaved)

– Up to 500 Mpixel/s for JPEG (performance shared with the VDEC)
• VDERAM
– 128 Kbytes
– Hardware handshake between VENC and VDEC
– Can be statically assigned to CPU as additional system RAM by SYSCFG setting
3.41 Video decoder (VDEC)

• Video decode
– H264 (MPEG4_Part10/AVC, baseline/main/high up to 5.2), VP8
– Up to 1080p60 for H264/VP8 (performance shared with the VENC)
• Still-image decode
– JPEG (baseline interleaved).
– Up to 500 Mpixel/s for JPEG (performance shared with the VENC)
• VDERAM
– 128 Kbytes
– Hardware handshake between VENC and VDEC
– Can be statically assigned to CPU as additional system RAM by SYSCFG setting
3.42 True random number generator (RNG )

All devices embed an RNG that deliver s 32-bit random numbers generated by an integrated analog circuit.
3.43 Hash processor (HASH)

The HASH is a fully compliant implementation of the secure hash algorithm (SHA-1, SHA-2 family, SHA-3 family),
and the HMAC (keyed-hash message authentication code) algorithm. The HMAC is suitable for applications that
require a message authentication.
The HASH computes FIPS (federal information processing Standards) approved digests of 160-, 224-, 256-, 384-,
and 512-bit length, for messages of any length:
• less than 264 bits (for SHA-1, SHA-224, and SHA-256)
• less than 2128 bits (for SHA-384, SHA-512)
DS14284 - Rev 2 page 35/234

Functional overview
3.44 Cryptographic processor (CRYP1/2)

The devices embed two cryptographic processor that can be used both to encrypt and decrypt data using the
DES, triple-DES, or AES algorithms. The implementation if fully compliant with the following standards:
• DES and TDES are defined by FIPS (PUB 46-3, Oct 1999), and by the American National Standards
Institute (ANSI X9.52)
• AES is defined by FIPS (FIPS PUB 197, Nov 2001)
Multiple key sizes and chaining modes are supported:
• DES/TDES chaining modes ECB and CBC, supporting standard 56-bit keys with 8-bit parity per key
• AES chaining modes ECB, CBC, CTR, GCM, GMAC, CCM for key sizes of 128, 192, or 256 bits
The CRYP in AES mode supports key sharing from SAES co-processor. It is a 32-bit AHB peripheral with DMA
support for incoming and outgoing data.
The CRYP also includes input and output FIFOs (each 8 words deep) for better performance.
3.45 Secure AES (SAES)

The SAES encrypts or decrypts data, using an algorithm and implementation fully compliant with the AES
standard. It implements embedded protection against differential power analysis (DPA) and related side-channel
attacks.
The SAES supports CTR, GCM, GMAC, CCM, ECB, and CBC chaining modes for key sizes of 128 or 256 bits, as
well as special modes such as hardware secret key encryption/decryption (wrapped-key mode) and key sharing
with faster CRYP peripheral (shared-key mode).
The SAES can load directly two hardware master keys that are not directly accessible by any software. These
keys can be used to encrypt random keys that are usable only on this device, and are not directly accessible by
software.
The SAES supports DMA single transfers for incoming and outgoing data (two DMA channels required). It is
connected by hardware to the RNG and to the CRYP1/2.
The SAES is an AMBA AHB slave peripheral.
3.46 Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically those related to RSA,
Diffie-Hellmann, or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a
reasonable cost, these operations are executed in the Montgomery domain.
For a given operation, all needed computations are performed within the accelerator: no further hardware/
software elaboration is needed to process inputs or outputs.
3.47 Boot and security and OTP control (BSEC)

The BSEC is used to control an OTP (one-time programmable) fuse box, used for embedded non-volatile storage
for device configuration and security parameters.
Embedded non-volatile secrets are stored in the BSEC upper area that is only accessible while BSEC is operating
in a closed state. In open state those non-volatile secrets are permanently hidden.
The BSEC use is reserved to trusted domain CPU, and boot CPU following a BSEC reset (cold/warm or hot).
3.48 Timers and watchdogs

The devices include three advanced-control timers, twelve general-purpose timers, two basic timers, five low-
power timers, seven watchdogs, two SysTick timers in Cortex-M33 , one SysTick timer in Cortex-M0+, and four
system timers in each Cortex-A35.
All timer counters can be frozen in debug mode.
The table below compares features of the different timers.
DS14284 - Rev 2 page 36/234

Functional overview
Table 7. Timer feature comparison
Max Max(1)
DMA Capture/ Comple-
Timer Counter Counter Prescaler interface timer
Timer request compare mentary
type resolution type factor clock clock
generation channels output
(MHz) (MHz)
Up, Any integer

Advanced TIM1,
16-bit down, between 1 Yes 6 4 200 200
-control TIM8 , TIM20
up/down and 65536
TIM2,
Up,
TIM3,
32-bit down, Any integer between 1 and 65536 Yes 4 No 200 200
TIM4,
up/down
TIM5
TIM10,
General TIM11,
16-bit Up Any integer between 1 and 65536 No 1 No 200 200
purpose TIM13,
TIM14
TIM12 16-bit Up Any integer between 1 and 65536 No 2 No 200 200
TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 200 200
TIM16,
16-bit Up Any integer between 1 and 65536 Yes 1 1 200 200
TIM17
TIM6,
Basic 16-bit Up Any integer between 1 and 65536 Yes 0 No 200 200
TIM7
LPTIM1, Up,
16-bit 1, 2, 4, 8, 16, 32, 64, 128 Yes 2(2) No 200 100
LPTIM2 Up/down
Low-power LPTIM3,
16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 Yes 2(2) No 200(3) 100(4)
LPTIM4
LPTIM5 16-bit Up 1, 2, 4, 8, 16, 32, 64, 128 No 0 No 200(3) 100
1. The maximum timer clock depends on RCC settings.

2. only compare channel.
3. 16 MHz bus clock when supplied by the backup regulator (LP-Stop1/2, LPLV-Stop1/2 or Standby1).
4. 32 kHz timer clock in autonomous mode (Stop1/2, LP-Stop1/2, LPLV-Stop1/2 or Standby1).
3.48.1 Advanced-control timers (TIM1/8/20)

The advanced-control timers can be seen as three-phase PWM generators multiplexed on six channels. They
have complementary PWM outputs with programmable inserted dead times. They can also be considered as
complete general-purpose timers. Their four independent channels can be used for:
• input capture
• output compare
• PWM generation (edge- or center-aligned modes)
• one-pulse mode output
If configured as standard 16-bit timers, the advanced-control timers have the same features as the general-
purpose timers. If configured as 16-bit PWM generators, they have full modulation capability (0 to 100%).
The advanced-control timers can work together with general-purpose timers via the timer link feature for
synchronization or event chaining.
TIM1, TIM8 and TIM20 support independent DMA request generation.
DS14284 - Rev 2 page 37/234

Functional overview
3.48.2 General-purpose timers (TIM2/3/4/5/10/11/12/13/14/15/16/17)

There are twelve synchronizable general-purpose timers embedded in STM32MP25xC/F devices (see Table 7 for
differences).
• TIM2, TIM3, TIM4, TIM5
These timers are based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. They feature four
independent channels for input capture/output compare, PWM, or one-pulse mode output. This gives up to 16
input capture/output compare/PWMs on the largest packages.
These timers can work together, or with the other general-purpose timers and the advanced-control timers TIM1,
TIM8 and TIM20, via the timer link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 have independent DMA request generation. They can handle quadrature (incremental)
encoder signals, and the digital outputs from one to four halleffect sensors.
• TIM10, TIM11, TIM12, TIM13, TIM14, TIM15, TIM16, TIM17
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM10, TIM11, TIM13, TIM14,
TIM16 and TIM17 feature one independent channel, whereas TIM12 and TIM15 have two independent channels
for input capture/output compare, PWM, or one-pulse mode output. They can be synchronized with the TIM2,
TIM3, TIM4, TIM5 full-featured general-purpose timers or used as simple timebases.
3.48.3 Basic timers (TIM6/TIM7)

These timers are used as a generic 16-bit time base, and support independent DMA request generation.
3.48.4 Low-power timer (LPTIM1/2/3/4/5)

These low-power timers have an independent clock and run in Stop mode if they are clocked by LSE, LSI, or an
external clock. They can wake up the device from Stop mode.
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/one-shot mode
• Selectable software/hardware input trigger
• Selectable clock source:
– Internal clock source: LSE, LSI, HSI (RCC flexgen output)
– External clock source over LPTIM input (working even with no internal clock source running, used by
the pulse counter application)
• Programmable digital glitch filter
• Encoder mode (LPTIM1/2)
3.48.5 Independent watchdog (IWDG1/2/3/4/5)

The IWDG is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 32 kHz
internal RC (LSI). As it operates independently from the main clock, the IWDG can operate in Stop and Standby
modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the option bytes.
3.48.6 System window watchdog (WWDG1/2)

The WWDG is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to
reset the device when a problem occurs. It is clocked from the APB clock. It has an early warning interrupt
capability and the counter can be frozen in debug mode.
3.48.7 SysTick timer

This timer is embedded in the Cortex-M33 (two instances, secure and non-Secure) , and in the Cortex-M0+ core.
It is dedicated to real-time operating systems, but can also be used as standard downcounter.
• 24-bit downcounter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
DS14284 - Rev 2 page 38/234

Functional overview
• Programmable clock source
3.48.8 Cortex-A35 generic timers (CNT)

The Cortex-A35 generic timers are fed by value from system timing generation (STGEN). The Cortex-A35
processor provides a set of four timers for each processor:
• Physical timer for use in secure and non-secure modes. The registers for the physical timer are banked to
provide secure and non-secure copies.
• Virtual timer for use in non-secure mode
• Physical timer for use in hypervisor mode
These generic timers are not memory-mapped peripherals: they are accessible only by specific Cortex-A35
coprocessor instructions (cp15).
3.49 System timer generation (STGEN)

The STGEN generates a time-count value that provides a consistent view of time for all Cortex-A35 generic
timers.
• 64-bit wide to avoid roll-over issues
• Starts from zero or a programmable value
• control APB interface (STGENC) that enables the timer to be saved and restored across powerdown
events
• Read-only APB interface (STGENR) that enables the timer value to be read by nonsecure software and
debug tools
• timer value incrementing that can be stopped during system debug
3.50 Real-time clock (RTC)

The RTC provides an automatic wake-up to manage all low-power modes. It is an independent BCD timer/counter
that provides a time-of-day clock/calendar with programmable alarm interrupts.
The RTC includes also a periodic programmable wake-up flag with interrupt capability.
After backup domain reset, all RTC registers are protected against possible parasitic write accesses.
As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device
status (Run mode, low-power mode, or under reset).
• Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of
month), month, and year
• Daylight saving compensation programmable by software
• Programmable alarm with interrupt function. The alarm can be triggered by any combination of the
calendar fields.
• Automatic wake-up unit that generates a periodic flag that triggers an automatic wakeup interrupt
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the
calendar precision.
• Accurate synchronization with an external clock using the subsecond shift feature
• Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window
of several seconds
• Timestamp function for event saving
• Maskable interrupts/events:
– Alarm A
– Alarm B
– Wake-up interrupt
– Timestamp
• TrustZone support:
– RTC fully securable
– Alarm A, alarm B, wake-up timer and timestamp individual secure or non-secure configuration
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Functional overview
3.51 Tamper and backup registers (TAMP)

The 128 x 32-bit backup registers are retained in all low-power modes, and in VBAT mode. They can be used to
store sensitive data as their content is protected by a tamper detection circuit. 16 tamper pins (eight input and
eight outputs), and 14 internal tampers are available for anti-tamper detection.
The eight external tamper pins can be configured for edge detection, edge and level, level detection with filtering,
or up to eight active tamper which increases the security level by auto-checking that tamper pins are not
externally opened or shorted.
• 128 backup registers (TAMP_BKPxR) implemented in the RTC domain that remains powered-on by VBAT
when the VDD power is switched off
• 8 external tamper detection events:
– Each external event can be configured to be active or passive.
– External passive tampers with configurable filter and internal pull-up
• 14 internal tamper events
• Any tamper detection can generate an RTC timestamp event.
• Any tamper detection erases backup registers.
• TrustZone support:
– Tamper secure or non-secure configuration
– Backup registers configuration in three configurable-size areas:

◦ 1 read/write secure area
◦ 1 write secure/read non-secure area
◦ 1 read/write non-secure area
• Monotonic counter
3.52 Inter-integrated circuit interface (I2C1/2/3/4/5/6/7/8)

STM32MP25xC/F devices embed eight I2C interfaces, that handle communications between the device and the
serial I2C bus. Each I2C interface controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 Kbit/s
– Fast-mode (Fm), with a bitrate up to 400 Kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System management bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK control
– Address resolution protocol (ARP) support
– SMBus alert
• Power system management protocol (PMBus) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources that allows the I2C communication speed to be
independent from the PCLK reprogramming
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
3.53 Improved inter-integrated circuit (I3C1/2/3/4)

STM32MP25xC/F devices embed four I3C interfaces, that handle communication between the device and others
that are all connected on an I3C bus, like sensors and host processors.
DS14284 - Rev 2 page 40/234

Functional overview
The I3C peripheral implements all required features of the MIPI I3C specification v1.1. It can control all I3C
bus‑specific sequencing, protocol, arbitration and timing, and can be acting as controller (formerly known as
master), or as target (formerly known as slave).
The I3C peripheral, acting as controller, improves the I2C interface features still preserving some backward
compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast‑mode (Fm) or legacy I2C
fast‑mode plus (Fm+), provided that this latter does not perform clock stretching.
The I3C peripheral can be used with DMA in order to off‑load the CPU.
• MIPI I3C specification v1.1 (see I3C section in the reference manual), as:
– I3C primary controller
– I3C secondary controller
– I3C target
• Registers configuration from the host application via the APB slave port
• Queued transfers:
– Transmit FIFO (TX‑FIFO) for data bytes/words to be transmitted on I3C bus
– Receive FIFO (RX‑FIFO) for received data bytes/words on I3C bus
– Control FIFO (C‑FIFO) for control words to be sent on I3C bus, when controller
– Status FIFO (S‑FIFO) for status words as received on I3C bus, when controller
– For each FIFO, optional DMA mode with a dedicated DMA channel
• Messages:
– Legacy I2C read/write messages to legacy I2C targets in Fm/Fm+
– I3C SDR read/write private messages
– I3C SDR (write) broadcast CCC messages
– I3C SDR read/write direct CCC messages
• Frame‑level management, when controller:
– Software‑triggered or hardware‑triggered transfer
– Optional C‑FIFO and TX‑FIFO preload
– Multiple messages encapsulation
– Optional arbitrable header
• Programmable bus timing, when controller
– SCL high and low period
– SDA hold time
– Bus free (minimum) time (between a stop and a start)
– Bus available/idle condition time, maximum clock stall time
– Minimum clock stall time during 9th bit
• Target‑initiated requests management:
– In‑band interrupts, with programmable IBI payload (up to 4 bytes)
– Bus control request, with recovery flow support and hand‑off delay
– Hot‑join mechanism
– Pending read notification
• Bus error management
– M0, M1, M2, and M3, when controller
– S0, S1, S2, S3, S4, S5, and S6 when target
– bus control switch error and recovery
– target reset
• Separately programmed event/flag generation and management
– Separated identification and clear control
– Host application notification via event/flag polling, and/or via interrupt with a perevent programmable
enable
– Error type identification
• Autonomous mode and transfers during Sleep and Stop modes via DMA
DS14284 - Rev 2 page 41/234

Functional overview
• Autonomous wake‑up on
– Slave request acknowledge, when controller
– Missed start detection, when target
– Reset pattern detection, when target
3.54 Universal synchronous asynchronous receiver transmitter (USART1/2/3/6,

UART4/5/7/8/9)
STM32MP25xC/F devices embed four USART and five UART (see Table 8. USART/UART features for feature
summary).
These interfaces provide asynchronous communication, IrDA SIR ENDEC support, multiprocessor
communication mode, single-wire half-duplex communication mode, and have LIN master/slave capability. They
provide hardware management of CTS and RTS signals, and RS485 Driver Enable. They can communicate at
speeds of up to 10 Mbit/s.
The USARTs embed a 64-bytes transmit FIFO (TXFIFO) and a 64-bytes receive FIFO (RXFIFO). The FIFO mode
is enabled by software, and is disabled by default.
All USARTs provide Smartcard mode (ISO 7816 compliant) and SPI-like communication capability. They have a
clock domain independent from the CPU clock: this allows the USARTx to wake up the device from Stop mode
using baudrates up to 200 Kbaud. Wake-up events from Stop mode are programmable and can be one of the
following:
• start bit detection
• any received data frame
• a specific programmed data frame
All USARTs can be served by the DMA controller.
Table 8. USART/UART features
Modes/features(1) USART1/2/3/6 UART4/5/7/8/9
Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
Synchronous SPI mode (master/slave) X -
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X X
LIN mode X X
Dual clock domain and wakeup from low power mode X X
Receiver timeout interrupt X X
Modbus communication X X
Auto-baudrate detection X X
Driver enable X X
Data length 7, 8, and 9 bits
1. X = supported.
3.55 Low-power universal asynchronous receiver transmitter (LPUART1)

The devices embed one LPUART that supports asynchronous serial communication with minimum power
consumption. The LPUART supports half-duplex single-wire communication and modem operations (CTS/RTS). It
allows multiprocessor communication.
The LPUART embeds a transmit FIFO (TXFIFO) and a receive FIFO (RXFIFO). The FIFO mode is enabled by
software, and is disabled by default.
DS14284 - Rev 2 page 42/234

Functional overview
The LPUART has a clock domain independent from the CPU clock, and can wake up the system from Stop mode.
The wake-up from Stop mode is programmable, and can be done on one of the following:
• a start bit detection
• any received data frame
• a specific programmed data frame
• specific TXFIFO/RXFIFO status when FIFO mode is enabled
Even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low-energy
consumption.
The LPUART interface can be served by the LPDMA controller.
3.56 Serial peripheral interface (SPI1/2/3/4/5/6/7/8) inter-integrated sound interfaces

(I2S1/2/3)
The devices feature up to eight SPIs that allow communication at up to 50 Mbit/s in master and slave modes, in
half-duplex, full-duplex, and simplex modes. The 3-bit prescaler gives eight master mode frequencies, and the
frame is configurable from 4 to 16 bits.
All SPI interfaces support NSS pulse mode, TI mode, hardware CRC calculation, and eight 8-bit embedded Rx
and Tx FIFOs with DMA capability.
The standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) can be operated in master or slave mode, in
full-duplex and half-duplex communication modes. They can be configured to operate with a 16-/32-bit resolution
as an input or output channel.
Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both I2S interfaces is/are
configured in master mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency. All I2S interfaces support 16x 8bit embedded Rx and Tx FIFOs with DMA capability.
3.57 Serial audio interfaces (SAI1/2/3/4)

The devices embed four SAIs that are used to design many stereo or mono audio protocols such as I2S, LSB or
MSB-justified, PCM/DSP, TDM, or AC’97. An SPDIF output is available when the audio block is configured as a
transmitter. To bring this level of flexibility and reconfigurability, the SAI contains two independent audio
subblocks. Each block has it own clock generator and I/O line controller.
Audio sampling frequencies up to 192 kHz are supported.
Up to eight microphones can be supported thanks to an embedded PDM interface.
The SAI can work in master or slave configuration. The audio subblocks can be either receiver or transmitter, and
can work synchronously or asynchronously (with respect to the other one). The SAI can be connected with other
SAIs to work synchronously.
3.58 SPDIF receiver interface (SPDIFRX)

The SPDIFRX is designed to receive an S/PDIF flow compliant with IEC-60958 and IEC61937. These standards
support simple stereo streams up to high sample rate, and compressed multi-channel surround sound, such as
those defined by Dolby® or DTS® (up to 5.1).
• Up to 4 inputs available
• Automatic symbol rate detection
• Maximum symbol rate: 12.288 MHz
• Stereo stream from 32 to 192 kHz supported
• Supports audio IEC-60958 and IEC-61937, consumer applications
• Parity bit management
• Communication using DMA for audio samples
• Communication using DMA for control and user channel information
• Interrupt capabilities
The SPDIFRX receiver provides all necessary features to detect the symbol rate, and to decode the incoming
data stream. The user can select the wanted SPDIF input, and when a valid signal is available, the SPDIFRX
re‑samples the incoming signal, decodes the Manchester stream, and recognizes frames, sub-frames, and blocks
elements. It delivers to the CPU decoded data, and associated status flags.
DS14284 - Rev 2 page 43/234

Functional overview
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF sub-frame rate: this
signal is used to compute the exact sample rate for clock drift algorithms.
3.59 Secure digital input/output MultiMediaCard interface (SDMMC1/2/3)

Three SDMMCs provide an interface between the AHB bus and SD memory cards, SDIO and e.MMC devices.
SDMMC features include the following:
• Full compliance with MultiMediaCard System Specification Version 5.1
Card support for three different databus modes: 1-bit (default), 4-bit and 8-bit (HS200 speed limited by maximum
allowed I/O speed, HS400 is not supported).
• Full compatibility with previous versions of MultiMediaCards (backward compatibility)
• Full compliance with SD memory card specifications version 6.0 (SDR104 SDMMC_CK speed limited to
maximum allowed I/O speed, SPI and UHS-II modes not supported)
• Full compliance with SDIO card specification version 4.0
Card support for two different databus modes: 1-bit (default) and 4-bit (SDR104 SDMMC_CK speed limited to
maximum allowed I/O speed, SPI and UHS-II modes not supported)
• Data transfer up to 208 Mbyte/s for the 8-bit mode (depending on the maximum allowed I/O speed)
• Data and command output enable signals to control external bidirectional drivers
• The SDMMC host interface embeds a dedicated DMA controller that allows high-speed transfers between
the interface and the SRAM.
• IDMA linked list support
Each SDMMC is coupled with a delay block (DLYBSD) that supports an external data frequency above 100 MHz.
3.60 Controller area network (FDCAN1/2/3)

The CAN subsystem consists of three FDCANs, a shared message RAM, and a clock calibration unit.
All FDCANs are compliant with ISO 11898-1 (CAN protocol specification version 2.0 part A, B), and CAN FD
protocol specification version 1.0.
FDCAN1 supports time triggered CAN (TTCAN) specified in ISO 11898-4, including event synchronized time-
triggered communication, global system time, and clock drift compensation. The FDCAN1 contains additional
registers, specific to the time triggered feature. The CAN FD option can be used together with event-triggered and
time-triggered CAN communication.
A 10 Kbyte message RAM implements filters, receives FIFOs, receives buffers, transmits event FIFOs, transmits
buffers (and triggers for TTCAN). This message RAM is shared between all FDCANs.
The common clock calibration unit is optional. It can be used to generate a calibrated clock for FDCANs from the
HSI internal RC oscillator and the PLL, by evaluating CAN messages received by the FDCAN1.
3.61 Universal serial bus Hi-Speed host (USBH)

The devices embed one USB Hi-Speed host (up to 480 Mbit/s) with one physical port. USBH supports both low,
full-speed (OHCI) as well as Hi-Speed (EHCI) operations. It integrates a physical interface (PHY) which can be
used for either low-speed (1.2 Mbit/s), full-speed (12 Mbit/s) ,or Hi-Speed operation (480 Mbit/s).
The USBH is compliant with the USB 2.0 specification.
3.62 USB Type-C Power Delivery controller (UCPD1)

The devices embed one controller compliant with USB Type-C Rev.1.2 and USB Power Delivery Rev. 3.1
specifications.
The UCPD use specific I/Os supporting the USB Type-C and USB Power Delivery requirements, featuring:
• USB Type-C pull-up (Rp, all values) and pull-down (Rd) resistors
• USB Power Delivery message transmission and reception
The digital controller handles notably:
• USB Type-C level detection with de-bounce, generating interrupts
• byte-level interface for USB Power Delivery payload, generating interrupts (DMA compatible)
• USB Power Delivery timing dividers (including a clock pre-scaler)
DS14284 - Rev 2 page 44/234

Functional overview
• CRC generation/checking
• 4b5b encode/decode
• ordered sets (with a programmable ordered set mask at receive)
• frequency recovery in receiver during preamble
The interface offers low-power operation compatible with Stop mode, maintaining the capacity to detect incoming
USB Power Delivery messages.
3.63 Universal serial bus 3.0 dual role data (USB3DR)

• 5 Gbit/s PHY (COMBOPHY)
• xHCI model.
• Dual Role Data. The USB3DR can be configured statically as a Host or Device port.
• OTG is not supported:
– Dynamic switch from Host (resp. Device) to Device (resp. Host) role is not supported.
– Host Negotiation Protocol (HNP), Role Swap Protocol (RSP), Session Request Protocol (SRP),
Attach Detection Protocol (ADP) are not supported.
• USB3 SuperSpeed mode (5 Gbit/s), as well as USB2 Low-Speed/Full-Speed/Hi-Speed modes (when Host)
or USB2 Full-Speed/Hi-Speed modes (when Device).
• Descriptor caching and data pre-fetching to meet system performance.

• Variable FIFO buffer allocation for each endpoint.
• Simultaneously 4 Gbps IN and 4 Gbps OUT bandwidth
• DMA engine
• Supports Battery Charging v1.2, with the exception of the Accessory Charger Adapter mode
The standards supported are:
• Universal Serial Bus 3.0 Specification, Revision 1.0, November 12, 2008
• Universal Serial Bus Specification, Revision 2.0, USB Implementers Forum, Inc., April 27, 2000
• Errata for “USB Revision 2.0 April 27 2000” as of May 28, 2002, USB-IF
• eXtensible Host Controller Interface for Universal Serial Bus (xHCI), Revision 1.1, Intel Corp., December
20, 2013
• UTMI+ Specification, Revision 1.0, ULPI Working Group, February 25, 2004
• Battery Charging Specification, Revision 1.2, December 7, 2010
3.64 PCI Express interface (PCIE)

The PCIE controller has the following features:
• one lane Generation2 PCIe
• dual-mode (RC or EP)
• PTM
• 256 byte maximum payload size
• Remote device maximum read request size 1K Byte
• Single Virtual Channel
• Single Function
• Legacy INTx support, MSI and GICv2m host support
• ASPM L0s and L1, and L1.1 substate
• AER
• internal ATU
• 5 Gbit/s PHY (COMBOPHY)
An included PCIe reference clock generator (REFGEN) provides a 100 MHz differential clock to a PCIe link
partner. This can be used to eliminate the external 100 MHz clock source that is typically found in PCIe common-
clock implementations.
The PCIE internal reference clock is 25 MHz (without SSC). There is also the option of an external PCIE
differential reference clock 100 MHz (with SSC).
DS14284 - Rev 2 page 45/234

Functional overview
3.65 5-Gbit/s PHY controller (COMBOPHY)

The COMBOPHY control a 5-Gbit/s multi-protocol PHY, that is used by the USB3DR or the PCIE (mutually
exclusive). It supports data rates up to 5 Gbit/s for USB3.0, 5 Gbit/s for PCIe gen2, and 2.5 Gbit/s for PCIe gen1.
The COMBOPHY includes the physical coding sublayer (PCS) blocks that perform 8-/10bit encoding/decoding,
and resynchronizing RX data to the local clock domain.
The COMBOPHY is single lane. The SuperSpeed lane multiplexing for USB Type-C must be managed by a
switch outside the device.
3.66 Gigabit Ethernet MAC interface (ETH1/2)

The devices embed two fully independent instances of a 10/100/1000 Ethernet MAC controller, that enable
transmission and reception of data over Ethernet, in compliance with IEEE 802.3-2008.
Each Ethernet MAC controller is connected to an external Ethernet PHY via a standard media independent
interface.
Features provided by the Ethernet controller include:
• 10, 100, and 1000 Mbps data transfer rates
• Full-duplex and half-duplex operations
• Standard or Jumbo Ethernet packets

• Two independent Rx queues and two independent Tx queues, with each queue associated to a (subset of)
PCP code(s)
• Configurable media-independent interface to external PHY:
– RGMII
– MII
– RMII
– MDIO master interface for external PHY device configuration
– Internal or external reference clocks
• Low-power support:
– Energy Efficient Ethernet (EEE) compliant with IEEE 802.3az-2010;
– Detection of LAN wake-up frames and “Magic Packet” frames
• Timing and synchronization:
– compliance with IEEE 1588-2008 (PTP) and IEEE 802.1AS-Rev
– hardware “auxiliary timestamp trigger” for accurate sampling of the “PTP system clock”
– Internal or external system time
• Time-sensitive networking:
– “Forwarding and Queuing Enhancements for Time-Sensitive Streams” compliant with IEEE 802.1Qav
– “Enhancements to Scheduled Traffic” compliant with IEEE 802.1Qbv, with a gate control list depth up
to 128
– “Frame Preemption” compliant with IEEE 802.1Qbu and IEEE 802.3br
• Preamble and start-of-frame data insertion (for Tx) and deletion (for Rx)
• Option for automatic CRC generation (for Tx), checking and stripping (for Rx)
• Source address field insertion or replacement in transmitted packets
• Filtering options:
– Perfect match with a given SA/DA (up to 3 MAC addresses are supported)
– 64-bit Hash filter match
– Several multicast/broadcast rules supported
– Based on IEEE 802.1q ‘VLAN tag’ field (perfect match, hash filtering)
– Support for different ‘VLAN tag’ filtering for each Rx queue
– Based on TCP/UDP/IP address (perfect match, inverse filtering)
DS14284 - Rev 2 page 46/234

Functional overview
• TCP/IP offloading:
– Checksum calculation and insertion in the transmit path
– Checksum error detection in the receive path.
– TCP segmentation offload (automatic split of a large TCP packet into smaller Ethernet frames)
3.67 Gigabit Ethernet switch (ETHSW)

A 3-port gigabit Ethernet switch is included. The switch supports TSN and related standards, and also includes a
cut-through accelerator (called ACM) for the two external ports.
Two switch ports are available externally providing RGMII and RMII interfaces. The third port is connected
internally to the ETH1 controller.
The switch can be completely bypassed. In this case, ETH1 is connected directly to a single external port.
3.68 Debug infrastructure

The devices offer a comprehensive set of debug and trace features to support software development and system
integration.
• Breakpoint debugging
• Code execution tracing

• Software instrumentation
• JTAG debug port
• Serial-wire debug port
• Trigger input and output
• Serial-wire trace port
• Trace port
• Arm CoreSight debug and trace components
The debug can be controlled via a JTAG/serial-wire debug access port, using industry standard debugging tools.
A trace port allows data to be captured for logging and analysis.
DS14284 - Rev 2 page 47/234

Pinouts/ballouts, pin description, and alternate functions
4 Pinouts/ballouts, pin description, and alternate functions
4.1 Ballout schematics
Figure 6. STM32MP25xC/F VFBGA361 pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
DDR_ DDR_
A VSS DSI_D3P DSI_D2P DSI_CKN DSI_D0N DSI_D1N PB8 PB9 PB3 PD2 PD15 PD6 PD14 PE2 PE3 PE13
DQ11 DQ9
VSS
DDR_ DDR_ DDR_

B VDDCSI DSI_D3N DSI_D2N DSI_CKP DSI_D0P DSI_D1P PB11 PB0 PB5 PD11 PI10 PD5 PE0 PE4 PE8 PE11
DQ10 DQS1N DQS1P
DSI_ VDDA18 DDR_ DDR_ DDR_

C CSI_CKP CSI_CKN VSS
REXT DSI
VDDDSI VSS PB6 PB4 PD9 PD0 PD4 PE1 PE5 PE7 PE12
DQ8 DQ15 DQM1
VDDA18 VDDA18 DDR_ DDR_ DDR_

D CSI_D1P CSI_D1N
CSI
PI6 PI7 VDDIO4 PB7 PD3 PB1 VDDIO1 PD10 PD7 VSS PE15 PE10
DDR DQ14 DQ13 DQ12
CSI_ VDDA18 DDR_

E CSI_D0N CSI_D0P
REXT
PG15 PG8 VDDIO4 PG7 VSS PB2 VDDIO3 PD8 PB10 VDDCPU PB12
PLL1
VSS
RESETN
DDR_A9 DDR_A20
LVDS1_ LVDS1_ LVDS1_ LVDS1_ VDD

F D0N D0P D1N D1P
PG10 VSS PG11 VDDIO2 PD1 VDDIO3 VSS PI11 VSS PE6 PE9
QDDR
DDR_A0 DDR_A11 DDR_A21
LVDS1_ LVDS1_ VDDA18 VDD

G PI4 PG9
D2N D2P
PF15
PLL2
PF14 VSS PD13
CORE
VSS PH4 VDDCPU PE14 PB13 DDR_ZQ DDR_A1 DDR_A10 DDR_A22
LVDS1_ LVDS1_ VDDA18 VDD

H PI0 PF13
D4N D4P
PG14
PLL3
PG12 VDD PI3 VSS
CORE
PG3 VSS PD12 PB14 VSS DDR_A25 DDR_A8 DDR_A23
VDD LVDS1_ LVDS1_ VDDA18 VDD VDD

J LVDS D3N D3P LVDS
PI2 VSS PG13 VSS PI1
CORE
VSS PA5 VDDCPU VSS PB15
QDDR
VDD DDR_
K PG5 PG6 PZ6 VSS VSS PI9 PI5 VDD PA8 VSS
CORE
PA9 VSS PH3 PA7 VSS
VREF
DDR_A14 DDR_A26
VDD VDD
L PZ7 PZ9 PZ8 PZ4 PZ0 VDD PF12 VSS PF10
CORE
VSS PH7 VDDCPU PH2 PH6
QDDR
OSC32_ OSC32_ VDD

M OUT IN
PZ2 PZ1 PZ3 VSSAON PG2 V08CAP PH5 VSS VDDGPU PH8 VDDCPU PA6 PA10
QDDR
VDDA18 VDDA18 VDD VDD

N PDR_ON NRST PZ5 PI8
AON ADC
PG4
CORE
PF0
CORE
VSS PA2 VSS VDDGPU PA1 VSS DDR_A6 DDR_A17 DDR_A29
PWR_ VDD
P PWR_LP
CPU_ON
BOOT1 PC13 ANA1 VSSA PF5 VSS PF2 VSS VDDGPU PA4 VDDGPU VSS PA0
QDDR
VDDA18 USB3DR
OSC_ VDD33
R OSC_IN
OUT
BOOT3 PG1 ANA0 VBAT PC6 PA12 PA11 VDDGPU VSS PA3 COMBO
PHY
USB
_TXR
TUNE
VSS DDR_A12 VSS DDR_A31
VDD USBH_
NRSTC1 VDDA18 VDD DDR_ DDR_ DDR_
T MS
BOOT0 BOOT2 PF11 PG0 PF9 PC5 PA14 PC2 PA15 PH11 DNU
USB
COMBO
PHY
HS_TXR
TUNE
QDDR DQM0 DQ5 DQ4
PCIE_ COMBO COMBO

VDD33U VDDPCIE PCIE_ DDR_ DDR_ DDR_
U VREF- VREF+ PWR_ON PC3 PF6 PC8 PF8 PF1 PH13 PH10
CPD CLK CLKINP
CLK
OUTP
PHY_
TX1P
PHY_
RX1P
DQ3 DQ7 DQ6
JTDO- PCIE_ COMBO COMBO

USBH_ USB3DR PCIE_ DDR_ DDR_ DDR_
V TRACE
SWO
NJTRST PC4 PC12 PC11 PC9 PF7 PH12 PC0 PC1
HS_DM _DM CLKINN
CLK
OUTN
PHY_
TX1N
PHY_
RX1N
DQ2 DQS0N DQS0P
DT73148V1
COMBO VDD
W VSS
JTMS-
SWDIO
JTDI
JTCK-
SWCLK
PC7 PC10 PF4 PH9 PA13 PF3
USBH_
HS_DP
USB3DR
_DP
UCPD1_
CC1
UCPD1_
CC2
PHY_
REXT
COMBO
PHYTX
DDR_
DQ1
DDR_
DQ0
VSS
1. The above figure shows the package top view.

2. VDDGPU, VDDA18DSI, VDDDSI, VDDA18LVDS, and VDDLVDS are DNU on product without the related
feature (respectively GPU/NPU, DSI and LVDS) and must be connected to VSS. DSI_xxx and LVDSx_xxx are
DNU on product without the related feature (respectively DSI and LVDS) and must be left open. See Section 2
for details on feature availability. Alternatively, for PCB compatibility purposes, those balls could be connected
in same ways as for a product with enabled feature. Refer to AN5489 for additional details.
DS14284 - Rev 2 page 48/234

Figure 7. STM32MP25xC/F VFBGA424 pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
A VSS VSS
CSI_
D0N
DSI_
D3P
DSI_
D2N
DSI_
D1N
PB11 PB2 PD11 PD6 PD1 PE6 PE9 PB13 VSS
B LVDS2
_D0P
LVDS2
_D0N
CSI_
D0P
CSI_
D1P
DSI_
D3N
DSI_
D2P
DSI_
D0P
DSI_
D1P
PB10 PB0 PB3 PB4 PD0 PD5 PE0 PE4 PE7 PE11 PE14 PD12 PI11
C LVDS2
_D1P
LVDS2
_D1N
CSI_
CKP
CSI_
D1N
VSS
DSI_
CKP
DSI_
CKN
DSI_
D0N
VSS PB7 PB1 PB6 PB5 PD9 PD8 PD10 PD4 PE1 PE2 PE3 PE5 PE8 PE13 PE12 PB12 PB14
D LVDS2
_D2N
CSI_
CKN
DSI_
REXT
PB8
VDDIO
3
PD2
VDDIO
1
PI10
VDDIO
2
PD7 PE10 PE15 PD13
DDR_
E LVDS2
_D3P
LVDS2
_D3N
LVDS2
_D2P
VDD
CSI
VSS
VDDIO
4
VDDIO
3
VDDIO
1
PD15
VDDIO
2
PD14 RESET
N
DDR_
A23
DDR_
DQ19
DDR_
DQ17
DDR_
F LVDS2
_D4P
LVDS2
_D4N
VSS
VDD
LVDS
CSI_
REXT
VDD
DSI
PB9 VSS VSS VSS
VDD
CPU
VDDA1
8DDR
DDR_
A22
DDR_
DQ18
DDR_
DQ16
DQS2
N
DDR_
DQS2P
G LVDS1
_D0P
LVDS1
_D0N
VDDA1
8LVDS
VDDA1
8CSI
VDDA1
8DSI
VDDIO
4
PD3
VDD
CPU
VDD
CPU
VDDA1
8PLL1
DDR_
VREF
DDR_
A18
DDR_
DQ23
DDR_
DQ22
DDR_
DQM2
H LVDS1 LVDS1 VDDA1 1 2 3 4 5 6 7 8 9 10 11 12 DDR_ DDR_ DDR_

_D1P _D1N 8PLL2 A21 A17 DQ21
1A VSS VSS VSS VSS VSS VSS
J LVDS1
_D2P
LVDS1
_D2N
PI6 PI7 VSS
DDR_
A20
DDR_
A16
DDR_
DQ20
DDR_
DQ24
1B VSS VSS VSS VSS VSS VSS
K LVDS1
_D4P
LVDS1
_D4N
VSS PI5 PG15
DDR_
ZQ
DDR_
A13
DDR_
DQ25
DDR_
DQ26
DDR_
DQ27
VDDC VDDC VDDC VDDC VDDC VDDQ
1C ORE ORE ORE PU PU DDR DDR_
L LVDS1 LVDS1
PG8 PI0
DDR_ DDR_ DDR_ DDR_
DQS3
_D3P _D3N A19 A12 DQ28 DQS3P

VDDC VDDC VDDC VDDC VDDC VDDQ N
1D ORE ORE PU PU PU DDR
M PG9 PG10 PI1
VDDQ
DDR
DDR_
A14
DDR_
DQM3
VDDA1 VDDC VDDC VDDQ
1E 8PLL3 ORE ORE
VSS VSS
DDR
N PG14 PG11 PG12 PI2 PI3
VDDQ
DDR
DDR_
A15
DDR_
DQ29
DDR_
DQ30
VDDC VDDC VDDQ
1F ORE ORE
VSS VSS VSS
DDR
P PG13 PF13 PF14 PF12 PI4
DDR_
A3
DDR_
A11
DDR_
DQ31
DDR_
DQ11
DDR_
DQ10
VDDG VDDG
1G VSS VSS VSS
PU PU
VSS
DDR_
R PF15 PG5 PZ5
V08
CAP
VDDQ
DDR
DDR_
A10
DQS1
N
DDR_
DQ9
DDR_
DQ8
VDDG VDDG VDDG
1H VSS VSS
PU PU PU
VSS
T PG6 PZ0 VBAT

DDR_
A9
DDR_
A5
DDR_
DQS1P
1J VSS VSS VSS VSS VSS VSS
U PI9 PG7 PZ9 PI8 PZ1

DDR_
A0
DDR_
A4
DDR_
DQ15
DDR_
DQM1
1K VSS VSS VSS VSS VSS VSS
V PZ8 PZ7 PZ4 PZ6 VSS

DDR_
A8
DDR_
A2
DDR_
DQ14
DDR_
DQ12
DDR_
DQ13
VDDG VDDG VDDQ
1L VDD VDD VDD
PU PU DDR
W PDR_
ON
NRST
C1MS
PZ2 PC13
DDR_
A25
DDR_
A31
DDR_
DQ4
DDR_
DQ6
DDR_
DQ5
VDDG VDDG VDDG VDDQ
1M VDD VDD
PU PU PU DDR
Y BOOT0 VSS PZ3
DDR_
A29
DDR_
A6
DDR_
DQ7
JTCK- DDR_
AA OSC32
_OUT
OSC32
_IN
BOOT1 SW
CLK
PG3 PC3 PF5 PH9 PF0 PA8
UCPD1
_CC2
DDR_
A30
DDR_
A27
DDR_
DQS0P
DQS0
N
PWR_ VDDC VDDC
AB BOOT2 BOOT3
VDDA1
8AON
CPU_
ON
VDDA1
8ADC
PF7 PC6 PA14 PC0 PH4
UCPD1
_CC1
OMBO
PHY
OMBO
PHYTX
DDR_
A26
DDR_
DQM0
DDR_
DQ0
DDR_
DQ2
JTDO- VDDP
AC TRACE
SWO
VSSA
ON
VSSA PF6 PC4 VSS PA12 PF2 PH2 PA1 CIE
CLK
DDR_
A28
DDR_
A7
DDR_
DQ1
DDR_
DQ3
COMB
AD PWR_
ON
PG1 PG4 PC11 PC5 PA11 PA13 PH8 PA3 DNU
VDDA1
8USB
OPHY_
TX1N
DDR_
A1
USBH_ VDDA1
COMB PCIE_ PCIE_
AE NRST
JTMS-
SWDIO
JTDI PF11 PF10 PB15 PC12 PF9 PC9 PF8 PF1 PC2 PA15 PH11 PA10 PH7 PA5 PA7 PH3
HS_TX
RTUN
VDD33
USB
VDD33
UCPD
8COM
BOPH
OPHY_
TX1P
CLKIN
P
CLKIN
N
E Y
USB3D COMB PCIE_ COMB
AF PWR_ OSC_ NJT
PA0 VREF- PG0 PC7 PF4 PF3 PH12 PH10 PA9 PA2 PA6 PH6
USBH_ USB3D
R_TXR OPHY_ CLKO OPHY_
DT73146V1
LP OUT RST HS_DP R_DP

TUNE RX1N UTP REXT
USBH_ COMB PCIE_
AG VSS
OSC_
IN
PG2 VREF+ PC8 PC10 PH13 PC1 PA4 PH5 HS_
DM
USB3D
R_DM
OPHY_
RX1P
CLKO
UTN
VSS

DS14284 - Rev 2 page 49/234

Figure 8. STM32MP25xC/F TFBGA436 pinout
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
A VSS
LVDS2_
D1P
LVDS2_
D1N
LVDS2_
D0P
DSI_D3P
DSI_
CKP
PB10 PB9 PD6 PE0 PE10 PE14 PD12 VSS
B LVDS2_
D4P
LVDS2_
D4N
LVDS2_
D2N
LVDS2_
D0N
CSI_D0N DSI_D3N
DSI_
CKN
DSI_D0N PB5 PB11 PD9 PD5 PE1 PE4 PE13 PB12 PD13
DDR_
DQ19
C LVDS2_
D3P
LVDS2_
D3N
LVDS2_
D2P
VDDA18
LVDS
CSI_D0P
CSI_
CKP
VDDA18
DSI
DSI_D2P DSI_D0P PB2 PB0 PB6 PD8 PD4 PD3 PE2 PE5 PE8 PE12 PB14
DDR_
DQ18
DDR_
DQ17
D LVDS1_
D1N
LVDS1_
D1P
LVDS1_
D0N
LVDS1_
D0P
VDDCSI
CSI_
CKN
CSI_D1P DSI_D2N DSI_D1P PB4 PB1 PB7 PD10 PD0 PD7 PE3 PE7 PE9 PB13
DDR_
DQ16
DDR_
DQS2P
DDR_
DQS2N
E LVDS1_
D2P
LVDS1_
D2N
VSS
CSI_
REXT
CSI_D1N
DSI_
REXT
DSI_D1N PB3 PI15 PK1 PD11 PD2 PD1 PE6 PE11 PI11
DDR_
DQ22
DDR_
DQ23
DDR_
DQM2
F LVDS1_
D3P
LVDS1_
D3N
LVDS1_
D4P
LVDS1_
D4N
VDDA18
CSI
VDDDSI VDDIO3 VDDIO3 VDDIO2 PK4 PK0 PK2 PK5 PK3 PD15 PE15
DDR_
RESETN
DDR_
DQ21
DDR_
DQ20
G PI12 PI13 PG9 PG14 PI0 VSS

VDD
LVDS
VDDIO4 VDDIO4 VDDIO1 PB8 PK6 PI14 PK7 PD14 PI10
VDDA18
PLL1
DDR_
A20
DDR_
DQ24
DDR_
DQ27
DDR_
DQ26
DDR_
DQ25
H PF14 PG6 PG10 PG15 PI5 PI1

VDD
CORE
VSS
VDD
CORE
VSS VDDCPU VSS VDDCPU VSS VDDCPU VSS
DDR_
A22
DDR_
A17
DDR_
A18
DDR_
DQM3
DDR_
DQS3N
DDR_
DQS3P
J PG12 PG11 PI2 PI3 PI6

VDD
CORE
VSS
VDD
CORE
VSS VDDCPU VSS VDDCPU VSS
VDDA18
DDR
DDR_
A23
DDR_
A16
DDR_
A21
DDR_
DQ29
DDR_
DQ28
K PJ15 PF12 PG7 PG13 PI4 PI9

VDDA18
PLL2
VDD
CORE
VSS
VDD
CORE
VSS VDDCPU VSS
VDD
QDDR
DDR_ZQ
DDR_
A19
DDR_
A13
DDR_
A12
DDR_
DQ30
L PG5 PJ12 PJ14 PF13 PG8 PI7 PF15

VDDA18
PLL3
VSS
VDD
CORE
VSS VDDCPU VSS
VDD
QDDR
VSS
VDD
QDDR
DDR_
A15
DDR_
A14
DDR_
DQ31
DDR_
VREF
DDR_
DQ10
DDR_
DQ11
M PJ9 PJ8 PJ10 PJ13 PJ11 PI8 VSSAON V08CAP VDD VSS
VDD
GPU
VSS
VDD
GPU
VSS
VDD
QDDR
DDR_A0 DDR_A3
DDR_
A28
DDR_A5 VSS
DDR_
DQ8
DDR_
DQ9
N PZ9 PZ3 PZ0 PZ1 VSS VDD VSS

VDD
GPU
VSS
VDD
GPU
VSS
VDD
QDDR
VSS DDR_A2
DDR_
A11
DDR_
A10
DDR_A4
DDR_
DQS1P
DDR_
DQS1N
P PZ7 PZ8 PZ2 PZ5 PC13 VBAT VSS VDD VSS VDD VSS
VDD
GPU
VSS
VDD
QDDR
DDR_
A31
DDR_
A30
DDR_A9 DDR_A8
DDR_
DQM1
R OSC32_
IN
OSC32_
OUT
BOOT1 BOOT0 PZ4 PZ6
VDDA18
AON
VDD VSS VDD VSS VDD
GPU
VSS VDD
QDDR
VSS
VDD
QDDR
DDR_
A25
DDR_
A27
DDR_
A26
DDR_
DQ13
DDR_
DQ14
DDR_
DQ15
T BOOT3 BOOT2
NRST
C1MS
VSS
PWR_
ON
PWR_
CPU_ON
PDR_ON PC10 PF7 PA15 PH11 PA9 PH7 PA3
UCPD1_
CC1
VDD33
UCPD
UCPD1_
CC2
DDR_A6
DDR_
A29
DDR_
DQ5
DDR_
DQ4
DDR_
DQ12
U NRST PWR_LP PJ6 VSS VSSA PC9 PC5 PA14 PH10 PA12 PA10 PH8 PJ0 DNU
VDDA18
USB
DDR_A1 DDR_A7
DDR_
DQ7
DDR_
DQ6
USBH_ USB3DR VDD

V OSC_
OUT
OSC_IN PJ5 ANA0 ANA1
VDDA18
ADC
PC8 PC4 PF2 PC1 PF0 PH2 PA6 PA1 HS_TX
RTUNE
_TX
RTUNE
VDDPCI
ECLK
COMBO
PHY
DDR_
DQS0P
JTDO- VDDA18
W TRACE
SWO
PJ7 PJ4 PG3 VREF- PG1 PG0 VSS PC3 PF3 PF1 PA11 PA2 PH3 PA8 VSS
USB3DR
_DP
COMBO
PHY
VSS
DDR_
DQS0N
DDR_
DQM0
DDR_
DQ0
VDD COMBO
Y JTMS-
SWDIO
PA0 PJ1 PG2 VREF+ PF11 PC12 PC7 PF5 PF4 PC2 PA13 PA5 PA7 PA4
VDD33
USB
USB3DR
_DM
PCIE_
CLKINP
COMBO
PHYTX
PHY_
REXT
DDR_
DQ1
DDR_
DQ2
COMBO COMBO PCIE_

AA JTCK-
SWCLK
NJTRST PJ3 PG4 PF10 PF9 PF8 PC6 PH12 PC0 PH6 PH5
USBH_
HS_DP
PCIE_
CLKINN
PHY_
TX1P
PHY_
RX1P
CLKOUT
P
DDR_
DQ3
DT73147V1
COMBO COMBO PCIE_

AB VSS JTDI PJ2 PB15 PC11 PF6 PH13 PH9 PH4
USBH_
HS_DM
PHY_
TX1N
PHY_
RX1N
CLKOUT
N
VSS

DS14284 - Rev 2 page 50/234

Table 9. I/O power domains
Supply pin Pin names(1)
NRSTC1MS, PA0, PA1, PA10, PA11, PA12, PA13, PA14, PA15, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PB12, PB13,
PB14, PB15, PC0, PC1, PC10, PC11, PC12, PC2, PC6, PC7, PC8, PC9, PD12, PD13, PD14, PD15, PF0, PF1, PF10, PF11,
PF12, PF13, PF14, PF15, PF2, PF3, PF4, PF5, PF8, PF9, PG0, PG10, PG11, PG12, PG13, PG14, PG15, PG2, PG4, PG5,
VDD PG6, PG7, PG8, PG9, PH10, PH11, PH12, PH13, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PI0, PI1, PI10, PI11, PI12,
PI13, PI14, PI15, PI2, PI3, PI4, PI5, PI6, PI7, PI9, PJ0, PJ1, PJ10, PJ11, PJ12, PJ13, PJ14, PJ15, PJ2, PJ3, PJ4, PJ5, PJ6,
PJ7, PJ8, PJ9, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PWR_CPU_ON, PWR_LP, PWR_ON, PZ7, PZ8, PZ9, JTCK-
SWCLK, JTDI, JTDO-TRACESWO, JTMS-SWDIO, NJTRST, NRST
VDDIO1(2) PE0, PE1, PE2, PE3, PE4, PE5
VDDIO2(3) PE10, PE11, PE12, PE13, PE14, PE15, PE6, PE7, PE8, PE9
VDDIO3(4) PD0, PD1, PD10, PD11, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9
VDDIO4(5) PB0, PB1, PB10, PB11, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9
VDDA18AON OSC_IN, OSC_OUT, PDR_ON
VSW(6) OSC32_IN, OSC32_OUT, PC13, PI8, PZ0, PZ1, PZ2, PZ3, PZ4, PZ5, PZ6
VDD/VSW(6)(7) PC3, PC4, PC5, PF6, PF7, PG1, PG3

1. Does not includes analog peripherals which have one or more dedicated supplies (for example PHYs).
2. Usually used for SD-Card using SDMMC1.
3. Usually used for e.MMC or SD-Card using SDMMC2.
4. Usually used for OCTOSPIM_P1.
5. Usually used for OCTOSPIM_P2.
6. VSW is supplied by VBAT in absence of VDD.
7. Pins with two supplies: VSW supply for enabled TAMP_INx additional function, VDD supply for GPIO and other alternate function.
DS14284 - Rev 2 page 51/234

4.2 Ball description
DS14284 - Rev 2
Table 10. Legend/abbreviations used in the ballout table
Name Abbreviation Definition
Unless otherwise specified, the function during and after reset is the same as the actual pin/ball name
Pin name
DNU (do not use) Represent a pin/ball that must be left unconnected (open) at application level unless otherwise noted.
S Supply pin
I Input only pin

Pin type O Output only pin
I/O Input/output pin
A Analog or special level pin
TT(U/D/PD) 3.6 V capable I/O (with fixed pull-up/pull-down/programmable pull-down)(1)

DDR 1.35 V, 1.2 V, or 1.1 V I/O for DDR3L, DDR4 or LPDDR4 interface
A Analog signal
I/O structure RST Reset pin with weak pull-up resistor

Option for TT I/Os
_f(2) I3C option
_a(2) Analog option (supplied by VDDA18ADC for the analog part of the I/O)

Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected/enabled through peripheral registers
1. 3.6 V capable only if related I/O supply is 3.3 V typ. and related VDDIOxVRSEL = 0.
2. The related I/O structures in table below are TT_f, TT_a and TT_af.
Note: Alternate functions listed in following tables may be absent in some devices or packages (see Section 2 for details).
page 52/234
Table 11. STM32MP25xC/F ball definitions
DS14284 - Rev 2
Pin number
VFBGA361 I/O
VFBGA424
TFBGA436
Pin name (function
Pin type structur Notes Alternate functions Additional functions
after reset)
e
ADC1_INP0,
ADC1_INN1,
ADC2_INP0,
R5 - V5 ANA0 A A - -

ADC2_INN1,
ADC3_INP0,
ADC3_INN1
ADC1_INP1,
P5 - V6 ANA1 A A - - ADC2_INP1,
ADC3_INP1
T2 Y3 R4 BOOT0 I TTPD (1) - -
P3 AA3 R3 BOOT1 I TTPD (1) - -
T3 AB1 T2 BOOT2 I TTPD (1) - -
R3 AB2 T1 BOOT3 I TTPD (1) - -
W13 AB18 T15 UCPD1_CC1 A A - - UCPD1_CC1

W14 AA19 T17 UCPD1_CC2 A A - - UCPD1_CC2
C2 D4 D6 CSI_CKN A A - - -

C1 C4 C6 CSI_CKP A A - - -
E1 A3 B5 CSI_D0N A A - - -
E2 B3 C5 CSI_D0P A A - - -
D2 C5 E7 CSI_D1N A A - - -
D1 B5 D7 CSI_D1P A A - - -
E3 F6 E6 CSI_REXT A A - - -
F17 U21 M16 DDR_A0 O DDR - - -
G17 AD25 U18 DDR_A1 O DDR - - -
J17 V24 N16 DDR_A2 O DDR - - -
J19 P22 M17 DDR_A3 O DDR - - -
M17 U23 N19 DDR_A4 O DDR - - -
page 53/234
L17 T24 M19 DDR_A5 O DDR - - -

N17 Y24 T18 DDR_A6 O DDR - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
P17 AC25 U19 DDR_A7 O DDR - - -

H18 V22 P19 DDR_A8 O DDR - - -
E18 T22 P18 DDR_A9 O DDR - - -

G18 R23 N18 DDR_A10 O DDR - - -
F18 P24 N17 DDR_A11 O DDR - - -
R17 L23 K19 DDR_A12 O DDR - - -
J18 K24 K18 DDR_A13 O DDR - - -

K18 M24 L18 DDR_A14 O DDR - - -
L18 N23 L17 DDR_A15 O DDR - - -
M18 J23 J18 DDR_A16 O DDR - - -
N18 H24 H18 DDR_A17 O DDR - - -
P18 G23 H19 DDR_A18 O DDR - - -
- L21 K17 DDR_A19 O DDR - - -
E19 J21 G18 DDR_A20 O DDR - - -

F19 H22 J19 DDR_A21 O DDR - - -
G19 F22 H17 DDR_A22 O DDR - - -
H19 E23 J17 DDR_A23 O DDR - - -
H17 W21 R17 DDR_A25 O DDR - - -
K19 AB24 R19 DDR_A26 O DDR - - -
L19 AA23 R18 DDR_A27 O DDR - - -
M19 AC23 M18 DDR_A28 O DDR - - -
N19 Y22 T19 DDR_A29 O DDR - - -
P19 AA21 P17 DDR_A30 O DDR - - -
R19 W23 P16 DDR_A31 O DDR - - -
T17 AB25 W21 DDR_DQM0 O DDR - - -
page 54/234
C19 U26 P20 DDR_DQM1 O DDR - - -

- G27 E21 DDR_DQM2 O DDR - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
- M25 H20 DDR_DQM3 O DDR - - -

V18 AA26 W20 DDR_DQS0N I/O DDR - - -
B18 R25 N21 DDR_DQS1N I/O DDR - - -

- F26 D22 DDR_DQS2N I/O DDR - - -
- L27 H21 DDR_DQS3N I/O DDR - - -
V19 AA25 V20 DDR_DQS0P I/O DDR - - -
B19 T25 N20 DDR_DQS1P I/O DDR - - -

- F27 D21 DDR_DQS2P I/O DDR - - -
- L26 H22 DDR_DQS3P I/O DDR - - -
V17 AB27 Y22 DDR_DQ2 I/O DDR - - -
U17 AC27 AA22 DDR_DQ3 I/O DDR - - -
W17 AC26 Y21 DDR_DQ1 I/O DDR - - -
W18 AB26 W22 DDR_DQ0 I/O DDR - - -
U18 Y25 U20 DDR_DQ7 I/O DDR - - -

U19 W26 U21 DDR_DQ6 I/O DDR - - -
T19 W25 T21 DDR_DQ4 I/O DDR - - -
T18 W27 T20 DDR_DQ5 I/O DDR - - -
D19 V26 T22 DDR_DQ12 I/O DDR - - -
C18 U25 R22 DDR_DQ15 I/O DDR - - -
D17 V25 R21 DDR_DQ14 I/O DDR - - -
D18 V27 R20 DDR_DQ13 I/O DDR - - -
A18 R26 M22 DDR_DQ9 I/O DDR - - -
C17 R27 M21 DDR_DQ8 I/O DDR - - -
A17 P26 L22 DDR_DQ11 I/O DDR - - -
B17 P27 L21 DDR_DQ10 I/O DDR - - -
page 55/234
- J25 F20 DDR_DQ20 I/O DDR - - -

- H25 F19 DDR_DQ21 I/O DDR - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
- G25 E20 DDR_DQ23 I/O DDR - - -

- G26 E19 DDR_DQ22 I/O DDR - - -
- E25 B22 DDR_DQ19 I/O DDR - - -

- F25 D20 DDR_DQ16 I/O DDR - - -
- F24 C21 DDR_DQ18 I/O DDR - - -
- E26 C22 DDR_DQ17 I/O DDR - - -
- P25 L19 DDR_DQ31 I/O DDR - - -

- N26 K20 DDR_DQ30 I/O DDR - - -
- L25 J21 DDR_DQ28 I/O DDR - - -
- N25 J20 DDR_DQ29 I/O DDR - - -
- K25 G22 DDR_DQ25 I/O DDR - - -
- K26 G21 DDR_DQ26 I/O DDR - - -
- K27 G20 DDR_DQ27 I/O DDR - - -
- J26 G19 DDR_DQ24 I/O DDR - - -

K17 G21 L20 DDR_VREF A A - - -
E17 E21 F18 DDR_RESETN O DDR - - -
G16 K22 K16 DDR_ZQ A A - - -
A4 C8 B8 DSI_CKN A A - - -
B4 C7 A8 DSI_CKP A A - - -
A5 C9 B9 DSI_D0N A A - - -
B5 B9 C9 DSI_D0P A A - - -
A6 A10 E9 DSI_D1N A A - - -
B6 B10 D9 DSI_D1P A A - - -
B3 A7 D8 DSI_D2N A A - - -
A3 B7 C8 DSI_D2P A A - - -
page 56/234
B2 B6 B7 DSI_D3N A A - - -
A2 A6 A7 DSI_D3P A A - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
C4 D6 E8 DSI_REXT A A - - -
W4 AA5 AA1 JTCK-SWCLK I TTD (1) - -
W3 AE3 AB2 JTDI I TTU (1) - -

V1 AC2 W1 JTDO-TRACESWO O TTU (1) - -
W2 AE2 Y1 JTMS-SWDIO I/O TTU (1) - -
F1 G3 D3 LVDS1_D0N A A (2) - -
F2 G2 D4 LVDS1_D0P A A (2) - -
F3 H4 D1 LVDS1_D1N A A (2) - -
F4 H3 D2 LVDS1_D1P A A (2) - -
G3 J2 E4 LVDS1_D2N A A (2) - -
G4 J1 E3 LVDS1_D2P A A (2) - -
J2 L3 F3 LVDS1_D3N A A (2) - -
J3 L2 F2 LVDS1_D3P A A (2) - -
H3 K2 F5 LVDS1_D4N A A (2) - -

H4 K1 F4 LVDS1_D4P A A (2) - -
- B2 B4 LVDS2_D0N A A (2) - -
- B1 A4 LVDS2_D0P A A (2) - -
- C3 A3 LVDS2_D1N A A (2) - -
- C2 A2 LVDS2_D1P A A (2) - -
- D3 B3 LVDS2_D2N A A (2) - -
- E3 C3 LVDS2_D2P A A (2) - -
- E2 C2 LVDS2_D3N A A (2) - -
- E1 C1 LVDS2_D3P A A (2) - -
- F2 B2 LVDS2_D4N A A (2) - -
page 57/234
- F1 B1 LVDS2_D4P A A (2) - -
V2 AF3 AA2 NJTRST I TTU (1) - -

DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
N2 AE1 U3 NRST I/O RST (1) - -
T1 W3 T3 NRSTC1MS O TT (3) - -
LPTIM1_CH2, SPI5_RDY, UART8_CTS, SAI2_MCLK_B,

(1) UART5_TX(boot), USART3_TX, TIM3_ETR, TIM5_CH2,
P15 AF5 Y2 PA0 I/O TT_a WKUP1
ETH2_MII_RXD2, FMC_NL, DCMI_D9/PSSI_D9/DCMIPP_D9,
EVENTOUT
SPI6_MISO, SAI3_SD_A, USART1_RTS/USART1_DE,
(1) USART6_CK, TIM4_CH2, I2C4_SDA, I2C6_SDA, LCD_R3,

N15 AC19 V15 PA1 I/O TT_af -
DCMI_D5/PSSI_D5/DCMIPP_D5, ETH3_PHY_INTN,
EVENTOUT
LPTIM2_IN1, SPI7_MISO, MDF1_SDI7, USART1_RX,
(1) I3C1_SDA, I2C1_SDA, LCD_B0, DCMI_D3/PSSI_D3/
N12 AF17 W13 PA2 I/O TT_af -
DCMIPP_D3, ETH3_RGMII_RX_CTL/ETH3_RMII_CRS_DV,
EVENTOUT
LPTIM2_ETR, SPI7_MOSI, MDF1_CKI7, USART1_TX,
(1) I3C1_SCL, I2C7_SMBA, I2C1_SCL, LCD_B1, DCMI_D2/
R12 AD18 T14 PA3 I/O TT_af -
PSSI_D2/DCMIPP_D2, ETH3_RGMII_TX_CTL/
ETH3_RMII_TX_EN, EVENTOUT
(1) USART2_TX(boot), FDCAN2_TX, TIM2_CH1, LCD_R1,

P12 AG17 Y15 PA4 I/O TT_a -

ETH1_PTP_AUX_TS, ETH3_PPS_OUT, EVENTOUT
SPI4_MOSI, SAI2_MCLK_B, SAI2_SD_B, USART2_RTS/
(1) USART2_DE, FDCAN2_RX, TIM2_CH4, LCD_G0, FMC_A0,
J12 AE17 Y13 PA5 I/O TT -
DCMI_D13/PSSI_D13/DCMIPP_D13, ETH3_RGMII_RX_CLK/
ETH3_RMII_REF_CLK, EVENTOUT
SPI4_SCK, SAI2_FS_B, MDF1_SDI6, USART2_CK,
(1) TIM13_CH1, TIM2_ETR, LCD_G4, FMC_NE1, DCMI_D12/
M14 AF18 V14 PA6 I/O TT -
PSSI_D12/DCMIPP_D12, ETH3_RGMII_TXD0/
ETH3_RMII_TXD0, EVENTOUT
AUDIOCLK, SPI6_RDY, PCIE_CLKREQN, MDF1_CCK0,
USART1_CTS/USART1_NSS, TIM4_ETR, I2C2_SMBA,
K15 AE18 Y14 PA7 I/O TT (1) I2C6_SMBA, LCD_B5, I2C3_SMBA, I2C4_SMBA, DCMI_D6/ -
PSSI_D6/DCMIPP_D6, ETH3_RGMII_TXD1/
ETH3_RMII_TXD1, EVENTOUT
LPTIM2_CH2, SPI7_NSS, SAI1_FS_B, USART1_CK,
K9 AA17 W15 PA8 I/O TT_f (1) USART2_RX(boot), I2C5_SCL, LCD_B2, DCMI_D4/PSSI_D4/ -
page 58/234
DCMIPP_D4, EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI4_NSS, SAI2_SCK_B, USART2_CTS/USART2_NSS,

(1) LPTIM5_ETR, TIM2_CH3, ETH1_MDC, LCD_G7, PSSI_D14/
K12 AF15 T12 PA9 I/O TT -
DCMIPP_D14, ETH3_RGMII_RXD0/ETH3_RMII_RXD0,
EVENTOUT

SPI4_MISO, SAI2_SD_B, USART2_RX, LPTIM5_IN1,
M15 AE15 U13 PA10 I/O TT (1) TIM2_CH2, ETH1_MDIO, LCD_R6, PSSI_D15/DCMIPP_D15, -
ETH3_RGMII_RXD1/ETH3_RMII_RXD1, EVENTOUT
SPI8_SCK, LPTIM2_CH1, SAI4_SD_B, MDF1_SDI4,
R9 AD12 W12 PA11 I/O TT (1) ETH1_MII_RX_DV/ETH1_RGMII_RX_CTL/ -

ETH1_RMII_CRS_DV, EVENTOUT
(1) SPI6_MOSI, SAI3_FS_A, TIM4_CH1, I2C4_SCL, I2C6_SCL,

R8 AC13 U12 PA12 I/O TT_f -
ETH1_PHY_INTN, EVENTOUT
SPI8_RDY, I2S3_MCK, LPTIM2_ETR, MDF1_CKI3,
W9 AD14 Y12 PA13 I/O TT (1) USART2_CTS/USART2_NSS, I2C7_SMBA, ETH1_MII_TX_EN/ -
ETH1_RGMII_TX_CTL/ETH1_RMII_TX_EN, EVENTOUT
SPI8_NSS, LPTIM2_CH2, SAI4_FS_B, MDF1_CCK1,
T8 AB12 U10 PA14 I/O TT (1) ETH1_MII_RX_CLK/ETH1_RGMII_RX_CLK/ -
ETH1_RMII_REF_CLK, EVENTOUT
SPI3_MISO/I2S3_SDI, USART2_RX, I2C7_SDA,

T10 AE13 T10 PA15 I/O TT_f (1) ETH1_MII_TXD0/ETH1_RGMII_TXD0/ETH1_RMII_TXD0, -
EVENTOUT
(4) SPI2_SCK/I2S2_CK, USART1_CK, TIM16_CH1, TIM20_CH4N,

B8 B13 C11 PB0 I/O TT -
OCTOSPIM_P2_IO0(boot), EVENTOUT
(4) SPI3_NSS/I2S3_WS, TIM16_CH1N, TIM20_CH3N,

D9 C12 D11 PB1 I/O TT -
OCTOSPIM_P2_IO1(boot), FMC_NCE4, EVENTOUT
SPI2_MOSI/I2S2_SDO, MDF1_CKI3, TIM17_BKIN,
E9 A14 C10 PB2 I/O TT (4) TIM16_BKIN, TIM20_CH2N, OCTOSPIM_P2_IO2(boot), -
EVENTOUT
(4) SPI2_NSS/I2S2_WS, MDF1_SDI3, TIM20_CH3,

A9 B14 E10 PB3 I/O TT -
OCTOSPIM_P2_IO3(boot), FMC_NCE3, EVENTOUT
SPI2_RDY, UART4_CTS, SAI4_FS_B, MDF1_SDI4,
C9 B15 D10 PB4 I/O TT_f (4) TIM14_CH1, TIM20_CH2, I2C2_SDA, -
OCTOSPIM_P2_IO4(boot), I3C2_SDA, EVENTOUT
I2S2_MCK, UART4_RTS/UART4_DE, SAI4_SD_B,
page 59/234
(4) MDF1_CKI4, TIM20_CH1, I2C2_SCL,

B9 C14 B11 PB5 I/O TT_f -
OCTOSPIM_P2_IO5(boot), FMC_AD8/FMC_D8(boot),
I3C2_SCL, SDMMC3_D123DIR, EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI2_MISO/I2S2_SDI, UART4_RX, SAI4_SCK_B,

C8 C13 C12 PB6 I/O TT (4) TIM20_CH1N, OCTOSPIM_P2_IO6(boot), FMC_AD9/ -
FMC_D9(boot), SDMMC3_D0DIR, EVENTOUT
SPI3_SCK/I2S3_CK, UART4_TX, SAI4_MCLK_B, TIM20_ETR,

D7 C11 D12 PB7 I/O TT (4) TIM12_CH1, OCTOSPIM_P2_IO7(boot), FMC_AD10/ -
FMC_D10(boot), SDMMC3_CDIR, EVENTOUT
SPI3_MOSI/I2S3_SDO, PCIE_CLKREQN, USART1_TX,
A7 D8 G11 PB8 I/O TT (4) TIM17_CH1, TIM20_CH4, OCTOSPIM_P2_NCS1(boot), -
FMC_AD12/FMC_D12(boot), EVENTOUT
SPI3_RDY, USART1_RTS/USART1_DE, FDCAN1_TX,
(4) TIM20_BKIN, TIM10_CH1, OCTOSPIM_P2_DQS(boot),
A8 F10 A12 PB9 I/O TT -
OCTOSPIM_P2_NCS2, FMC_AD13/FMC_D13(boot),
EVENTOUT
SPI3_MISO/I2S3_SDI, USART1_RX, TIM17_CH1N,
E12 B11 A11 PB10 I/O TT (4) OCTOSPIM_P2_CLK(boot), FMC_AD15/FMC_D15(boot), -
EVENTOUT
I2S3_MCK, USART1_CTS/USART1_NSS, FDCAN1_RX,
(4) TIM20_BKIN2, TIM12_CH2, OCTOSPIM_P2_NCLK(boot),
B7 A11 B12 PB11 I/O TT -
OCTOSPIM_P2_NCS2, FMC_AD14/FMC_D14(boot),
OCTOSPIM_P1_NCS2, EVENTOUT

UART8_CTS, TIM13_CH1, DSI_TE, SDMMC3_D2,
E14 C26 B20 PB12 I/O TT_a (1) FMC_NWAIT, DCMI_D12/PSSI_D12/DCMIPP_D12, -
EVENTOUT
(1) SPI7_SCK, SAI1_SD_B, UART8_RX, SDMMC3_CK,

G15 A26 D19 PB13 I/O TT_a -
FMC_AD5/FMC_D5(boot), FMC_AD0/FMC_D0, EVENTOUT
SPI2_SCK/I2S2_CK, MDF1_CKI7, UART9_RX(boot),
H15 C27 C20 PB14 I/O TT (1) TIM4_CH2, SDMMC3_D0, FMC_AD7/FMC_D7(boot), -
FMC_AD2/FMC_D2, EVENTOUT
LPTIM1_IN2, SPI5_SCK, UART8_RTS/UART8_DE,
(1) SAI2_SD_B, UART5_RX(boot), TIM3_CH2, TIM5_CH1, ADC1_INP15,
J15 AE6 AB4 PB15 I/O TT_a
ETH1_PPS_OUT, FMC_A18, LCD_R4, DCMI_D8/PSSI_D8/ ADC3_INP5
DCMIPP_D8, EVENTOUT
V13 AE26 AA18 PCIE_CLKINN A - - - -
U13 AE25 Y18 PCIE_CLKINP A - - - -
page 60/234
V14 AG26 AB21 PCIE_CLKOUTN A - - - -

U14 AF26 AA21 PCIE_CLKOUTP A - - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
LPTIM1_CH1, SPI6_SCK, SAI3_MCLK_B, USART6_TX,

(1) DCMI_D0/PSSI_D0/DCMIPP_D0, ETH2_MII_RX_CLK/
V9 AB14 AA12 PC0 I/O TT -
ETH2_RMII_REF_CLK, ETH1_MII_TX_CLK,
ETH1_RGMII_GTX_CLK, LCD_G7, EVENTOUT

SPI3_MOSI/I2S3_SDO, USART2_TX, I2C7_SCL,
V10 AG14 V11 PC1 I/O TT_f (1) ETH1_MII_TXD1/ETH1_RGMII_TXD1/ETH1_RMII_TXD1, -
EVENTOUT
SPI8_MOSI, LPTIM2_IN1, SAI4_MCLK_B, MDF1_SDI3,
T9 AE12 Y11 PC2 I/O TT (1) USART2_RTS/USART2_DE, ETH1_MII_RXD1/ -

ETH1_RGMII_RXD1/ETH1_RMII_RXD1, EVENTOUT
ADC1_INP12,
LPTIM1_IN2, SPI3_NSS/I2S3_WS, SPI6_RDY, USART6_RTS/ ADC1_INN10,
USART6_DE, FDCAN2_TX, ETH2_MII_RX_DV/ ADC2_INP12,
U4 AA9 W9 PC3 I/O TT_a (5) ETH2_RGMII_RX_CTL/ETH2_RMII_CRS_DV, ADC2_INN10,
ETH1_MII_RX_ER, LCD_G6, DCMI_D3/PSSI_D3/DCMIPP_D3, ADC3_INP12,
EVENTOUT ADC3_INN10,
TAMP_IN3
SPI6_MISO, SAI3_FS_B, ETH2_MII_TX_EN/
V3 AC9 V9 PC4 I/O TT (5) ETH2_RGMII_TX_CTL/ETH2_RMII_TX_EN, TAMP_IN1
ETH1_RGMII_CLK125, LCD_R0, EVENTOUT

ADC1_INP10,
SPDIFRX1_IN1, MDF1_SDI1, TIM8_CH1N, I2C4_SDA,
(5) ADC2_INP10,
T7 AD10 U9 PC5 I/O TT_af ETH2_MDIO, ETH1_MII_COL, FMC_A25, ETH1_PPS_OUT,
ADC3_INP10,
LCD_DE, EVENTOUT
TAMP_IN6
ADC1_INP9,
RTC_REFIN, SPDIFRX1_IN0, MDF1_CKI1, TIM8_CH1,
(1) ADC1_INN5,
R7 AB10 AA10 PC6 I/O TT_af I2C4_SCL, ETH2_MDC, ETH1_MII_CRS, FMC_A24,
ADC2_INP9,
ETH1_PHY_INTN, LCD_CLK, EVENTOUT
ADC2_INN5
SPI6_MOSI, SAI3_SD_B, TIM8_CH2N, ETH2_MII_TXD0/
(1) ADC3_INP9,
W5 AF9 Y8 PC7 I/O TT_a ETH2_RGMII_TXD0/ETH2_RMII_TXD0, ETH1_MII_TXD2,
ADC3_INN5
LCD_B4, DCMI_D1/PSSI_D1/DCMIPP_D1, EVENTOUT
LPTIM1_ETR, SPI6_NSS, SAI3_SCK_B, USART6_CTS/
(1) USART6_NSS, TIM8_CH2, ETH2_MII_TXD1/
U6 AG9 V8 PC8 I/O TT_a -
ETH2_RGMII_TXD1/ETH2_RMII_TXD1, ETH1_MII_TXD3,
LCD_B3, DCMI_D2/PSSI_D2/DCMIPP_D2, EVENTOUT
MCO1, SPI3_MISO/I2S3_SDI, SAI2_SCK_A, TIM13_CH1, ADC1_INP8,
page 61/234
(1) TIM8_CH4N, USBH_HS_OVRCUR, ETH2_MII_TXD2/ ADC1_INN4,

V6 AE9 U8 PC9 I/O TT_a
ETH2_RGMII_TXD2, USB3DR_OVRCUR, FMC_A22, LCD_G2, ADC2_INP8,
DCMI_D7/PSSI_D7/DCMIPP_D7, EVENTOUT ADC2_INN4
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI3_MOSI/I2S3_SDO, LPTIM4_ETR, TIM8_CH4,

(1) USBH_HS_VBUSEN, ETH2_MII_TXD3/ETH2_RGMII_TXD3, ADC1_INP5,
W6 AG10 T8 PC10 I/O TT_a
USB3DR_VBUSEN, FMC_A23, LCD_G3, DCMI_D6/PSSI_D6/ ADC2_INP5
DCMIPP_D6, EVENTOUT

ADC1_INP7,
LPTIM1_CH1, SPI5_NSS, SAI2_MCLK_A, UART5_RTS/
ADC1_INN3,
UART5_DE, USART3_RTS/USART3_DE, TIM3_CH1,
(1) ADC2_INP7,
V5 AD8 AB7 PC11 I/O TT_a TIM5_ETR, ETH2_MII_RXD3/ETH2_RGMII_RXD3,
ADC2_INN3,
FMC_NBL1, LCD_R2, DCMI_D10/PSSI_D10/DCMIPP_D10,
ADC3_INP7,
EVENTOUT
ADC3_INN3
LPTIM1_CH2, I3C3_SCL, MDF1_CKI2, TIM8_CH3, I2C3_SCL,
(1) ETH2_MII_RXD1/ETH2_RGMII_RXD1/ETH2_RMII_RXD1,
V4 AE7 Y7 PC12 I/O TT_af ADC1_INP17
ETH1_MII_RXD3, LCD_G1, DCMI_D5/PSSI_D5/DCMIPP_D5,
EVENTOUT
RTC_OUT1/
P4 W7 P6 PC13 I/O TT (6) EVENTOUT RTC_LSCO/RTC_TS,
TAMP_OUT1
M2 AA2 R1 OSC32_IN I A (7) - OSC32_IN
M1 AA1 R2 OSC32_OUT O A (8) - OSC32_OUT

N1 W2 T7 PDR_ON I - (9) - -
TRACECLK, HDP0, SPI7_RDY, SAI1_D2, SAI4_FS_A,

(10) UART7_RX, TIM15_CH2, SDVSEL1,
C11 B17 D14 PD0 I/O TT -
OCTOSPIM_P1_CLK(boot), DCMI_PIXCLK/PSSI_PDCK/
DCMIPP_PIXCLK, EVENTOUT
HDP1, SPI1_MISO/I2S1_SDI, SAI1_CK2, SAI4_SD_A,
UART7_RTS/UART7_DE, TIM15_CH1, TIM1_BKIN,
F9 A19 E15 PD1 I/O TT (10) FDCAN3_RX, OCTOSPIM_P1_NCLK(boot), -
OCTOSPIM_P1_NCS2, OCTOSPIM_P2_NCS2,
DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, EVENTOUT
HDP2, SPI1_NSS/I2S1_WS, SAI1_CK1, SAI4_SCK_A,
(10) UART7_CTS, TIM15_BKIN, TIM1_ETR, FDCAN3_TX,
A10 D12 E14 PD2 I/O TT -
OCTOSPIM_P1_DQS(boot), OCTOSPIM_P1_NCS2,
DCMI_VSYNC/PSSI_RDY/DCMIPP_VSYNC, EVENTOUT
SAI1_MCLK_A, SPI2_SCK/I2S2_CK, SAI1_D1, SAI4_MCLK_A,
(10) UART7_TX, TIM15_CH1N, TIM1_BKIN2, SDVSEL2,
D8 G13 C15 PD3 I/O TT -
page 62/234
OCTOSPIM_P1_NCS1(boot), PSSI_D15/DCMIPP_D15,
EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
TRACED0, SPI4_MISO, HDP3, SAI1_D3, SAI1_SD_B,

C12 C18 C14 PD4 I/O TT (10) TIM1_CH4N, TIM4_CH1, OCTOSPIM_P1_IO0(boot), -
PSSI_D14/DCMIPP_D14, EVENTOUT
TRACED1, SPI4_NSS, HDP4, SAI1_D4, SAI1_FS_B,

B12 B18 B15 PD5 I/O TT (10) TIM1_CH3N, TIM4_CH2, OCTOSPIM_P1_IO1(boot), -
DCMI_D13/PSSI_D13/DCMIPP_D13, EVENTOUT
TRACED2, SPI4_MOSI, HDP5, SAI1_SCK_B, MDF1_SDI2,
A12 A18 A15 PD6 I/O TT (10) TIM1_CH2N, TIM4_CH3, OCTOSPIM_P1_IO2(boot), -
TRACED3, SPI4_SCK, SPI1_RDY, SAI1_MCLK_B,
(10) MDF1_CKI2, TIM1_CH1N, TIM4_CH4,
D12 D20 D15 PD7 I/O TT -
OCTOSPIM_P1_IO3(boot), DCMI_D11/PSSI_D11/
DCMIPP_D11, EVENTOUT
TRACED4, SPI4_RDY, I2S1_MCK, SAI1_FS_A, UART4_CTS,
(10) MDF1_SDI1, TIM1_CH4, TIM4_ETR,
E11 C16 C13 PD8 I/O TT -
OCTOSPIM_P1_IO4(boot), SDMMC1_D7, SDMMC1_D123DIR,
TRACED5, HDP6, SPI1_MOSI/I2S1_SDO, SAI1_SD_A,
(10) UART4_RTS/UART4_DE, MDF1_CKI1, TIM1_CH3,
C10 C15 B13 PD9 I/O TT -
OCTOSPIM_P1_IO5(boot), SDMMC1_D6, SDMMC1_D0DIR,

TRACED6, HDP7, SAI1_SCK_A, UART4_RX, MDF1_SDI0,
(10) I2C4_SDA, TIM1_CH2, TIM14_CH1,
D11 C17 D13 PD10 I/O TT_f -
OCTOSPIM_P1_IO6(boot), SDMMC1_D5, SDMMC1_CDIR,
TRACED7, SPI1_SCK/I2S1_CK, SAI1_MCLK_A, UART4_TX,
(10) MDF1_CKI0, I2C4_SCL, TIM1_CH1, SDVSEL1,
B10 A15 E13 PD11 I/O TT_f -
OCTOSPIM_P1_IO7(boot), SDMMC1_D4, SDMMC1_CKIN,
SPI7_MISO, SPI2_MISO/I2S2_SDI, SPDIFRX1_IN2,
H14 B26 A21 PD12 I/O TT_a (1) UART8_RTS/UART8_DE, TIM4_ETR, SDMMC3_CMD, -
FMC_AD6/FMC_D6(boot), FMC_AD1/FMC_D1, EVENTOUT
SPI2_NSS/I2S2_WS, MDF1_SDI7, UART9_TX(boot),
G9 D25 B21 PD13 I/O TT_a (1) TIM4_CH4, SDMMC3_D1, FMC_AD11/FMC_D11(boot), -
FMC_NWE, EVENTOUT
page 63/234
I2S1_MCK, FDCAN1_RX, TIM11_CH1, I2C7_SDA, FMC_AD4/

A13 E19 G15 PD14 I/O TT_af (1) FMC_D4(boot), SDMMC3_D3, DCMI_D1/PSSI_D1/ -
DCMIPP_D1, EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI1_RDY, DSI_TE, I2C5_SDA, FDCAN1_TX, TIM1_BKIN2,

(1) TIM5_ETR, I2C7_SCL, FMC_AD3/FMC_D3(boot),
A11 E15 F16 PD15 I/O TT_af -
SDMMC3_CKIN, DCMI_D0/PSSI_D0/DCMIPP_D0,
EVENTOUT

(11) TRACED2, LPTIM2_CH1, SPI1_SCK/I2S1_CK, SPI3_RDY,
B13 B19 A16 PE0 I/O TT -
USART3_CK, SDMMC1_D2, EVENTOUT
(11) TRACED3, LPTIM2_CH2, I2S1_MCK, I2S3_MCK,

C13 C19 B16 PE1 I/O TT -
USART3_RX, SDMMC1_D3, EVENTOUT
(11) LPTIM2_ETR, SPI1_MISO/I2S1_SDI, SPI3_MOSI/I2S3_SDO,

A14 C20 C16 PE2 I/O TT -
SAI1_SCK_B, TIM10_CH1, SDMMC1_CMD(boot), EVENTOUT
(11) TRACECLK, SPI1_RDY, SPI3_SCK/I2S3_CK, SAI1_MCLK_B,

A15 C21 D16 PE3 I/O TT -
USART3_TX, TIM11_CH1, SDMMC1_CK(boot), EVENTOUT
TRACED0, LPTIM2_IN1, SPI1_MOSI/I2S1_SDO, SPI3_MISO/
B14 B21 B17 PE4 I/O TT (11) I2S3_SDI, SAI1_SD_B, USART3_CTS/USART3_NSS, -
FDCAN1_TX, SDMMC1_D0(boot), EVENTOUT
TRACED1, LPTIM2_IN2, SPI1_NSS/I2S1_WS, SPI3_NSS/
C14 C22 C17 PE5 I/O TT (11) I2S3_WS, SAI1_FS_B, USART3_RTS/USART3_DE, -
FDCAN1_RX, SDMMC1_D1, EVENTOUT
SPI4_RDY, SPDIFRX1_IN2, USART1_TX, TIM1_ETR,

F14 A22 E16 PE6 I/O TT (12) FMC_AD1/FMC_D1(boot), SDMMC2_D6, SDMMC2_D0DIR, -
EVENTOUT
SAI4_D4, SPDIFRX1_IN3, USART1_RX, TIM1_CH4N,
C15 B22 D17 PE7 I/O TT (12) TIM14_CH1, FMC_AD2/FMC_D2(boot), SDMMC2_D7, -
SDMMC2_D123DIR, EVENTOUT
SPI4_MOSI, SAI4_CK1, SAI4_MCLK_A, MDF1_CKI0,
B15 C23 C18 PE8 I/O TT (12) TIM1_CH1, FMC_A17/FMC_ALE(boot), SDMMC2_D2, -
EVENTOUT
SPI4_MISO, SAI4_D2, SAI4_FS_A, USART1_CK, TIM1_CH4,
F15 A23 D18 PE9 I/O TT (12) FMC_AD0/FMC_D0(boot), SDMMC2_D5, SDMMC2_CDIR, -
EVENTOUT
SPI4_SCK, SAI4_D1, SAI4_SD_A, USART1_CTS/
D15 D22 A19 PE10 I/O TT (12) USART1_NSS, TIM1_CH3, FMC_NE3, FMC_NCE2, -
SDMMC2_D4, SDMMC2_CKIN, EVENTOUT
(12) SPI7_SCK, SAI4_D3, SAI1_FS_A, TIM15_CH2, TIM1_CH3N,

page 64/234
B16 B23 E17 PE11 I/O TT -

FMC_A16/FMC_CLE(boot), SDMMC2_D1, EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI4_NSS, SAI4_CK2, SAI4_SCK_A, MDF1_SDI0,

C16 C25 C19 PE12 I/O TT (12) USART1_RTS/USART1_DE, TIM1_CH2, FMC_NE2, -
FMC_NCE1(boot), SDMMC2_D3, EVENTOUT
(12) SPI7_MISO, SAI1_SD_A, TIM15_CH1, TIM1_CH2N,

A16 C24 B19 PE13 I/O TT -

FMC_RNB(boot), SDMMC2_D0(boot), EVENTOUT
SPI7_NSS, SAI1_MCLK_A, MDF1_CKI6, TIM15_BKIN,
G14 B25 A20 PE14 I/O TT (12) TIM1_BKIN, FMC_NWE(boot), SDMMC2_CK(boot), -
EVENTOUT
SPI7_MOSI, SAI1_SCK_A, MDF1_SDI6, TIM15_CH1N,

D14 D24 F17 PE15 I/O TT (12) TIM1_CH1N, FMC_NOE(boot), SDMMC2_CMD(boot), -
EVENTOUT
ADC1_INP11,
(1) SPI3_SCK/I2S3_CK, FDCAN2_RX, TIM12_CH2, I2C2_SDA,
N9 AA15 V12 PF0 I/O TT_af ADC2_INP11,
ETH1_MDC, ETH2_MII_CRS, I3C2_SDA, EVENTOUT
ADC3_INP11
SPI8_MISO, LPTIM2_IN2, SAI4_SCK_B, MDF1_CKI4,
U8 AE11 W11 PF1 I/O TT (1) USART2_CK, ETH1_MII_RXD0/ETH1_RGMII_RXD0/ -
ETH1_RMII_RXD0, EVENTOUT
ADC1_INP13,
ADC1_INN11,

(1) SPI3_RDY, I2C4_SMBA, TIM12_CH1, I2C2_SCL, ETH1_MDIO, ADC2_INP13,
P9 AC15 V10 PF2 I/O TT_af
ETH2_MII_COL, FMC_NE4, I3C2_SCL, EVENTOUT ADC2_INN11,
ADC3_INP13,
ADC3_INN11
UART8_RX(boot), SAI2_SCK_B, MDF1_CCK0, TIM3_CH4,
(1) TIM8_BKIN2, ETH1_CLK, ETH2_PPS_OUT, FMC_A20, ADC1_INP16,
W10 AF11 W10 PF3 I/O TT_a
LCD_R6, DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, ADC1_INN15
EVENTOUT
RTC_OUT2, SPI6_NSS, SAI3_SCK_A, USART6_RX(boot),
W7 AF10 Y10 PF4 I/O TT (1) TIM4_CH4, ETH1_MDC, ETH2_CLK, ETH2_PPS_OUT, -
ETH1_PPS_OUT, LCD_B7, EVENTOUT
SPI6_SCK, SAI3_MCLK_A, USART6_TX(boot), TIM4_CH3,
P7 AA11 Y9 PF5 I/O TT (1) ETH1_MDIO, ETH1_CLK, ETH2_PHY_INTN, -
ETH1_PHY_INTN, LCD_B6, EVENTOUT
RTC_OUT2, SAI3_MCLK_B, USART6_CK, TIM12_CH1,
U5 AC7 AB8 PF6 I/O TT (5) I2C3_SMBA, ETH2_MII_RX_CLK/ETH2_RGMII_RX_CLK/ TAMP_IN5
page 65/234
ETH2_RMII_REF_CLK, LCD_B0, EVENTOUT

DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPDIFRX1_IN1, SPI6_SCK, SAI3_SD_A, TIM2_ETR,

V7 AB8 T9 PF7 I/O TT (5) ETH2_RGMII_GTX_CLK, ETH2_MII_TX_CLK, LCD_R1, TAMP_IN2
EVENTOUT
RTC_REFIN, SAI3_SCK_B, USART3_RX, TIM12_CH2,

(1) ETH1_CLK, ETH2_RGMII_CLK125, ETH2_MII_RX_ER,
U7 AE10 AA8 PF8 I/O TT -
ETH2_MII_RX_DV/ETH2_RMII_CRS_DV, LCD_G0,
EVENTOUT
SAI3_SD_B, SAI2_SD_A, MDF1_SDI5, UART8_RTS/
T6 AE8 AA7 PF9 I/O TT (1) UART8_DE, TIM2_CH2, ETH2_MII_RXD2/ -

ETH2_RGMII_RXD2, ETH2_MDIO, EVENTOUT
(1) MCO2, SPI3_RDY, SAI2_MCLK_A, MDF1_CKI6, UART8_TX,

L9 AE5 AA6 PF10 I/O TT_a ADC3_INP2
TIM2_CH3, ETH2_MII_TXD2, EVENTOUT
MCO1, SPDIFRX1_IN0, SPI6_RDY, SAI2_SCK_A,
(1) ADC3_INP6,
T4 AE4 Y6 PF11 I/O TT_a MDF1_SDI6, UART8_RX, TIM2_CH4, ETH2_MII_TXD3,
ADC3_INN2
EVENTOUT
TRACECLK, SPI5_MISO, SPI1_MISO/I2S1_SDI, UART9_RTS/
L7 P4 K3 PF12 I/O TT (1) UART9_DE, TIM5_CH1, LCD_CLK, DCMI_D0/PSSI_D0/ -
DCMIPP_D0, EVENTOUT
TRACED0, HDP0, AUDIOCLK, USART6_TX, SPI2_NSS/

H2 P2 L4 PF13 I/O TT (1) I2S2_WS, MDF1_CKI7, USART3_CTS/USART3_NSS, -
FDCAN3_TX, TIM3_CH3, LCD_R2, EVENTOUT
(1) TRACED1, HDP1, USART6_RX, MDF1_SDI7, USART3_RTS/

G7 P3 H1 PF14 I/O TT -
USART3_DE, FDCAN3_RX, TIM3_CH4, LCD_R3, EVENTOUT
TRACED2, HDP2, SPI2_RDY, USART6_CTS/USART6_NSS,
G5 R2 L7 PF15 I/O TT (1) SPI2_SCK/I2S2_CK, USART3_CK, TIM2_CH2, TIM3_ETR, -
I2C6_SMBA, LCD_R4, EVENTOUT
LPTIM1_IN1, I3C3_SDA, MDF1_SDI2, TIM8_CH3N,
(1) I2C3_SDA, ETH2_MII_RXD0/ETH2_RGMII_RXD0/ ADC1_INP18,
T5 AF7 W7 PG0 I/O TT_af
ETH2_RMII_RXD0, ETH1_MII_RXD2, LCD_G5, DCMI_D4/ ADC1_INN17
LPTIM1_IN1, I2S3_MCK, I3C3_SCL, SAI2_SD_A, WKUP3, ADC1_INP6,
UART5_CTS, USART3_CTS/USART3_NSS, TIM5_CH4, ADC1_INN2,
R4 AD4 W6 PG1 I/O TT_af (5) I2C3_SCL, ETH2_MII_RX_ER, ETH2_MII_RXD3, FMC_NBL0, ADC2_INP6,
LCD_VSYNC, DCMI_D11/PSSI_D11/DCMIPP_D11, ADC2_INN2,
EVENTOUT TAMP_IN4
page 66/234
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
RTC_REFIN, I2S3_MCK, I3C3_SDA, SAI2_FS_A,

(1) WKUP5, ADC1_INP2,
M7 AG5 Y4 PG2 I/O TT_af USART3_CK, TIM5_CH3, I2C3_SDA, ETH2_MII_TX_CLK,
ADC2_INP2
ETH2_RGMII_CLK125, FMC_CLK, LCD_HSYNC, EVENTOUT
LPTIM1_ETR, SPI5_MOSI, UART8_TX(boot), SAI2_FS_B, WKUP6, ADC1_INP3,

(5) TIM3_CH3, TIM8_ETR, ETH2_CLK, ETH2_PHY_INTN, ADC2_INP3,
H12 AA7 W4 PG3 I/O TT_a
FMC_A19, LCD_R5, DCMI_PIXCLK/PSSI_PDCK/ ADC3_INP3,
DCMIPP_PIXCLK, EVENTOUT TAMP_IN7
SPI5_MISO, SAI3_FS_B, LPTIM4_IN1, TIM8_BKIN,
PVD_IN, ADC1_INP4,
N7 AD6 AA4 PG4 I/O TT_a (1) ETH2_PPS_OUT, ETH2_MDC, FMC_A21, LCD_R7,
ADC2_INP4
TRACED3, HDP3, USART6_RTS/USART6_DE, TIM2_CH3,
K1 R3 L1 PG5 I/O TT_f (1) I2C6_SDA, LCD_R5, DCMI_PIXCLK/PSSI_PDCK/ -
DCMIPP_PIXCLK, EVENTOUT
TRACED4, HDP4, SPI5_SCK, SPI1_SCK/I2S1_CK,
K2 T3 H2 PG6 I/O TT_f (1) TIM2_CH4, I2C6_SCL, LCD_R6, DCMI_HSYNC/PSSI_DE/ -
DCMIPP_HSYNC, EVENTOUT
TRACED5, HDP5, SPI5_NSS, SPI1_NSS/I2S1_WS,
E7 U2 K4 PG7 I/O TT (1) UART9_CTS, TIM5_ETR, LCD_R7, DCMI_VSYNC/PSSI_RDY/ -
DCMIPP_VSYNC, EVENTOUT

TRACED6, HDP6, SPI5_RDY, SPI1_RDY, USART6_CK,
E5 L5 L5 PG8 I/O TT (1) UART5_RTS/UART5_DE, UART9_TX, TIM5_CH3, LCD_G2, -
(1) TRACED7, UART5_TX, TIM5_CH4, LCD_G3, DCMI_D3/

G2 M3 G3 PG9 I/O TT -
(1) TRACED8, HDP0, UART5_RX, TIM8_CH4N, LCD_G4,

F5 M4 H3 PG10 I/O TT -
(1) TRACED9, HDP1, SPI7_MOSI, FDCAN1_TX, TIM8_CH4,

F7 N2 J4 PG11 I/O TT -
LCD_G5, DCMI_D5/PSSI_D5/DCMIPP_D5, EVENTOUT
(1) TRACED10, HDP2, SPI7_MISO, FDCAN1_RX, TIM8_CH1N,

H7 N3 J3 PG12 I/O TT -
LCD_G6, DCMI_D6/PSSI_D6/DCMIPP_D6, EVENTOUT
TRACED11, HDP3, SPI7_SCK, MDF1_CKI6, TIM8_CH2N,
J7 P1 K5 PG13 I/O TT_f (1) I2C1_SCL, I3C1_SCL, LCD_G7, DCMI_D7/PSSI_D7/ -
DCMIPP_D7, EVENTOUT
TRACED12, HDP4, SPI7_RDY, MDF1_CKI5, USART1_TX,
page 67/234
H5 N1 G4 PG14 I/O TT (1) TIM8_BKIN2, LCD_B1, DCMI_D9/PSSI_D9/DCMIPP_D9, -

EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
TRACED13, HDP5, LPTIM1_CH2, MDF1_SDI5, USART1_RX,

E4 K6 H4 PG15 I/O TT (1) TIM8_ETR, LCD_B2, DCMI_D10/PSSI_D10/DCMIPP_D10, -
EVENTOUT
R1 AG2 V3 OSC_IN I A (13) - OSC_IN

R2 AF2 V2 OSC_OUT I/O A (14) - OSC_OUT
LPTIM2_CH1, SPI7_RDY, SPDIFRX1_IN3, SAI1_SCK_B,

L14 AC17 V13 PH2 I/O TT_f (1) I3C3_SDA, TIM16_CH1, I2C5_SDA, I2C3_SDA, -
ETH3_RGMII_GTX_CLK, EVENTOUT
(1) SPI1_NSS/I2S1_WS, UART7_RX, TIM17_CH1N, TIM5_CH3,

K14 AE19 W14 PH3 I/O TT_f -
I2C7_SCL, ETH3_RGMII_TXD3, EVENTOUT
UART7_TX, TIM17_BKIN, TIM5_CH2, LCD_R0,
G12 AB16 AB15 PH4 I/O TT (1) USB3DR_OVRCUR, USBH_HS_OVRCUR, BOOTFAILN
ETH1_PTP_AUX_TS, ETH3_PPS_OUT, EVENTOUT
SAI2_FS_A, UART8_CTS, TIM2_CH1, UART7_RX, LCD_G1,
M9 AG18 AA15 PH5 I/O TT (1) USB3DR_VBUSEN, USBH_HS_VBUSEN, WKUP2
ETH2_PTP_AUX_TS, EVENTOUT
LPTIM2_IN2, SAI1_MCLK_B, I3C3_SCL, TIM16_CH1N,
L15 AF19 AA14 PH6 I/O TT_f (1) I2C5_SCL, I2C3_SCL, I2C1_SMBA, ETH3_RGMII_TXD2, -

EVENTOUT
SPI1_MOSI/I2S1_SDO, UART4_TX, UART7_RTS/UART7_DE,
L12 AE16 T13 PH7 I/O TT_f (1) TIM17_CH1, TIM5_CH4, I2C7_SDA, ETH3_RGMII_RXD2, -
EVENTOUT
SPI1_MISO/I2S1_SDI, SPDIFRX1_IN3, UART4_RX,
M12 AD16 U14 PH8 I/O TT (1) UART7_CTS, TIM5_CH1, I2C3_SMBA, I2C5_SMBA, -
ETH3_RGMII_RXD3, EVENTOUT
(1) SPI6_NSS, SAI3_MCLK_A, USART6_RX, TIM15_CH1N,

W8 AA13 AB12 PH9 I/O TT_a ADC3_INP4
ETH1_RGMII_CLK125, ETH1_MII_RX_ER, EVENTOUT
SPI1_SCK/I2S1_CK, SPI6_MOSI, SAI3_SCK_A, TIM15_CH1,
(1) ADC3_INP8,
U10 AF14 U11 PH10 I/O TT_a ETH2_MDC, ETH1_MII_TXD2/ETH1_RGMII_TXD2,
ADC3_INN4
EVENTOUT
(1) SPI6_MISO, SAI3_FS_A, TIM15_CH2, ETH2_MDIO,

T11 AE14 T11 PH11 I/O TT_a -
ETH1_MII_TXD3/ETH1_RGMII_TXD3, EVENTOUT
(1) SPI3_NSS/I2S3_WS, SPI6_MISO, TIM10_CH1,

V8 AF13 AA11 PH12 I/O TT -
page 68/234
ETH1_MII_RXD2/ETH1_RGMII_RXD2, EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
(1) SPI3_SCK/I2S3_CK, SPI6_MOSI, TIM15_BKIN, TIM11_CH1,

U9 AG13 AB11 PH13 I/O TT -
ETH1_MII_RXD3/ETH1_RGMII_RXD3, EVENTOUT
TRACED14, HDP6, LPTIM1_IN1, SAI4_MCLK_B,
H1 L7 G5 PI0 I/O TT (1) USART1_CK, TIM8_BKIN, LCD_B3, DCMI_D11/PSSI_D11/ -

TRACED15, HDP7, SPI7_NSS, MDF1_SDI6, TIM8_CH3N,
J9 M6 H6 PI1 I/O TT_f (1) I2C1_SDA, I3C1_SDA, LCD_B4, DCMI_D8/PSSI_D8/ -
DCMIPP_D8, EVENTOUT
LPTIM1_ETR, SAI4_SCK_B, USART1_RTS/USART1_DE,

J5 N5 J5 PI2 I/O TT (1) TIM8_CH1, LCD_B5, DCMI_D13/PSSI_D13/DCMIPP_D13, -
EVENTOUT
(1) LPTIM1_IN2, SAI4_SD_B, USART1_CTS/USART1_NSS,

H9 N7 J6 PI3 I/O TT -
TIM8_CH2, LCD_B6, PSSI_D14/DCMIPP_D14, EVENTOUT
(1) LPTIM1_CH1, SAI4_FS_B, TIM8_CH3, LCD_B7, PSSI_D15/

G1 P6 K6 PI4 I/O TT -
SPI5_MOSI, SPI1_MOSI/I2S1_SDO, UART5_CTS,
K7 K4 H5 PI5 I/O TT (1) UART9_RX, TIM5_CH2, LCD_DE, DCMI_D1/PSSI_D1/ -
DCMIPP_D1, EVENTOUT
MCO1, USART3_TX, TIM2_ETR, TIM3_CH1, LCD_VSYNC,

D4 J3 J7 PI6 I/O TT (1) WKUP4
EVENTOUT
(1) USART3_RX, TIM2_CH1, TIM3_CH2, LCD_HSYNC,

D5 J5 L6 PI7 I/O TT -
EVENTOUT
RTC_OUT2/
(6) RTC_LSCO,
N4 U5 M6 PI8 I/O TT EVENTOUT
TAMP_IN1/
TAMP_OUT2
SPI7_MOSI, SPI2_MOSI/I2S2_SDO, FDCAN2_TX,
K6 U1 K7 PI9 I/O TT (1) UART9_CTS, TIM16_BKIN, SDVSEL2, FMC_NWAIT, DSI_TE, -
LCD_B0, EVENTOUT
SAI1_SCK_A, SPI1_SCK/I2S1_CK, SPDIFRX1_IN0,
B11 D16 G16 PI10 I/O TT (1) FDCAN2_RX, MDF1_CCK0, TIM4_CH1, SDVSEL1, -
FMC_AD12/FMC_D12, DSI_TE, EVENTOUT
(1) I2S2_MCK, UART8_TX, UART9_RTS/UART9_DE, TIM4_CH3,

F12 B27 E18 PI11 I/O TT -
SDMMC3_D3, FMC_AD15/FMC_D15, EVENTOUT
page 69/234
(1) SPI4_NSS, FDCAN3_RX, TIM11_CH1, FMC_A2, LCD_G0,

- - G1 PI12 I/O TT -
EVENTOUT
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
(1) SPI4_MOSI, FDCAN2_RX, TIM10_CH1, FMC_A3, LCD_G1,

- - G2 PI13 I/O TT -
EVENTOUT
SPI2_NSS/I2S2_WS, MDF1_SDI1, TIM20_CH3, TIM1_CH3N,
- - G13 PI14 I/O TT (1) FMC_NWAIT, FMC_AD10/FMC_D10, DCMI_D4/PSSI_D4/ -

DCMIPP_D4, EVENTOUT
I2S2_MCK, UART4_RX, MDF1_CKI2, TIM20_BKIN2,
- - E11 PI15 I/O TT (1) TIM1_BKIN2, SDVSEL1, SDMMC3_CDIR, DCMI_D9/PSSI_D9/ -
DCMIPP_D9, EVENTOUT
SPI5_MOSI, PCIE_CLKREQN, SAI4_D2, USART6_CTS/

- - U15 PJ0 I/O TT (1) USART6_NSS, USBH_HS_VBUSEN, ETH2_PTP_AUX_TS, -
FMC_A11, ETH3_PPS_OUT, EVENTOUT
(1) USART6_RX, TIM8_CH1N, I2C1_SCL, I3C1_SCL, FMC_A7,

- - Y3 PJ1 I/O TT_f -
(1) SAI2_SD_B, UART9_RTS/UART9_DE, TIM8_CH4N,

- - AB3 PJ2 I/O TT -
USBH_HS_OVRCUR, FMC_A14, EVENTOUT
(1) SPI5_NSS, SAI2_FS_A, SAI4_D1, USART6_RTS/

- - AA3 PJ3 I/O TT -
USART6_DE, TIM8_CH3, FMC_A10, EVENTOUT
(1) SAI2_FS_B, MDF1_CCK1, USART6_CK, TIM8_CH4,

- - W3 PJ4 I/O TT -
I2C2_SMBA, I2C5_SMBA, EVENTOUT

(1) SPI5_MISO, SAI2_SCK_B, SAI4_CK1, USART6_TX,
- - V4 PJ5 I/O TT -
TIM8_CH1, FMC_A8, EVENTOUT
SPI7_MOSI, SAI4_SD_A, USART2_CK, TIM20_CH1N,
- - U5 PJ6 I/O TT (1) TIM1_CH1, I2C6_SMBA, DCMI_D7/PSSI_D7/DCMIPP_D7, -
EVENTOUT
SPI5_MISO, SAI2_MCLK_B, SAI4_D3, USART6_CK,
- - W2 PJ7 I/O TT (1) TIM8_CH2N, I2C1_SMBA, FMC_A12, DCMI_D0/PSSI_D0/ -
DCMIPP_D0, EVENTOUT
(1) SPI5_SCK, SAI4_CK2, USART6_RX, TIM8_CH2, FMC_A9,

- - M2 PJ8 I/O TT -
(1) SPI4_RDY, TIM12_CH1, TIM8_BKIN, FMC_A5, DCMI_PIXCLK/

- - M1 PJ9 I/O TT -
PSSI_PDCK/DCMIPP_PIXCLK, EVENTOUT
(1) TIM12_CH2, TIM8_ETR, I2C1_SDA, I3C1_SDA, FMC_A6,

- - M3 PJ10 I/O TT_f -
DCMI_HSYNC/PSSI_DE/DCMIPP_HSYNC, EVENTOUT
page 70/234
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
SPI5_RDY, SAI2_SCK_A, SAI4_D4, UART9_CTS,

- - M5 PJ11 I/O TT (1) TIM8_CH3N, FMC_A13, DCMI_D12/PSSI_D12/DCMIPP_D12, -
EVENTOUT
SAI2_SD_A, UART9_RX, FDCAN1_TX, TIM8_BKIN2,

- - L2 PJ12 I/O TT_f (1) I2C2_SCL, I3C2_SCL, FMC_A15, DCMI_D13/PSSI_D13/ -
(1) SAI2_MCLK_A, UART9_TX, FDCAN1_RX, TIM10_CH1,

- - M4 PJ13 I/O TT_f -
I2C2_SDA, I3C2_SDA, PSSI_D15/DCMIPP_D15, EVENTOUT
- - L3 PJ14 I/O TT (1) SPI4_SCK, FDCAN3_TX, FMC_A1, LCD_R0, EVENTOUT -
(1) TRACED7, HDP7, SPI4_MISO, FDCAN2_TX, TIM11_CH1,

- - K2 PJ15 I/O TT -
FMC_A4, LCD_R1, EVENTOUT
SPI2_MISO/I2S2_SDI, SPDIFRX1_IN2, MDF1_CCK0,
- - F12 PK0 I/O TT (1) TIM20_ETR, TIM1_ETR, SDMMC3_D123DIR, FMC_AD11/ -
FMC_D11, DCMI_D11/PSSI_D11/DCMIPP_D11, EVENTOUT
SPI2_MOSI/I2S2_SDO, MDF1_SDI2, TIM20_BKIN,
- - E12 PK1 I/O TT (1) TIM1_BKIN, SDVSEL2, SDMMC3_D0DIR, FMC_AD13/ -
FMC_D13, DCMI_D10/PSSI_D10/DCMIPP_D10, EVENTOUT
SPI7_NSS, SAI4_SCK_A, USART1_RTS/USART1_DE,
- - F13 PK2 I/O TT_f (1) TIM20_CH2, TIM1_CH2N, I2C6_SDA, FMC_NCE3, DCMI_D6/ -

SPI7_RDY, MDF1_CKI1, TIM20_CH3N, TIM1_CH3, FMC_AD8/
- - F15 PK3 I/O TT (1) FMC_D8, DCMI_D3/PSSI_D3/DCMIPP_D3, FMC_NCE4, -
EVENTOUT
SPI7_MISO, UART4_TX, SAI4_FS_A, TIM20_CH1,
- - F11 PK4 I/O TT (1) TIM1_CH1N, SDMMC3_CKIN, FMC_AD9/FMC_D9, DCMI_D8/ -
SPI2_RDY, MDF1_CKI0, USART1_TX, TIM20_CH4N,
- - F14 PK5 I/O TT_f (1) TIM1_CH4, I2C5_SCL, FMC_AD5/FMC_D5, DCMI_D1/ -
SPI7_SCK, SAI4_MCLK_A, USART1_CTS/USART1_NSS,
(1) TIM20_CH2N, TIM1_CH2, I2C6_SCL, FMC_AD14/FMC_D14,
- - G12 PK6 I/O TT_f -
FMC_AD7/FMC_D7, DCMI_D5/PSSI_D5/DCMIPP_D5,
EVENTOUT
MDF1_SDI0, USART1_RX, TIM20_CH4, TIM1_CH4N,
page 71/234
- - G14 PK7 I/O TT_f (1) I2C5_SDA, FMC_NCE4, FMC_AD6/FMC_D6, DCMI_D2/ -

DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
P2 AB4 T6 PWR_CPU_ON O TT (1) - -
P1 AF1 U4 PWR_LP O TT (1) - -
U3 AD3 T5 PWR_ON O TT (1) - -

LPTIM3_IN1, SPI8_MOSI, TIM8_CH1, LPUART1_TX,
(15) CPU3_SWDIO,
L5 T4 N5 PZ0 I/O TT_f LPTIM5_OUT, I2C8_SDA, LPTIM3_CH2, I3C4_SDA,
TAMP_OUT3
EVENTOUT
LPTIM3_CH1, SPI8_MISO, TIM8_CH2, LPUART1_RX, CPU3_SWCLK,
M4 U7 N6 PZ1 I/O TT_f (15)

LPTIM5_ETR, I2C8_SCL, I2C8_SMBA, I3C4_SCL, EVENTOUT TAMP_OUT5
LPTIM3_CH1, SPI8_SCK, ADF1_CCK0, LPUART1_RTS/
(15) TAMP_IN3/
M3 W5 P4 PZ2 I/O TT_f LPUART1_DE, LPTIM4_ETR, I2C8_SCL, I3C4_SCL,
TAMP_OUT7
EVENTOUT
DBTRGI, DBTRGO, LPTIM3_ETR, SPI8_NSS, MDF1_SDI5,
M5 Y6 N4 PZ3 I/O TT_f (15) ADF1_SDI0, LPUART1_CTS, LPTIM4_IN1, I2C8_SDA, TAMP_OUT4
LPTIM4_CH2, I3C4_SDA, EVENTOUT
DBTRGI, DBTRGO, MCO2, SPI8_RDY, MDF1_CCK1,
(15) TAMP_IN5/
L4 V3 R5 PZ4 I/O TT_f ADF1_CCK1, LPUART1_RX, LPTIM4_CH1, I2C8_SCL,
TAMP_OUT6
I3C4_SCL, EVENTOUT
MCO1, LPTIM3_ETR, SPI8_SCK, ADF1_CCK0,

N3 R5 P5 PZ5 I/O TT (15) LPUART1_RTS/LPUART1_DE, LPTIM5_IN1, LPTIM4_CH2, TAMP_OUT8
EVENTOUT
(15) DBTRGI, DBTRGO, SPI8_NSS, TIM8_CH3, ADF1_SDI0,

K3 V4 R6 PZ6 I/O TT TAMP_IN8
LPUART1_CTS, LPTIM5_OUT, LPTIM4_CH2, EVENTOUT
(1) SPI8_MOSI, MDF1_CCK1, ADF1_CCK1, LPUART1_TX,

L1 V2 P2 PZ7 I/O TT -
LPTIM5_IN1, LPTIM3_CH2, EVENTOUT
LPTIM3_IN1, SPI8_MISO, MDF1_SDI5, ADF1_SDI0,
L3 V1 P3 PZ8 I/O TT (1) LPUART1_RX, LPTIM4_CH1, I2C8_SMBA, LPTIM5_ETR, -
EVENTOUT
(1) MCO2, SPI8_RDY, MDF1_CKI5, LPUART1_TX, LPTIM4_ETR,

L2 U3 N3 PZ9 I/O TT_f -
I2C8_SDA, LPTIM3_CH2, I3C4_SDA, EVENTOUT
V11 AG21 AB16 USBH_HS_DM A A - - -
V12 AG22 Y17 USB3DR_DM A A - - -
W11 AF21 AA16 USBH_HS_DP A A - - -
page 72/234
W12 AF22 W17 USB3DR_DP A A - - -

DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
USBH_HS_TXRTU
T15 AE20 V16 A A - - -
NE
USB3DR_TXRTUN
R15 AF23 V17 A A - - -
E

T12 AD20 U16 DNU A A - - -
W15 AF27 Y20 COMBOPHY_REXT A A - - -
V16 AF25 AB20 COMBOPHY_RX1N A A - - -
U16 AG25 AA20 COMBOPHY_RX1P A A - - -

V15 AD24 AB19 COMBOPHY_TX1N A A - - -
U15 AE24 AA19 COMBOPHY_TX1P A A - - -
U1 AF6 W5 VREF- A A - - -
U2 AG6 Y5 VREF+ A A - - -
R6 T6 P7 VBAT S - - - -
H8 1L1 M9 VDD S - - - -
K8 1L3 N8 VDD S - - - -

L6 1L5 P9 VDD S - - - -
- 1M2 P11 VDD S - - - -
- 1M4 R8 VDD S - - - -
- - R10 VDD S - - - -
N6 AB6 V7 VDDA18ADC S - - - -
D3 G7 F6 VDDA18CSI S - - - -
D16 F20 J16 VDDA18DDR S - - - -
C5 G9 C7 VDDA18DSI S - - - -
J4 G5 C4 VDDA18LVDS S - (2) - -
E15 G19 G17 VDDA18PLL1 S - - - -

H6 1E1 L8 VDDA18PLL3 S - - - -
page 73/234
G6 H6 K8 VDDA18PLL2 S - - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
VDDA18COMBOPH
R13 AE23 W18 S - - - -
Y
T13 AD22 U17 VDDA18USB S - - - -
G10 1C1 H7 VDDCORE S - - - -

H11 1C3 H9 VDDCORE S - - - -
J10 1C5 J8 VDDCORE S - - - -
K11 1D2 J10 VDDCORE S - - - -

L10 1D4 K9 VDDCORE S - - - -
N8 1E3 K11 VDDCORE S - - - -
N10 1E5 L10 VDDCORE S - - - -
- 1F2 - VDDCORE S - - - -
- 1F4 - VDDCORE S - - - -
E13 F18 H11 VDDCPU S - - - -
G13 G15 H13 VDDCPU S - - - -
J13 G17 H15 VDDCPU S - - - -

L13 1C7 J12 VDDCPU S - - - -
M13 1C9 J14 VDDCPU S - - - -
- 1D6 K13 VDDCPU S - - - -
- 1D8 L12 VDDCPU S - - - -
- 1D10 - VDDCPU S - - - -
F16 1C11 K15 VDDQDDR S - - - -
J16 1D12 L14 VDDQDDR S - - - -
L16 1E11 L16 VDDQDDR S - - - -
M16 M22 M15 VDDQDDR S - - - -
P16 1F12 N14 VDDQDDR S - - - -
T16 N21 P15 VDDQDDR S - - - -
page 74/234
- R21 R14 VDDQDDR S - - - -

- 1L11 R16 VDDQDDR S - - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
- 1M12 - VDDQDDR S - - - -
F8 D18 F10 VDDIO2 S - - - -
- E17 - VDDIO2 S - - - -

M11 1G7 M11 VDDGPU S - (2) - -
N14 1G9 M13 VDDGPU S - (2) - -
P11 1H6 N10 VDDGPU S - (2) - -

P13 1H8 N12 VDDGPU S - (2) - -
R10 1H10 P13 VDDGPU S - (2) - -
- 1L7 R12 VDDGPU S - (2) - -
- 1L9 - VDDGPU S - (2) - -
- 1M6 - VDDGPU S - (2) - -
- 1M8 - VDDGPU S - (2) - -
- 1M10 - VDDGPU S - (2) - -
E10 D10 F8 VDDIO3 S - - - -

F10 E11 F9 VDDIO3 S - - - -
D6 E9 G8 VDDIO4 S - - - -
E6 G11 G9 VDDIO4 S - - - -
D10 D14 G10 VDDIO1 S - - - -
- E13 - VDDIO1 S - - - -
U11 AE22 T16 VDD33UCPD S - - - -
B1 E5 D5 VDDCSI S - - - -
C6 F8 F7 VDDDSI S - - - -
J1 F4 G7 VDDLVDS S - (2) - -
U12 AC21 V18 VDDPCIECLK S - - - -

T14 AB20 V19 VDDCOMBOPHY S - - - -
page 75/234
VDDCOMBOPHYT
W16 AB22 Y19 S - - - -
X
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
N5 AB3 R7 VDDA18AON S - - - -
R14 AE21 Y16 VDD33USB S - - - -
A1 A1 AB1 VSS S - - - -

A19 A2 AB22 VSS S - - - -
C3 A27 A1 VSS S - - - -
C7 AC11 A22 VSS S - - - -
D13 AG1 E5 VSS S - - - -

E8 AG27 G6 VSS S - - - -
E16 C6 H8 VSS S - - - -
F6 C10 H10 VSS S - - - -
F11 E7 H12 VSS S - - - -
F13 F3 H14 VSS S - - - -
G8 F12 H16 VSS S - - - -
G11 F14 J9 VSS S - - - -

H10 F16 J11 VSS S - - - -
H13 1A1 J13 VSS S - - - -
H16 1A3 J15 VSS S - - - -
J6 1A5 K10 VSS S - - - -
J8 1A7 K12 VSS S - - - -
J11 1A9 K14 VSS S - - - -
J14 1A11 L9 VSS S - - - -
K4 J7 L11 VSS S - - - -
K5 1B2 L13 VSS S - - - -
K10 1B4 L15 VSS S - - - -
K13 1B6 M10 VSS S - - - -
page 76/234
K16 1B8 M12 VSS S - - - -

L8 1B10 M14 VSS S - - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
L11 1B12 M20 VSS S - - - -

M10 K3 N7 VSS S - - - -
N11 1E7 N9 VSS S - - - -

N13 1E9 N11 VSS S - - - -
N16 1F6 N13 VSS S - - - -
P8 1F8 N15 VSS S - - - -
P10 1F10 P8 VSS S - - - -

P14 1G1 P10 VSS S - - - -
R11 1G3 P12 VSS S - - - -
R16 1G5 P14 VSS S - - - -
R18 1G11 R9 VSS S - - - -
W1 1H2 R11 VSS S - - - -
W19 1H4 R13 VSS S - - - -
- 1H12 R15 VSS S - - - -

- 1J1 T4 VSS S - - - -
- 1J3 U6 VSS S - - - -
- 1J5 W8 VSS S - - - -
- 1J7 W16 VSS S - - - -
- 1J9 W19 VSS S - - - -
- 1J11 - VSS S - - - -
- 1K2 - VSS S - - - -
- 1K4 - VSS S - - - -
- 1K6 - VSS S - - - -
- 1K8 - VSS S - - - -
- 1K10 - VSS S - - - -
page 77/234
- 1K12 - VSS S - - - -
- V6 - VSS S - - - -
DS14284 - Rev 2
Pin number
I/O
VFBGA361
VFBGA424
TFBGA436
Pin name (function
after reset)
e
- Y4 - VSS S - - - -
P6 AC5 U7 VSSA S - - - -
M6 AC3 M7 VSSAON S - - - -

M8 R7 M8 V08CAP A - - - -
1. Power supply is VDD.

2. ball is DNU in some part numbers.
3. Power supply is VDD - used in open drain with external pull-up.

4. Power supply is VDDIO4.
5. Power supply is VDD or VSW - input only in VSW.
6. Power supply is VSW.
7. Power supply is VSW - OSC32_IN pin is also used as digital input in LSE bypass mode and tied to GPIO PC14 input (for test purpose only).
8. Power supply is VSW - OSC32_OUT pin is also tied to GPIO PC15 input (for test purpose only).
9. Power supply is VDDA18AON, must be always connected at board level to VDDA18AON.

13. Power supply is VDDA18AON - OSC_IN pin is also used as digital input in HSE bypass mode and tied to GPIO PH0 input (for test purpose only).
14. Power supply is VDDA18AON - OSC_OUT pin is also tied to GPIO PH1 input, used by Boot ROM to autodetect HSE bypass mode.
15. Power supply is VDD or VSW.
page 78/234
4.3 Alternate functions
DS14284 - Rev 2
Table 12. Alternate functions AF0 to AF7
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
I3C3 / LPTIM1/2 /
HDP / I2S /
DBG / HDP / SAI1/2/3/4 / FDCAN3 /
LPTIM2/3 / FDCAN2 / MDF1 / ADF1 / DSI /
LPTIM1/2 / RTC / SPDIFRX1 / I2C4/5 /
Port SPDIFRX1 / SPI1 / PCIE / SAI1/2/3/4 / I3C3 / MDF1 /
SAI1 / SPI1 / SPI1 / I2S1 / LPUART1 / FDCAN1/2/3 / LPTIM4/5 /
DBG I2S1 / SPI2 / SPDIFRX1 / SPI2 / SAI2/4 /
I2S1 / SPI3 / SPI3 / I2S3 / TIM14/17 / TIM2/3/4/12/13/15/16/17/20
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /

I2S3 / SPI4/5/6/7 / UART4 / USART6 USART1/6
SYS UART4/8 / USART1/2/3/6
SYS
USART6
PA0 - LPTIM1_CH2 SPI5_RDY UART8_CTS SAI2_MCLK_B UART5_TX USART3_TX TIM3_ETR

USART1_RTS/
PA1 - - SPI6_MISO - SAI3_SD_A USART6_CK TIM4_CH2
USART1_DE
PA2 - LPTIM2_IN1 SPI7_MISO - - MDF1_SDI7 USART1_RX -
PA3 - LPTIM2_ETR SPI7_MOSI - - MDF1_CKI7 USART1_TX -
PA4 - - - - - - USART2_TX FDCAN2_TX
USART2_RTS/
PA5 - - - SPI4_MOSI SAI2_MCLK_B SAI2_SD_B FDCAN2_RX
USART2_DE
PA6 - - - SPI4_SCK SAI2_FS_B MDF1_SDI6 USART2_CK TIM13_CH1
USART1_CTS/
PA7 - - AUDIOCLK SPI6_RDY PCIE_CLKREQN MDF1_CCK0 TIM4_ETR
USART1_NSS

Port A
PA8 - LPTIM2_CH2 SPI7_NSS - SAI1_FS_B - USART1_CK -

USART2_CTS/
PA9 - - - SPI4_NSS SAI2_SCK_B - LPTIM5_ETR
USART2_NSS
PA10 - - - SPI4_MISO SAI2_SD_B - USART2_RX LPTIM5_IN1
PA11 - SPI8_SCK LPTIM2_CH1 - SAI4_SD_B MDF1_SDI4 - -
PA12 - - SPI6_MOSI - SAI3_FS_A - - TIM4_CH1
USART2_CTS/
PA13 - SPI8_RDY I2S3_MCK LPTIM2_ETR - MDF1_CKI3 -
USART2_NSS
PA14 - SPI8_NSS LPTIM2_CH2 - SAI4_FS_B MDF1_CCK1 - -
SPI3_MISO/
PA15 - - - - - USART2_RX -
I2S3_SDI
SPI2_SCK/
page 79/234
PB0 - - - - - USART1_CK TIM16_CH1

Port B
I2S2_CK
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
SPI3_NSS/
PB1 - - - - - - TIM16_CH1N
I2S3_WS

SPI2_MOSI/
PB2 - - - - MDF1_CKI3 TIM17_BKIN TIM16_BKIN
I2S2_SDO
SPI2_NSS/
PB3 - - - - MDF1_SDI3 - -
I2S2_WS
PB4 - - SPI2_RDY UART4_CTS SAI4_FS_B MDF1_SDI4 TIM14_CH1 -
UART4_RTS/
PB5 - - I2S2_MCK SAI4_SD_B MDF1_CKI4 - -
UART4_DE
SPI2_MISO/
PB6 - - UART4_RX SAI4_SCK_B - - -
I2S2_SDI
SPI3_SCK/
PB7 - - UART4_TX SAI4_MCLK_B - - -
I2S3_CK
Port B
SPI3_MOSI/
PB8 - - - PCIE_CLKREQN - USART1_TX TIM17_CH1
I2S3_SDO

USART1_RTS/
PB9 - SPI3_RDY - - - - FDCAN1_TX
USART1_DE
SPI3_MISO/
PB10 - - - - - USART1_RX TIM17_CH1N
I2S3_SDI
USART1_CTS/
PB11 - I2S3_MCK - - - - FDCAN1_RX
USART1_NSS
PB12 - - - - - UART8_CTS - TIM13_CH1
PB13 - - SPI7_SCK - SAI1_SD_B UART8_RX - -
SPI2_SCK/
PB14 - - - - MDF1_CKI7 UART9_RX -
I2S2_CK
UART8_RTS/
PB15 - LPTIM1_IN2 SPI5_SCK SAI2_SD_B UART5_RX - TIM3_CH2
UART8_DE
PC0 - LPTIM1_CH1 - SPI6_SCK SAI3_MCLK_B USART6_TX - -
page 80/234
Port C
SPI3_MOSI/
PC1 - - - - - USART2_TX -
I2S3_SDO
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
USART2_RTS/
PC2 - SPI8_MOSI LPTIM2_IN1 - SAI4_MCLK_B MDF1_SDI3 -
USART2_DE

SPI3_NSS/ USART6_RTS/
PC3 - LPTIM1_IN2 SPI6_RDY - - FDCAN2_TX
I2S3_WS USART6_DE
PC4 - - - SPI6_MISO SAI3_FS_B - - -
PC5 - - SPDIFRX1_IN1 - - MDF1_SDI1 - -

PC6 - RTC_REFIN SPDIFRX1_IN0 - - MDF1_CKI1 - -
PC7 - - - SPI6_MOSI SAI3_SD_B - - -
USART6_CTS/
Port C
PC8 - LPTIM1_ETR - SPI6_NSS SAI3_SCK_B - -

USART6_NSS
SPI3_MISO/
PC9 - MCO1 - SAI2_SCK_A - - TIM13_CH1
I2S3_SDI
SPI3_MOSI/
PC10 - - - - - - LPTIM4_ETR
I2S3_SDO

UART5_RTS/ USART3_RTS/
PC11 - LPTIM1_CH1 SPI5_NSS - SAI2_MCLK_A TIM3_CH1
UART5_DE USART3_DE
PC12 - LPTIM1_CH2 - I3C3_SCL - MDF1_CKI2 - -
PC13 - - - - - - - -
PD0 TRACECLK HDP0 SPI7_RDY SAI1_D2 - SAI4_FS_A UART7_RX TIM15_CH2
SPI1_MISO/ UART7_RTS/
PD1 - HDP1 SAI1_CK2 - SAI4_SD_A TIM15_CH1
I2S1_SDI UART7_DE
SPI1_NSS/
PD2 - HDP2 SAI1_CK1 - SAI4_SCK_A UART7_CTS TIM15_BKIN
I2S1_WS
SPI2_SCK/
PD3 - SAI1_MCLK_A SAI1_D1 - SAI4_MCLK_A UART7_TX TIM15_CH1N
Port D
I2S2_CK
PD4 TRACED0 SPI4_MISO HDP3 SAI1_D3 SAI1_SD_B - - -
PD5 TRACED1 SPI4_NSS HDP4 SAI1_D4 SAI1_FS_B - - -
page 81/234
PD6 TRACED2 SPI4_MOSI HDP5 - SAI1_SCK_B MDF1_SDI2 - -

PD7 TRACED3 SPI4_SCK SPI1_RDY - SAI1_MCLK_B MDF1_CKI2 - -
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
PD8 TRACED4 SPI4_RDY I2S1_MCK SAI1_FS_A UART4_CTS MDF1_SDI1 - -

SPI1_MOSI/ UART4_RTS/
PD9 TRACED5 HDP6 SAI1_SD_A MDF1_CKI1 - -
I2S1_SDO UART4_DE
PD10 TRACED6 HDP7 - SAI1_SCK_A UART4_RX MDF1_SDI0 I2C4_SDA -
SPI1_SCK/
PD11 TRACED7 - SAI1_MCLK_A UART4_TX MDF1_CKI0 I2C4_SCL -
I2S1_CK
Port D
PD12 - SPI7_MISO SPDIFRX1_IN2 - - -
I2S2_SDI UART8_DE
SPI2_NSS/
PD13 - - - - MDF1_SDI7 UART9_TX -
I2S2_WS
PD14 - - I2S1_MCK - - - - FDCAN1_RX
PD15 - SPI1_RDY - - - DSI_TE I2C5_SDA FDCAN1_TX
SPI1_SCK/
PE0 TRACED2 LPTIM2_CH1 SPI3_RDY - - USART3_CK -
I2S1_CK

PE1 TRACED3 LPTIM2_CH2 I2S1_MCK I2S3_MCK - - USART3_RX -
SPI1_MISO/ SPI3_MOSI/
PE2 - LPTIM2_ETR SAI1_SCK_B - - -
I2S1_SDI I2S3_SDO
SPI3_SCK/
PE3 TRACECLK - SPI1_RDY SAI1_MCLK_B - USART3_TX -
I2S3_CK
SPI1_MOSI/ SPI3_MISO/ USART3_CTS/
PE4 TRACED0 LPTIM2_IN1 SAI1_SD_B - FDCAN1_TX
I2S1_SDO I2S3_SDI USART3_NSS
Port E
SPI1_NSS/ SPI3_NSS/ USART3_RTS/

PE5 TRACED1 LPTIM2_IN2 SAI1_FS_B - FDCAN1_RX
I2S1_WS I2S3_WS USART3_DE
PE6 - SPI4_RDY - - SPDIFRX1_IN2 - USART1_TX -
PE7 - - - SAI4_D4 SPDIFRX1_IN3 - USART1_RX -
PE8 - SPI4_MOSI - SAI4_CK1 SAI4_MCLK_A MDF1_CKI0 - -
PE9 - SPI4_MISO - SAI4_D2 SAI4_FS_A - USART1_CK -
page 82/234
USART1_CTS/
PE10 - SPI4_SCK - SAI4_D1 SAI4_SD_A - -
USART1_NSS
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
PE11 - - SPI7_SCK SAI4_D3 SAI1_FS_A - - TIM15_CH2

USART1_RTS/
PE12 - SPI4_NSS - SAI4_CK2 SAI4_SCK_A MDF1_SDI0 -
USART1_DE
Port E
PE13 - - SPI7_MISO - SAI1_SD_A - - TIM15_CH1

PE14 - - SPI7_NSS - SAI1_MCLK_A MDF1_CKI6 - TIM15_BKIN

PE15 - - SPI7_MOSI - SAI1_SCK_A MDF1_SDI6 - TIM15_CH1N
SPI3_SCK/
PF0 - - - - - - FDCAN2_RX
I2S3_CK
PF1 - SPI8_MISO LPTIM2_IN2 - SAI4_SCK_B MDF1_CKI4 USART2_CK -
PF2 - - SPI3_RDY - - - I2C4_SMBA -
PF3 - - - UART8_RX SAI2_SCK_B MDF1_CCK0 - TIM3_CH4
PF4 - RTC_OUT2 SPI6_NSS - SAI3_SCK_A - USART6_RX TIM4_CH4
PF5 - - SPI6_SCK - SAI3_MCLK_A - USART6_TX TIM4_CH3

PF6 - RTC_OUT2 - SAI3_MCLK_B - - USART6_CK TIM12_CH1
PF7 - - SPDIFRX1_IN1 SPI6_SCK SAI3_SD_A - - TIM2_ETR
PF8 - RTC_REFIN - SAI3_SCK_B - - USART3_RX TIM12_CH2
Port F
UART8_RTS/
PF9 - - - SAI3_SD_B SAI2_SD_A MDF1_SDI5 TIM2_CH2
UART8_DE
PF10 - MCO2 SPI3_RDY - SAI2_MCLK_A MDF1_CKI6 UART8_TX TIM2_CH3
PF11 - MCO1 SPDIFRX1_IN0 SPI6_RDY SAI2_SCK_A MDF1_SDI6 UART8_RX TIM2_CH4
PF12 TRACECLK - SPI5_MISO - - -
I2S1_SDI UART9_DE
SPI2_NSS/ USART3_CTS/
PF13 TRACED0 HDP0 AUDIOCLK USART6_TX MDF1_CKI7 FDCAN3_TX
I2S2_WS USART3_NSS
USART3_RTS/
PF14 TRACED1 HDP1 - USART6_RX - MDF1_SDI7 FDCAN3_RX
USART3_DE
page 83/234
USART6_CTS/ SPI2_SCK/
PF15 TRACED2 HDP2 SPI2_RDY - USART3_CK TIM2_CH2
USART6_NSS I2S2_CK
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
PG0 - LPTIM1_IN1 - I3C3_SDA - MDF1_SDI2 - -

USART3_CTS/
PG1 - LPTIM1_IN1 I2S3_MCK I3C3_SCL SAI2_SD_A UART5_CTS -
USART3_NSS
PG2 - RTC_REFIN I2S3_MCK I3C3_SDA SAI2_FS_A - USART3_CK -
PG3 - LPTIM1_ETR SPI5_MOSI UART8_TX SAI2_FS_B - - TIM3_CH3

PG4 - - SPI5_MISO SAI3_FS_B - - - LPTIM4_IN1
USART6_RTS/
PG5 TRACED3 HDP3 - - - - TIM2_CH3
USART6_DE
SPI1_SCK/
PG6 TRACED4 HDP4 SPI5_SCK - - - TIM2_CH4
I2S1_CK
SPI1_NSS/
PG7 TRACED5 HDP5 SPI5_NSS - - UART9_CTS -
I2S1_WS
UART5_RTS/
Port G
PG8 TRACED6 HDP6 SPI5_RDY SPI1_RDY USART6_CK UART9_TX -

UART5_DE

PG9 TRACED7 - - - - UART5_TX - -
PG1
TRACED8 HDP0 - - - UART5_RX - -
0
PG11 TRACED9 HDP1 SPI7_MOSI - - - - FDCAN1_TX
PG1
TRACED10 HDP2 SPI7_MISO - - - - FDCAN1_RX
2
PG1
TRACED11 HDP3 SPI7_SCK - - MDF1_CKI6 - -
3
PG1
TRACED12 HDP4 SPI7_RDY - - MDF1_CKI5 USART1_TX -
4
PG1
TRACED13 HDP5 - LPTIM1_CH2 - MDF1_SDI5 USART1_RX -
5
PH2 - LPTIM2_CH1 SPI7_RDY SPDIFRX1_IN3 SAI1_SCK_B I3C3_SDA - TIM16_CH1
SPI1_NSS/
page 84/234
PH3 - - - - - UART7_RX TIM17_CH1N

Port H
I2S1_WS
PH4 - - - - - - UART7_TX TIM17_BKIN
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
PH5 - - - - SAI2_FS_A - UART8_CTS TIM2_CH1

PH6 - LPTIM2_IN2 - - SAI1_MCLK_B I3C3_SCL - TIM16_CH1N
SPI1_MOSI/ UART7_RTS/
PH7 - - - UART4_TX - TIM17_CH1
I2S1_SDO UART7_DE
SPI1_MISO/
PH8 - - SPDIFRX1_IN3 UART4_RX - UART7_CTS -
I2S1_SDI
PH9 - - - SPI6_NSS SAI3_MCLK_A - USART6_RX TIM15_CH1N
Port H
SPI1_SCK/
PH10 - - SPI6_MOSI SAI3_SCK_A - - TIM15_CH1
I2S1_CK
PH11 - - - SPI6_MISO SAI3_FS_A - - TIM15_CH2
SPI3_NSS/
PH12 - - SPI6_MISO - - - -
I2S3_WS
SPI3_SCK/
PH13 - - SPI6_MOSI - - - TIM15_BKIN
I2S3_CK

PI0 TRACED14 HDP6 - LPTIM1_IN1 SAI4_MCLK_B - USART1_CK -
PI1 TRACED15 HDP7 SPI7_NSS - - MDF1_SDI6 - -
USART1_RTS/
PI2 - - - LPTIM1_ETR SAI4_SCK_B - -
USART1_DE
USART1_CTS/
PI3 - - - LPTIM1_IN2 SAI4_SD_B - -
USART1_NSS
PI4 - - - LPTIM1_CH1 SAI4_FS_B - - -
Port I
SPI1_MOSI/
PI5 - - SPI5_MOSI - UART5_CTS UART9_RX -
I2S1_SDO
PI6 - MCO1 - - - - USART3_TX TIM2_ETR
PI7 - - - - - - USART3_RX TIM2_CH1
PI8 - - - - - - - -
SPI2_MOSI/
PI9 - SPI7_MOSI - FDCAN2_TX - UART9_CTS -
page 85/234
I2S2_SDO
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
SPI1_SCK/
PI10 - SAI1_SCK_A SPDIFRX1_IN0 FDCAN2_RX MDF1_CCK0 - -
I2S1_CK

UART9_RTS/
PI11 - - I2S2_MCK - - UART8_TX -
UART9_DE
PI12 - - SPI4_NSS - - - - FDCAN3_RX
Port I
PI13 - - SPI4_MOSI - FDCAN2_RX - - -

SPI2_NSS/
PI14 - - - - MDF1_SDI1 - TIM20_CH3
I2S2_WS
PI15 - - I2S2_MCK UART4_RX - MDF1_CKI2 - TIM20_BKIN2
USART6_CTS/
PJ0 - - SPI5_MOSI - PCIE_CLKREQN SAI4_D2 -
USART6_NSS
PJ1 - - - - - - USART6_RX -
UART9_RTS/
PJ2 - - - - SAI2_SD_B - -
UART9_DE

USART6_RTS/
PJ3 - - SPI5_NSS SAI2_FS_A - SAI4_D1 -
USART6_DE
PJ4 - - - SAI2_FS_B - MDF1_CCK1 USART6_CK -
PJ5 - - SPI5_MISO SAI2_SCK_B - SAI4_CK1 USART6_TX -
PJ6 - - SPI7_MOSI - SAI4_SD_A - USART2_CK TIM20_CH1N
Port J
PJ7 - - SPI5_MISO - SAI2_MCLK_B SAI4_D3 USART6_CK -

PJ8 - - SPI5_SCK - - SAI4_CK2 USART6_RX -
PJ9 - - SPI4_RDY - - - - TIM12_CH1
PJ10 - - - - - - - TIM12_CH2
PJ11 - - SPI5_RDY SAI2_SCK_A - SAI4_D4 UART9_CTS -
PJ12 - - - SAI2_SD_A - - UART9_RX FDCAN1_TX
PJ13 - - - SAI2_MCLK_A - - UART9_TX FDCAN1_RX
page 86/234
PJ14 - - SPI4_SCK - - - - FDCAN3_TX

PJ15 TRACED7 HDP7 SPI4_MISO - FDCAN2_TX - - -
DS14284 - Rev 2
I3C3 / LPTIM1/2 /
HDP / I2S /
I2S2 / SPI3 / I2S2 / TIM8 / UART5/8 /
I2S3 / SPI4/7/8 / SPI4/6/8 / UART7/8/9 /
SYS
USART6
SPI2_MISO/
PK0 - - SPDIFRX1_IN2 - MDF1_CCK0 - TIM20_ETR
I2S2_SDI

SPI2_MOSI/
PK1 - - - - MDF1_SDI2 - TIM20_BKIN
I2S2_SDO
USART1_RTS/
PK2 - - SPI7_NSS - SAI4_SCK_A - TIM20_CH2
USART1_DE
Port K
PK3 - - SPI7_RDY - - MDF1_CKI1 - TIM20_CH3N

PK4 - - SPI7_MISO UART4_TX SAI4_FS_A - - TIM20_CH1
PK5 - - SPI2_RDY - - MDF1_CKI0 USART1_TX TIM20_CH4N
USART1_CTS/
PK6 - - SPI7_SCK - SAI4_MCLK_A - TIM20_CH2N
USART1_NSS
PK7 - - - - - MDF1_SDI0 USART1_RX TIM20_CH4
PZ0 - - LPTIM3_IN1 SPI8_MOSI TIM8_CH1 - LPUART1_TX LPTIM5_OUT
PZ1 - - LPTIM3_CH1 SPI8_MISO TIM8_CH2 - LPUART1_RX LPTIM5_ETR

LPUART1_RTS/
PZ2 - - LPTIM3_CH1 SPI8_SCK - ADF1_CCK0 LPTIM4_ETR
LPUART1_DE
PZ3 DBTRGI DBTRGO LPTIM3_ETR SPI8_NSS MDF1_SDI5 ADF1_SDI0 LPUART1_CTS LPTIM4_IN1
PZ4 DBTRGI DBTRGO MCO2 SPI8_RDY MDF1_CCK1 ADF1_CCK1 LPUART1_RX LPTIM4_CH1
Port Z
LPUART1_RTS/
PZ5 - MCO1 LPTIM3_ETR SPI8_SCK - ADF1_CCK0 LPTIM5_IN1
LPUART1_DE
PZ6 DBTRGI DBTRGO - SPI8_NSS TIM8_CH3 ADF1_SDI0 LPUART1_CTS LPTIM5_OUT
PZ7 - - - SPI8_MOSI MDF1_CCK1 ADF1_CCK1 LPUART1_TX LPTIM5_IN1
PZ8 - - LPTIM3_IN1 SPI8_MISO MDF1_SDI5 ADF1_SDI0 LPUART1_RX LPTIM4_CH1
PZ9 - MCO2 - SPI8_RDY MDF1_CKI5 - LPUART1_TX LPTIM4_ETR
page 87/234
Table 13. Alternate functions AF8 to AF15
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
ETH1/2 / FDCAN3 / ETH1/2 / FMC / I2C3/5 /
Port I3C1 / ETH1/2 / FMC / I2C1/3/5/7 / I3C1/2 / LCD / DCMI / PSSI / DCMIPP / DSI /
I2C1/2/3/4/5/6/7/8 / I3C4 / LCD / DSI / ETH1/2 / FMC / I2C4 / LCD / DCMI / PSSI / DCMIPP /
TIM1/2/3/4/5/8/10/1 LPTIM3/4 / OCTOSPIM_P1/2 / SDMMC1/3 / ETH1/2/3 / I3C2 / LCD / SYS
LPTIM5 / OCTOSPIM_P1/2 / OCTOSPIM_P2 / SDMMC1/2/3 / USBH_HS ETH3 / FMC / LCD / SDMMC3
1/12/16/20 / TIM14 OCTOSPIM_P1 / SDMMC2
SDMMC1/2 / SDMMC1 / USB3DR
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
DCMI_D9/PSSI_D9/ EVEN
PA0 TIM5_CH2 - ETH2_MII_RXD2 - FMC_NL -
DCMIPP_D9 TOUT

PA1 I2C4_SDA I2C6_SDA - LCD_R3 - ETH3_PHY_INTN
DCMIPP_D5 TOUT
DCMI_D3/PSSI_D3/ ETH3_RGMII_RX_CTL/ EVEN

PA2 I3C1_SDA - I2C1_SDA LCD_B0 -
DCMIPP_D3 ETH3_RMII_CRS_DV TOUT
DCMI_D2/PSSI_D2/ ETH3_RGMII_TX_CTL/ EVEN

PA3 I3C1_SCL I2C7_SMBA I2C1_SCL LCD_B1 -
DCMIPP_D2 ETH3_RMII_TX_EN TOUT
EVEN
PA4 TIM2_CH1 - LCD_R1 - - ETH1_PTP_AUX_TS ETH3_PPS_OUT
TOUT
DCMI_D13/PSSI_D13/ ETH3_RGMII_RX_CLK/ EVEN

PA5 TIM2_CH4 - LCD_G0 - FMC_A0
DCMIPP_D13 ETH3_RMII_REF_CLK TOUT
DCMI_D12/PSSI_D12/ ETH3_RGMII_TXD0/ EVEN

PA6 TIM2_ETR - LCD_G4 - FMC_NE1
DCMIPP_D12 ETH3_RMII_TXD0 TOUT
DCMI_D6/PSSI_D6/ ETH3_RGMII_TXD1/ EVEN

PA7 I2C2_SMBA I2C6_SMBA LCD_B5 I2C3_SMBA I2C4_SMBA
DCMIPP_D6 ETH3_RMII_TXD1 TOUT
Port A
PA8 USART2_RX I2C5_SCL - - LCD_B2 -
DCMIPP_D4 TOUT
ETH3_RGMII_RXD0/ EVEN
PA9 TIM2_CH3 - ETH1_MDC - LCD_G7 PSSI_D14/DCMIPP_D14
ETH3_RMII_RXD0 TOUT
PA1 ETH3_RGMII_RXD1/ EVEN

TIM2_CH2 - ETH1_MDIO - LCD_R6 PSSI_D15/DCMIPP_D15
0 ETH3_RMII_RXD1 TOUT
ETH1_MII_RX_DV/ETH1_RGMII_RX_CTL/ EVEN
PA11 - - - - - -
ETH1_RMII_CRS_DV TOUT
PA1 EVEN
I2C4_SCL I2C6_SCL ETH1_PHY_INTN - - - -
2 TOUT
PA1 ETH1_MII_TX_EN/ETH1_RGMII_TX_CTL/ EVEN

- I2C7_SMBA - - - -
3 ETH1_RMII_TX_EN TOUT
PA1 ETH1_MII_RX_CLK/ETH1_RGMII_RX_CLK/ EVEN

- - - - - -
4 ETH1_RMII_REF_CLK TOUT
PA1 ETH1_MII_TXD0/ETH1_RGMII_TXD0/ EVEN

- I2C7_SDA - - - -
5 ETH1_RMII_TXD0 TOUT
EVEN
PB0 TIM20_CH4N - OCTOSPIM_P2_IO0 - - - -
TOUT
EVEN
PB1 TIM20_CH3N - OCTOSPIM_P2_IO1 - FMC_NCE4 - -
TOUT
EVEN
PB2 TIM20_CH2N - OCTOSPIM_P2_IO2 - - - -
Port B
TOUT
EVEN
page 88/234
PB3 TIM20_CH3 - OCTOSPIM_P2_IO3 - FMC_NCE3 - -

TOUT
EVEN
PB4 TIM20_CH2 I2C2_SDA OCTOSPIM_P2_IO4 - - I3C2_SDA -
TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
EVEN
PB5 TIM20_CH1 I2C2_SCL OCTOSPIM_P2_IO5 - FMC_AD8/FMC_D8 I3C2_SCL SDMMC3_D123DIR
TOUT
EVEN
PB6 TIM20_CH1N - OCTOSPIM_P2_IO6 - FMC_AD9/FMC_D9 - SDMMC3_D0DIR
TOUT

EVEN
PB7 TIM20_ETR TIM12_CH1 OCTOSPIM_P2_IO7 - FMC_AD10/FMC_D10 - SDMMC3_CDIR
TOUT
EVEN
PB8 TIM20_CH4 - OCTOSPIM_P2_NCS1 - FMC_AD12/FMC_D12 - -
TOUT
EVEN
PB9 TIM20_BKIN TIM10_CH1 OCTOSPIM_P2_DQS OCTOSPIM_P2_NCS2 FMC_AD13/FMC_D13 - -

TOUT
PB1 EVEN
Port B
- - OCTOSPIM_P2_CLK - FMC_AD15/FMC_D15 - -
0 TOUT
PB1 EVEN
TIM20_BKIN2 TIM12_CH2 OCTOSPIM_P2_NCLK OCTOSPIM_P2_NCS2 FMC_AD14/FMC_D14 OCTOSPIM_P1_NCS2 -
1 TOUT
PB1 DCMI_D12/PSSI_D12/ EVEN

- DSI_TE SDMMC3_D2 FMC_NWAIT - -
2 DCMIPP_D12 TOUT
PB1 EVEN
- - SDMMC3_CK FMC_AD5/FMC_D5 FMC_AD0/FMC_D0 - -
3 TOUT
PB1 EVEN
- TIM4_CH2 SDMMC3_D0 FMC_AD7/FMC_D7 FMC_AD2/FMC_D2 - -
4 TOUT
PB1 DCMI_D8/PSSI_D8/ EVEN

TIM5_CH1 - ETH1_PPS_OUT - FMC_A18 LCD_R4
5 DCMIPP_D8 TOUT

PC0 - ETH2_MII_RX_CLK/ETH2_RMII_REF_CLK ETH1_MII_TX_CLK ETH1_RGMII_GTX_CLK LCD_G7 -
DCMIPP_D0 TOUT
ETH1_MII_TXD1/ETH1_RGMII_TXD1/ EVEN
PC1 - I2C7_SCL - - - -
ETH1_RMII_TXD1 TOUT
ETH1_MII_RXD1/ETH1_RGMII_RXD1/ EVEN
PC2 - - - - - -
ETH1_RMII_RXD1 TOUT
ETH2_MII_RX_DV/ETH2_RGMII_RX_CTL/ DCMI_D3/PSSI_D3/ EVEN

PC3 - - ETH1_MII_RX_ER - LCD_G6
ETH2_RMII_CRS_DV DCMIPP_D3 TOUT
ETH2_MII_TX_EN/ETH2_RGMII_TX_CTL/ EVEN
PC4 - - - ETH1_RGMII_CLK125 LCD_R0 -
ETH2_RMII_TX_EN TOUT
EVEN
PC5 TIM8_CH1N I2C4_SDA ETH2_MDIO ETH1_MII_COL FMC_A25 ETH1_PPS_OUT LCD_DE
Port C
TOUT
EVEN
PC6 TIM8_CH1 I2C4_SCL ETH2_MDC ETH1_MII_CRS FMC_A24 ETH1_PHY_INTN LCD_CLK
TOUT
ETH2_MII_TXD0/ETH2_RGMII_TXD0/ DCMI_D1/PSSI_D1/ EVEN

PC7 TIM8_CH2N - ETH1_MII_TXD2 - LCD_B4
ETH2_RMII_TXD0 DCMIPP_D1 TOUT
ETH2_MII_TXD1/ETH2_RGMII_TXD1/ DCMI_D2/PSSI_D2/ EVEN

PC8 TIM8_CH2 - ETH1_MII_TXD3 - LCD_B3
ETH2_RMII_TXD1 DCMIPP_D2 TOUT
page 89/234
USBH_HS_OVRCU DCMI_D7/PSSI_D7/ EVEN

PC9 TIM8_CH4N ETH2_MII_TXD2/ETH2_RGMII_TXD2 USB3DR_OVRCUR FMC_A22 LCD_G2
R DCMIPP_D7 TOUT
PC1 DCMI_D6/PSSI_D6/ EVEN

TIM8_CH4 USBH_HS_VBUSEN ETH2_MII_TXD3/ETH2_RGMII_TXD3 USB3DR_VBUSEN FMC_A23 LCD_G3
0 DCMIPP_D6 TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
PC1 DCMI_D10/PSSI_D10/ EVEN

TIM5_ETR - ETH2_MII_RXD3/ETH2_RGMII_RXD3 - FMC_NBL1 LCD_R2
1 DCMIPP_D10 TOUT
PC1 ETH2_MII_RXD1/ETH2_RGMII_RXD1/ DCMI_D5/PSSI_D5/ EVEN

Port C
TIM8_CH3 I2C3_SCL ETH1_MII_RXD3 - LCD_G1

2 ETH2_RMII_RXD1 DCMIPP_D5 TOUT

PC1 EVEN
- - - - - - -
3 TOUT
DCMI_PIXCLK/PSSI_PDCK/ EVEN
PD0 - SDVSEL1 OCTOSPIM_P1_CLK - - -
DCMIPP_PIXCLK TOUT
DCMI_HSYNC/PSSI_DE/ EVEN
PD1 TIM1_BKIN FDCAN3_RX OCTOSPIM_P1_NCLK OCTOSPIM_P1_NCS2 OCTOSPIM_P2_NCS2 -

DCMIPP_HSYNC TOUT
DCMI_VSYNC/PSSI_RDY/ EVEN
PD2 TIM1_ETR FDCAN3_TX OCTOSPIM_P1_DQS OCTOSPIM_P1_NCS2 - -
DCMIPP_VSYNC TOUT
EVEN
PD3 TIM1_BKIN2 SDVSEL2 OCTOSPIM_P1_NCS1 - - PSSI_D15/DCMIPP_D15 -
TOUT
EVEN
PD4 TIM1_CH4N TIM4_CH1 OCTOSPIM_P1_IO0 - - PSSI_D14/DCMIPP_D14 -
TOUT
PD5 TIM1_CH3N TIM4_CH2 OCTOSPIM_P1_IO1 - - -
DCMIPP_D13 TOUT
DCMIPP_D12 TOUT
DCMIPP_D11 TOUT
Port D

PD8 TIM1_CH4 TIM4_ETR OCTOSPIM_P1_IO4 SDMMC1_D7 SDMMC1_D123DIR -
DCMIPP_D10 TOUT
PD9 TIM1_CH3 - OCTOSPIM_P1_IO5 SDMMC1_D6 SDMMC1_D0DIR -
DCMIPP_D9 TOUT
PD1 DCMI_D8/PSSI_D8/ EVEN

TIM1_CH2 TIM14_CH1 OCTOSPIM_P1_IO6 SDMMC1_D5 SDMMC1_CDIR -
0 DCMIPP_D8 TOUT

TIM1_CH1 SDVSEL1 OCTOSPIM_P1_IO7 SDMMC1_D4 SDMMC1_CKIN -
1 DCMIPP_D7 TOUT
PD1 EVEN
- TIM4_ETR SDMMC3_CMD FMC_AD6/FMC_D6 FMC_AD1/FMC_D1 - -
2 TOUT
PD1 EVEN
- TIM4_CH4 SDMMC3_D1 FMC_AD11/FMC_D11 FMC_NWE - -
3 TOUT

TIM11_CH1 - I2C7_SDA FMC_AD4/FMC_D4 SDMMC3_D3 -
4 DCMIPP_D1 TOUT

TIM1_BKIN2 TIM5_ETR I2C7_SCL FMC_AD3/FMC_D3 SDMMC3_CKIN -
5 DCMIPP_D0 TOUT
EVEN
PE0 - - SDMMC1_D2 - - - -
TOUT
page 90/234
EVEN
PE1 - - SDMMC1_D3 - - - -
Port E
TOUT
EVEN
PE2 TIM10_CH1 - SDMMC1_CMD - - - -
TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
EVEN
PE3 TIM11_CH1 - SDMMC1_CK - - - -
TOUT
EVEN
PE4 - - SDMMC1_D0 - - - -
TOUT

EVEN
PE5 - - SDMMC1_D1 - - - -
TOUT
EVEN
PE6 TIM1_ETR - - FMC_AD1/FMC_D1 SDMMC2_D6 SDMMC2_D0DIR -
TOUT
EVEN
PE7 TIM1_CH4N - TIM14_CH1 FMC_AD2/FMC_D2 SDMMC2_D7 SDMMC2_D123DIR -

TOUT
EVEN
PE8 TIM1_CH1 - - FMC_A17/FMC_ALE SDMMC2_D2 - -
TOUT
EVEN
Port E
PE9 TIM1_CH4 - - FMC_AD0/FMC_D0 SDMMC2_D5 SDMMC2_CDIR -

TOUT
PE1 EVEN
TIM1_CH3 - FMC_NE3 FMC_NCE2 SDMMC2_D4 SDMMC2_CKIN -
0 TOUT
PE1 EVEN
TIM1_CH3N - - FMC_A16/FMC_CLE SDMMC2_D1 - -
1 TOUT
PE1 EVEN
TIM1_CH2 - FMC_NE2 FMC_NCE1 SDMMC2_D3 - -
2 TOUT
PE1 EVEN
TIM1_CH2N - - FMC_RNB SDMMC2_D0 - -
3 TOUT

PE1 EVEN
TIM1_BKIN - - FMC_NWE SDMMC2_CK - -
4 TOUT
PE1 EVEN
TIM1_CH1N - - FMC_NOE SDMMC2_CMD - -
5 TOUT
EVEN
PF0 TIM12_CH2 I2C2_SDA ETH1_MDC ETH2_MII_CRS - I3C2_SDA -
TOUT
ETH1_MII_RXD0/ETH1_RGMII_RXD0/ EVEN
PF1 - - - - - -
ETH1_RMII_RXD0 TOUT
EVEN
PF2 TIM12_CH1 I2C2_SCL ETH1_MDIO ETH2_MII_COL FMC_NE4 I3C2_SCL -
TOUT
PF3 TIM8_BKIN2 ETH1_CLK ETH2_PPS_OUT - FMC_A20 LCD_R6
DCMIPP_HSYNC TOUT
EVEN
PF4 ETH1_MDC ETH2_CLK ETH2_PPS_OUT ETH1_PPS_OUT - LCD_B7 -
Port F
TOUT
EVEN
PF5 ETH1_MDIO ETH1_CLK ETH2_PHY_INTN ETH1_PHY_INTN - LCD_B6 -
TOUT
ETH2_MII_RX_CLK/ETH2_RGMII_RX_CLK/ EVEN
PF6 - I2C3_SMBA - - LCD_B0 -
ETH2_RMII_REF_CLK TOUT
page 91/234
EVEN
PF7 - - ETH2_RGMII_GTX_CLK ETH2_MII_TX_CLK - LCD_R1 -
TOUT
EVEN
PF8 - ETH1_CLK ETH2_RGMII_CLK125 ETH2_MII_RX_ER ETH2_MII_RX_DV/ETH2_RMII_CRS_DV LCD_G0 -
TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
EVEN
PF9 - - ETH2_MII_RXD2/ETH2_RGMII_RXD2 ETH2_MDIO - - -
TOUT
PF1 EVEN
- - ETH2_MII_TXD2 - - - -
0 TOUT

EVEN
PF11 - - ETH2_MII_TXD3 - - - -
TOUT
PF1 DCMI_D0/PSSI_D0/ EVEN

Port F
TIM5_CH1 - - - - LCD_CLK
2 DCMIPP_D0 TOUT
PF1 EVEN
TIM3_CH3 - - - - LCD_R2 -
3 TOUT
PF1 EVEN
TIM3_CH4 - - - - LCD_R3 -
4 TOUT
PF1 EVEN
TIM3_ETR I2C6_SMBA - - - LCD_R4 -
5 TOUT
ETH2_MII_RXD0/ETH2_RGMII_RXD0/ DCMI_D4/PSSI_D4/ EVEN

PG0 TIM8_CH3N I2C3_SDA ETH1_MII_RXD2 - LCD_G5
ETH2_RMII_RXD0 DCMIPP_D4 TOUT
PG1 TIM5_CH4 I2C3_SCL ETH2_MII_RX_ER ETH2_MII_RXD3 FMC_NBL0 LCD_VSYNC
DCMIPP_D11 TOUT
EVEN
PG2 TIM5_CH3 I2C3_SDA ETH2_MII_TX_CLK ETH2_RGMII_CLK125 FMC_CLK LCD_HSYNC -
TOUT
PG3 TIM8_ETR ETH2_CLK ETH2_PHY_INTN - FMC_A19 LCD_R5
DCMIPP_PIXCLK TOUT

PG4 TIM8_BKIN - ETH2_PPS_OUT ETH2_MDC FMC_A21 LCD_R7
DCMIPP_VSYNC TOUT
PG5 - I2C6_SDA - - - LCD_R5
DCMIPP_PIXCLK TOUT
PG6 - I2C6_SCL - - - LCD_R6
DCMIPP_HSYNC TOUT
PG7 TIM5_ETR - - - - LCD_R7
Port G
DCMIPP_VSYNC TOUT
PG8 TIM5_CH3 - - - - LCD_G2
DCMIPP_D2 TOUT
PG9 TIM5_CH4 - - - - LCD_G3
DCMIPP_D3 TOUT
PG1 DCMI_D4/PSSI_D4/ EVEN

TIM8_CH4N - - - - LCD_G4
0 DCMIPP_D4 TOUT

TIM8_CH4 - - - - LCD_G5
1 DCMIPP_D5 TOUT

TIM8_CH1N - - - - LCD_G6
2 DCMIPP_D6 TOUT
page 92/234

TIM8_CH2N I2C1_SCL I3C1_SCL - - LCD_G7
3 DCMIPP_D7 TOUT

TIM8_BKIN2 - - - - LCD_B1
4 DCMIPP_D9 TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS

Port G
TIM8_ETR - - - - LCD_B2
5 DCMIPP_D10 TOUT
EVEN
PH2 I2C5_SDA I2C3_SDA - - - - ETH3_RGMII_GTX_CLK
TOUT

EVEN
PH3 - TIM5_CH3 I2C7_SCL - - - ETH3_RGMII_TXD3
TOUT
EVEN
PH4 - TIM5_CH2 LCD_R0 USB3DR_OVRCUR USBH_HS_OVRCUR ETH1_PTP_AUX_TS ETH3_PPS_OUT
TOUT
EVEN
PH5 UART7_RX - LCD_G1 USB3DR_VBUSEN USBH_HS_VBUSEN ETH2_PTP_AUX_TS -
TOUT
EVEN
PH6 I2C5_SCL I2C3_SCL I2C1_SMBA - - - ETH3_RGMII_TXD2
TOUT
EVEN
PH7 - TIM5_CH4 I2C7_SDA - - - ETH3_RGMII_RXD2
TOUT
Port H
EVEN
PH8 - TIM5_CH1 I2C3_SMBA I2C5_SMBA - - ETH3_RGMII_RXD3
TOUT
EVEN
PH9 - - ETH1_RGMII_CLK125 ETH1_MII_RX_ER - - -
TOUT
PH1 EVEN
- ETH2_MDC ETH1_MII_TXD2/ETH1_RGMII_TXD2 - - - -
0 TOUT
PH1 EVEN
- ETH2_MDIO ETH1_MII_TXD3/ETH1_RGMII_TXD3 - - - -
1 TOUT

PH1 EVEN
TIM10_CH1 - ETH1_MII_RXD2/ETH1_RGMII_RXD2 - - - -
2 TOUT
PH1 EVEN
TIM11_CH1 - ETH1_MII_RXD3/ETH1_RGMII_RXD3 - - - -
3 TOUT
PI0 TIM8_BKIN - - - - LCD_B3
DCMIPP_D11 TOUT
PI1 TIM8_CH3N I2C1_SDA I3C1_SDA - - LCD_B4
DCMIPP_D8 TOUT
PI2 TIM8_CH1 - - - - LCD_B5
DCMIPP_D13 TOUT
EVEN
PI3 TIM8_CH2 - - - - LCD_B6 PSSI_D14/DCMIPP_D14
TOUT
Port I
EVEN
PI4 TIM8_CH3 - - - - LCD_B7 PSSI_D15/DCMIPP_D15
TOUT
PI5 TIM5_CH2 - - - - LCD_DE
DCMIPP_D1 TOUT
EVEN
PI6 TIM3_CH1 - - - - LCD_VSYNC -
TOUT
page 93/234
EVEN
PI7 TIM3_CH2 - - - - LCD_HSYNC -
TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
EVEN
PI8 - - - - - - -
TOUT
EVEN
PI9 TIM16_BKIN SDVSEL2 FMC_NWAIT - DSI_TE LCD_B0 -
TOUT

EVEN
PI10 TIM4_CH1 SDVSEL1 - - FMC_AD12/FMC_D12 DSI_TE -
TOUT
EVEN
PI11 - TIM4_CH3 SDMMC3_D3 FMC_AD15/FMC_D15 - - -
TOUT
Port I
EVEN
PI12 TIM11_CH1 - - - FMC_A2 LCD_G0 -

TOUT
EVEN
PI13 TIM10_CH1 - - - FMC_A3 LCD_G1 -
TOUT
PI14 TIM1_CH3N - FMC_NWAIT - FMC_AD10/FMC_D10 -
DCMIPP_D4 TOUT
PI15 TIM1_BKIN2 SDVSEL1 SDMMC3_CDIR - - -
DCMIPP_D9 TOUT
EVEN
PJ0 - USBH_HS_VBUSEN - ETH2_PTP_AUX_TS FMC_A11 ETH3_PPS_OUT -
TOUT
PJ1 TIM8_CH1N I2C1_SCL I3C1_SCL - FMC_A7 -
DCMIPP_VSYNC TOUT
USBH_HS_OVRCU EVEN
PJ2 TIM8_CH4N - - FMC_A14 - -
R TOUT

EVEN
PJ3 TIM8_CH3 - - - FMC_A10 - -
TOUT
EVEN
PJ4 TIM8_CH4 I2C2_SMBA I2C5_SMBA - - - -
TOUT
EVEN
PJ5 TIM8_CH1 - - - FMC_A8 - -
TOUT
PJ6 TIM1_CH1 I2C6_SMBA - - - -
DCMIPP_D7 TOUT
Port J
PJ7 TIM8_CH2N I2C1_SMBA - - FMC_A12 -
DCMIPP_D0 TOUT
EVEN
PJ8 TIM8_CH2 - - - FMC_A9 - PSSI_D14/DCMIPP_D14
TOUT
PJ9 TIM8_BKIN - - - FMC_A5 -
DCMIPP_PIXCLK TOUT
PJ10 TIM8_ETR I2C1_SDA I3C1_SDA - FMC_A6 -
DCMIPP_HSYNC TOUT
PJ11 TIM8_CH3N - - - FMC_A13 -
DCMIPP_D12 TOUT
page 94/234
PJ12 TIM8_BKIN2 I2C2_SCL I3C2_SCL - FMC_A15 -
DCMIPP_D13 TOUT
EVEN
PJ13 TIM10_CH1 I2C2_SDA I3C2_SDA - - - PSSI_D15/DCMIPP_D15
TOUT
DS14284 - Rev 2
DCMI / PSSI /
DCMIPP / DSI /
ETH1 / I2C2/4/5/8 /
UART7 / USART2
TIM4/5/10/12/14 /
USBH_HS
EVEN
PJ14 - - - - FMC_A1 LCD_R0 -
TOUT
Port J
EVEN
PJ15 TIM11_CH1 - - - FMC_A4 LCD_R1 -
TOUT

PK0 TIM1_ETR - SDMMC3_D123DIR - FMC_AD11/FMC_D11 -
DCMIPP_D11 TOUT
PK1 TIM1_BKIN SDVSEL2 SDMMC3_D0DIR - FMC_AD13/FMC_D13 -
DCMIPP_D10 TOUT
PK2 TIM1_CH2N I2C6_SDA - - FMC_NCE3 -

DCMIPP_D6 TOUT
PK3 TIM1_CH3 - - - FMC_AD8/FMC_D8 FMC_NCE4
DCMIPP_D3 TOUT
Port K
PK4 TIM1_CH1N - SDMMC3_CKIN - FMC_AD9/FMC_D9 -
DCMIPP_D8 TOUT
PK5 TIM1_CH4 - I2C5_SCL - FMC_AD5/FMC_D5 -
DCMIPP_D1 TOUT
PK6 TIM1_CH2 I2C6_SCL - FMC_AD14/FMC_D14 FMC_AD7/FMC_D7 -
DCMIPP_D5 TOUT
PK7 TIM1_CH4N - I2C5_SDA FMC_NCE4 FMC_AD6/FMC_D6 -
DCMIPP_D2 TOUT
EVEN
PZ0 I2C8_SDA - LPTIM3_CH2 I3C4_SDA - - -
TOUT

EVEN
PZ1 I2C8_SCL I2C8_SMBA - I3C4_SCL - - -
TOUT
EVEN
PZ2 I2C8_SCL - - I3C4_SCL - - -
TOUT
EVEN
TOUT
EVEN
PZ4 I2C8_SCL - - I3C4_SCL - - -
TOUT
Port Z
EVEN
PZ5 - - LPTIM4_CH2 - - - -
TOUT
EVEN
PZ6 - - LPTIM4_CH2 - - - -
TOUT
EVEN
PZ7 - - LPTIM3_CH2 - - - -
TOUT
EVEN
PZ8 I2C8_SMBA LPTIM5_ETR - - - - -
TOUT
EVEN
TOUT
page 95/234
Memory mapping
5 Memory mapping
Refer to the product line reference manual (RM0457) for details on the memory mapping as well as the boundary
addresses for all peripherals.
DS14284 - Rev 2 page 96/234

Electrical characteristics
6 Electrical characteristics
6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of junction
temperature, supply voltage and frequencies by tests in production on 100% of the devices with an junction
temperature at TJ = 25 ° C and TJ = TJmax (given by the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics are indicated in the
table footnotes and are not tested in production. Based on characterization, the minimum and maximum values
refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2 Typical values

Unless otherwise specified, typical data are based on TJ = 25 °C, VDD = 3.3 V, VDDCORE = 0.82 V,
VDDCPU = 0.8 V, VDDGPU = 0.8 V. They are given only as design guidelines and are not tested in production.
Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion
lot over the full temperature range, where 95% of the devices have an error less than or equal to the value
indicated (mean±2σ).
6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.
6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9 .
6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10 .
Figure 9. Pin loading conditions Figure 10. Pin input voltage
Device pin
Device pin
VIN
C = 50 pF
DT47493V1
DT47494V1
DS14284 - Rev 2 page 97/234

6.1.6 Power supply scheme
Figure 11. Power supply scheme
VDDA18COMBOPHY
VDDCOMBOPHYTX
VDDCOMBOPHY
IOports
VDDA18LVDS
VDDPCIECLK
VVDD18DDR
VDD33UCPD
VDDA18USB
VDDA18DSI
VDDA18CSI
VVREFDDR
VDD33USB
VDDQDDR
VDDLVDS
VDDDSI
VDDCSI
VDDIO1
VDDIO2
VDDIO3
VDDIO4
PE[5:0] PE[15:6] PD[11:0] PB[11:0] DDR USB USB/PCIE UCPD LVDS DSI CSI
(SDMMC1 (SDMMC2 (OCTOSPIM IOs)
IOs) IOs) (port1) (port2) PHY HS PHY COMBOPHY PHY PHY PHY PHY
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VDDA18AON
VDDCPU
VDDGPU
VDDCORE
VSS
GPU CPU1
VDD IO CPU2, peripherals, RAM,
IOports IOs logic EXTI1, System logic
VDDCPU (D1)
VDDGPU domain domain
VDDCORE (D2) domain
VDD
VSW / Backup
VDD IO WKUP, IWDG1-4, BSEC, domain
IOports IOs logic RIFSC, RESETs
VSS VDD / Retention domain

VDDA18AON OTP, HSE, HSI
VDDA18PLLx PLLs D3 domain RETRAM
V08CAP
VDD Power switch Backup
VBAT regulator LPSRAM1
LSE, LSI, RTC, AWU, CPU3, peripherals,

BKUP, IO
IOports D3 IOs logic
Tamper, backup LPSRAM2/3, Backup
registers, IWDG5 EXTI2, MSI RAM
VSS
VDDA18ADC Analog domain

VREFBUF ADCs
VREF+ VREF+
VREF- VREF-
VSSA
DT68353V3
DS14284 - Rev 2 page 98/234

Caution: Each power supply pair (VDD/VSS, VDDCORE/VSS, VDDA/VSSA ...) must be decoupled with filtering ceramic
capacitors. These capacitors must be placed as close as possible to, or below, the appropriate pins on the
underside of the PCB to ensure good operation of the device. It is not recommended to remove filtering
capacitors to reduce PCB size or cost. This might cause incorrect operation of the device.
The number of needed capacitances and their values are provided in AN5489 "Getting started with STM32MP25x
lines hardware development" available from the ST website www.st.com.
6.1.7 Current consumption measurement
Figure 12. Current consumption measurement scheme
IDDCORE IDDA18
VDDCORE VDDA18PLL1
VDDCORE VDDA18
VDDCSI VDDA18PLL2
VDDDSI VDDA18PLL3
VDDLVDS VDDA18DDR
VDDCOMBOPHY VDDA18DSI
VDDCOMBOPHYTX VDDA18CSI
VDDPCIECLK VDDA18LVDS
VDDA18COMBOPHY
IDDCPU
VDDCPU VDDA18USB
VDDCPU
IDDGPU IDDA18AON
VDDGPU VDDA18AON
VDDGPU VDDA18AON
IDD IDD33USB
VDD VDD33USB
VDD VDD33USB
VDDIO1 VDD33UCPD
VDDIO2
IDDA18ADC
VDDIO3 VDDA18ADC
VDDIO4 VDDA18ADC
IBAT
VBAT
DT74103V1
VSS VSSA VSSAON VBAT
6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 14. Voltage characteristics, Table 15. Current
characteristics, and Table 16. Thermal characteristics may cause permanent damage to the device. These are
stress ratings only and the functional operation of the device at these conditions is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability. Device mission profile (application
conditions) is compliant with JEDEC JESD47 qualification standard, extended mission profiles are available on
demand.
DS14284 - Rev 2 page 99/234

Table 14. Voltage characteristics

Specified by design, not tested in production.
All powers and grounds pins must always be connected to an external power supply, in the permitted
range.
Symbols Ratings Min Max Unit
VDDX - VSS
External supply voltage (including VDD, VDDIOx, VBAT) -0.3 2
range 1.8 V
VDDX - VSS External supply voltage (including VDD, VDDIOx, VBAT, VDD33USB,
-0.3 3.7
range 3.3 V VDD33UCPD)
External core supply voltage (including VDDCORE, VDDCPU,

VDDCORE – VSS VDDGPU, VDDCSI, VDDDSI, VDDLVDS, VDDCOMBOPHY, -0.3 0.99
VDDCOMBOPHYTX, VDDPCIECLK)
VDDQDDR – VSS DDR IO supply voltage -0.3 1.575 V

1.8 V supply voltage (including VDDA18AON, VDDA18PLL1,
VDDA18 – VSS VDDA18PLL2, VDDA18PLL3, VDDA18DSI, VDDA18CSI, VDDA18LVDS, -0.3 1.98
VDDA18COMBOPHY, VDDA18DDR, VDDA18USB, VDDA18ADC)
Input voltage on TT_xx pins (VDDIOxVRSEL = 0) 3.6

Input voltage on TT_xx pins (VDDIOxVRSEL = 1) VSS - 1.98

VIN
0.3
VDD3V3_UCPD
Input voltage on UCPD pins
+ 1.935
Variations between different VDDX power pins of the same
|∆VDDx| - 50
domain mV
|VSSx-VSS| Variations between all the different ground pins - 50
1. VIN maximum must always be respected. Refer to next table for the maximum allowed injected current values.
Table 15. Current characteristics

Symbols Ratings Condition Max Unit
TJ > 110 °C 4
Output current sunk/source by
IIO 90 °C < TJ ≤ 110 °C 10
any I/O and control pin mA
-40 °C < TJ ≤ 90 °C 20
∑IINJ(PIN) Total injected current (sum of all I/Os and control pins) ±25
1. When several inputs are submitted to a current injection, the maximum ∑IINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 16. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150

°C
TJ Maximum junction temperature (suffix 3) 125
DS14284 - Rev 2 page 100/234

6.3 Operating conditions
6.3.1 General operating conditions
Table 17. General operating conditions

Voltages in this table represent DC value at ball level.
Operating
Symbol Parameter Min Typ Max Unit
conditions
Fcpu1 Clock frequency of Cortex-A35 0 - 1200
Clock frequency of Cortex-A35 in

Fcpu1_overdrive(1) STM32MP25xF only 0 - 1500
overdrive
Fgpu(1) Clock frequency of GPU/NPU 0 - 800
Clock frequency of GPU/NPU in

Fgpu_overdrive(1) STM32MP25xF only 0 - 900
overdrive
DDR3L DLL ON 300 - 1066
DDR3L DLL OFF 0 - 125
Fddrctrl Clock frequency of DDR memory(2) DDR4 DLL ON 625 - 1200

DDR4 DLL OFF 20 - 125
LPDDR4 10 - 1200
Fck_icn_hs_mcu Clock frequency of Cortex-M33, MCU MLAHB memory 0 - 400
MHz
Fck_icn_m_gpu (1)
Clock frequency of GPU/NPU bus 0 - 600
Clock frequency of Cortex-A35 AXI buses, DDRCTRL AXI

Fck_icn_ddr 0 - 600
buses
Clock frequency of PCIE, USB3DR, USBH, ETH1, ETH2
Fck_icn_hsl 0 - 300
buses
Clock frequency of MCU MLAHB,
Cortex-M0+, MCU and SmartRun In Run mode 0 - 200
Fck_icn_ls_mcu domain peripherals buses
Clock frequency of Cortex-M0+ and In D3 autonomous
0 - 16
SmartRun domain peripherals buses mode
Fck_icn_sdmmc Clock frequency of MPU AHB5 0 - 200
Fck_icn_nic Clock frequency of MPU GIC and BOOTROM 0 - 400
Fck_icn_vid(1) Clock frequency of MPU VDEC and VENC bus 0 - 600
VDDA18AON(3) Internal analog supply voltage 1.71 1.8 1.89(4) V
1.8 V range 1.71 1.8 1.89(4) V

VDD(3) I/Os supply voltage
3.3 V range(5) 3 3.3 3.6 V
VDDIO1, VDDIO2, 1.8 V range 1.71 1.8 1.89(4) V

Specific I/Os supply voltage
VDDIO3, VDDIO4(6) 3 V / 3.3 V range(7) . 2.7 3.3 3.6 V
VDDCORE, Run1/2 mode 0.79 0.82 0.842 V

VDDCSI, VDDDSI,
Stop1/2, LP-Stop1/2
VDDLVDS, 0.79 0.82 0.842 V
Main digital logic supply voltage mode
VDDCOMBOPHY,
VDDCOMBOPHYTX, LPLV-Stop1/2 mode 0.64 0.67 0.842(9) V
VDDPCIECLK(8) Standby1/2 mode 0 0 0.48 V
DS14284 - Rev 2 page 101/234

Operating
conditions
Run1, Stop1 or LP-

Stop1 mode,
Fcpu1_overdrive 0.87 0.91 0.935 V
range(1)
Run1, Stop1 or LP-
Stop1 mode, Fcpu1 0.765 0.8 0.842 V
VDDCPU Cortex-A35 supply voltage range
LPLV-Stop1
0.64 0.67 0.842(9) V
(LPCFG_D1 = 0)
Run2, Stop2, LP-
Stop2 , LPLV-Stop2 0 0 0.48 V
or Standby1/2 mode
Fgpu1_overdrive range 0.86 0.9 0.961 V
VDDGPU(1) GPU supply voltage
Fgpu1 range 0.76 0.8 0.839 V
VDDA18PLL1,
VDDA18PLL2,
VDDA18PLL3,
VDDA18DSI, 1.8 V analog supply for PLLs, DSI/CSI/LVDS PHYs and
1.71 1.8 1.89(4) V
VDDA18CSI, COMBOPHY
VDDA18LVDS,
VDDA18COMBOPH
(8)(10)
Y
VDDA18DDR(11) 1.8 V analog supply for DDRPHY 1.71 1.8 1.89 V
VDDA18USB(11) 1.8 V analog supply for USBPHY 1.75 1.8 1.89(4) V
VDD33USB,
3.3V USB supply 3.07 3.3 3.6 V
VDD33UCPD
VDDA18ADC ADC operating voltage 1.62 1.8 1.89(4) V
VREF+ ADC reference voltage 1.1 - VDDA18ADC V
VBAT Backup operating voltage 2.3(12) - 3.6 V
DDR3L memory 1.283 1.35 1.45

VDDQDDR DDR PHY supply voltage(2) DDR4 memory 1.14 1.2 1.26 V
LPDDR4 memory 1.06 1.1 1.17
V08CAP Backup regulator output voltage(13) 0.72 0.8 0.88 V
VDDxx + 0.3
I/O (14)
I/O when ADC is

used VDDA18ADC
+ 0.3
ANA0/ANA1
VIN I/O Input voltage -0.3 - V
I/O when PVD_IN is VDDA18AON +
used 0.3
VDD3V3_UCPD
UCPD IOs
+ 1.935
DDR I/O VDDQDDR
TJ Junction temperature range Suffix 3 version -40 - 125 °C
1. Feature might be limited or absent in some devices or packages. See Table 1 for details.
2. Values depend on the external memory device choice.
3. VDDA18AON and VDD must be present before any other supply.
DS14284 - Rev 2 page 102/234

4. Static condition. 1.98 V allowed during transients.

5. Requires VDDIOVRSEL = 0.
6. These supplies are independent, that means each one could be in any of the following voltage ranges: 0 V (OFF), 1.8 V, 3 V
or 3.3 V.
7. Requires VDDIOxVRSEL = 0
8. All these supplies are usually connected together.
9. This is the max allowed voltage, however LPLV-Stop mode is relevant only to save power, so requires voltage as low as
possible (that is external regulator set for typical value, then the maximum voltage is few percent above the typical due to
regulator accuracy).
10. The VDDA18PLLx must be connected together.
11. Could be connected to other VDDA18xx supplies if min/max range fullfilled.
12. Except when connected to VDD where lower limit is then 1.71 V.
13. This pin is used only to connect a decoupling capacitor for internal backup regulator, this pin must never be used externally
for other purposes.
14. VDDxx stands for VDD, VDDIO1, VDDIO2, VDDIO3 or VDDIO4.
6.3.2 Operating conditions at power-up / power-down

Subject to general operating conditions.
Table 18. Operating conditions at power-up / power-down

VDDA18AON and VDD must be present before other supplies.
Operating
Symbol Parameter Min Max Unit
conditions
Rise time rate 20 1500

tVDDA18AON(1) VDDA18AON transitions
Fall time rate 20 1500
tVDD(1) VDD/VDDIOx transitions
tVDDCORE VDDCORE transitions
tVDDCPU, tVDDGPU, Rise time rate 10 1500
tVDDCSI, tVDDSI,
tVDDLVDS, VDDCPU, VDDGPU, VDDCSI, VDDDSI, VDDLVDS, VDDCOMBOPHY,
tVDDCOMBOPHY, VDDCOMBOPHYTX, VDDPCIECLK transitions Fall time rate 10 1500
tVDDCOMBOPHYTX, µs/V
tVDDPCIECLK
VDDA18PLL1, VDDA18PLL2, VDDA18PLL3, VDDA18DSI, VDDA18CSI, Rise time rate 10 1500

tVDDA18 VDDA18LVDS, VDDA18COMBOPHY, VDDA18DDR, VDDA18USB,
VDDA18ADC transitions Fall time rate 10 1500

tVDD33 VDD33USB, VDD33UCPD transitions
tVDDQDDR VDDQDDR transitions
Rise time rate 20 ∞
tVBAT VBAT transitions
1. VDDA18AON and VDD must be present before any other supply.
6.3.3 Embedded reset and power control block characteristics

The parameters given in Table 19 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17. General operating conditions.
DS14284 - Rev 2 page 103/234

Table 19. Embedded reset and power control block characteristics

Evaluated by characterization, not tested in production unless otherwise specified.
Symbol Paramete Conditions Min Typ Max Unit
tRSTTEMPO Reset temporization After POR released - 440 - μs
VDDA18AON thresholds
VPOR_ANA(1) Power‑on reset threshold Rising edge 1.62 1.67 1.71

V
VPDR_ANA(1) Power‑down reset threshold Falling edge 1.58 1.63 1.67
Vhyst_POR_ANA Hysteresis voltage of POR/PDR - - 40 - mV
IPOR_PDR(VDDA18AON) Supply current on VDDA18AON Always ON - 1.25 - μA
VDD thresholds
VPOR(1) Power‑on reset threshold Rising edge 1.62 1.67 1.71

V
VPDR(1) Power‑down reset threshold Falling edge 1.58 1.63 1.67
Vhyst_POR Hysteresis voltage of POR/PDR - - 40 - mV
IPOR_PDR(VDDA18AON) Supply current on VDDA18AON Always ON - 0.75 - μA

VDD = 1.8 V - 0.5 -

IPOR_PDR(VDD) Supply current on VDD Always ON μA
VDD = 3.3 V - 0.92 -
Rising edge 1.62 1.67 1.71

VBOR0(1) Brown-out reset threshold 0 V
Falling edge 1.58 1.63 1.67
VBOR1(1) Brown-out reset threshold 1 Falling edge - - 2.97 V
Vhyst_BOR0 Hysteresis voltage of BOR0 - - 40 - mV
Vhyst_BOR1 Hysteresis voltage of BOR1 - - 80 - mV
IBOR(VDDA18AON) Supply current on VDDA18AON BOR enabled in OTP - 0.75 - μA
VDDCPU thresholds
Normal modes 0.63 0.66 0.69

VRDY_VDDCPU(1) Threshold on rising edge V
LPLV modes 0.55 0.58 0.61
Vhyst_VDDCPU Hysteresis on falling edge - - 23 - mV
Rising edge 180 400 750

Tdelay_VDDCPU Delay after detection μs
Falling edge - 0 -
IRDY_VDDCPU(VDDA18AON) Supply current on VDDA18AON Always ON - 1.2 - μA
VDDCORE thresholds
Normal modes 0.63 0.66 0.69

VRDY_VDDCORE(1) Threshold on rising edge V
LPLV modes 0.55 0.58 0.61
Vhyst_VDDCORE Hysteresis on falling edge - - 23 - mV
Rising edge 180 400 750

Tdelay_VDDCORE Delay after detection μs
Falling edge - 0 -
IRDY_VDDCORE(VDDA18AON) Supply current on VDDA18AON Always ON - 1.2 - μA
1. Guaranteed by test in production.
6.3.4 Embedded reference voltage

The parameters given in Table 20 and Table 21 are derived from tests performed under ambient temperature and
VDD supply voltage conditions summarized in Table 17. General operating conditions .
DS14284 - Rev 2 page 104/234

Table 20. Embedded reference voltage characteristics

Symbol Parameter Conditions Min Typ Max Unit
VREFINT(1) Internal reference voltages -40 °C < TJ < 125 °C 0.792 0.8 0.808 V
ADC sampling time when reading the

tS_VREFINT(2) - 34 - - ns
internal reference voltage
Internal reference voltage spread over
DVREFINT -40 °C < TJ < 125 °C -4 - +4 mV
the temperature range
Tcoeff Average temperature coefficient -40 °C < TJ < 125 °C - - 43 ppm/°C
VDDcoeff Average voltage coefficient 1.71 < VDDA18AON < 1.89 - - 1250 ppm/V

2. Specified by design, not tested in production.
Table 21. Embedded reference voltage calibration value
Symbol Parameter Memory address

Raw data acquired on ADC1 at temperature of 30 °C,

VREFINT_CAL
VDDA18ADC = VREF+ = 1.8 V 0x4400 01B8[11:0](1)(2)
1. This is BSEC_FVR110 register which is not automatically shadowed with OTP content, so a fuse read sequence must be
issued to get the register updated once (clear after reading). Refer to product reference manual - BSEC section "Operations
on fuses".
2. Must be read in 32‑bit words and relevant masking and shifting must be performed to isolate the required bits.
6.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, ambient
temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program
location in memory and executed binary code.
The current consumption is measured as described in Figure 12. Current consumption measurement scheme.
All the Run mode current consumption measurements given in this section are performed with a CoreMark code
unless otherwise specified.
Supply current characteristics are evaluated by characterization, not tested in production unless otherwise
specified.
6.3.5.1 Typical and maximum current consumption

The device is placed under the following conditions:
• All I/O pins are in analog input mode except when explicitly mentioned
• All peripherals are disabled except when explicitly mentioned
• RTC/LSE are disabled, unless otherwise specified
• BKPSRAM, RETRAM, LPSRAM1 backup supplies in low-power modes (such as LPLV-Stop, Standby and
VBAT modes) are disabled, unless otherwise specified
DS14284 - Rev 2 page 105/234

• Unless otherwise specified, the typical values are obtained for:

– VDD / VDDIOx/VBAT = 3.3 V
– VDDCORE = 0.82 V
– VDDCPU = 0.8 V
– VDDGPU = 0.8 V
– VDDA18 / VDDA18AON = 1.8 V
and the maximum values are obtained for:
– VDD / VDDIOx / VBAT = 3.6 V
– VDDCORE = 0.842 V
– VDDCPU = 0.842 V
– VDDGPU = 0.839 V
– VDDA18 / VDDA18AON = 1.89 V
The parameters given in Table 22 to Table 34 are derived from tests performed under supply voltage conditions
summarized in Table 17. General operating conditions .
DS14284 - Rev 2 page 106/234

DS14284 - Rev 2
Table 22. Current consumption (IDDCORE) in Run modes

Except otherwise noted, typical values given with VDDCORE = 0.82 V, VDDCPU = 0.8 V and VDDGPU = 0.8 V, maximum values given with VDDCORE = 0.842 V, VDDCPU = 0.842 V and
VDDGPU = 0.839 V.
Conditions Typ Max
AXI
Symbol Parameter D2 D3 CPU1 CPU2 CPU3 GPU Unit
D1 (CPU1)(1) clk TJ = TJ = TJ = TJ = TJ =
- (CPU2) (CPU3) Osc. clk clk clk clk
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
mode mode (MHz) (2) (MHz) (MHz) (MHz)

1500(5) 600 400 200 900(6) 245 330 600 780 1200
Supply All DRun HSE + 1200 600 400 200 800 245 320 590 770 1200
Run1 SRun1
IDDCORE(3) current in Run peripherals (CRun: HSI + mA
(CRun) (CRun) 750 600 400 200 800 245 320 590 770 1200
mode Enabled(4) P0&P1) PLL
600 600 400 200 800 245 320 590 770 1200
1500(5) 600 400 200 900(6) 195 270 540 720 1100
Run1 SRun1
(CRun) (CRun) 750 600 400 200 800 195 260 530 710 1100
600 600 400 200 800 195 260 530 710 1100
1500(5) 600 400 200 - 195 270 530 710 1100

Supply All DRun HSE + 1200 600 400 200 - 195 260 530 710 1100
Run1 SRun1
(CRun) (CRun) 750 600 400 200 - 195 260 530 710 1100
600 600 400 200 - 195 260 530 710 1100
1500(5) 600 400 200 - 185 250 520 700 1100

Supply All HSE + 1200 600 400 200 - 185 250 520 700 1100
DRun Run1 SRun1
IDDCORE(9) current in Run peripherals HSI + mA
(CRun: P0) (CRun) (CRun) 750 600 400 200 - 185 250 520 700 1100
mode Enabled(4) PLL
600 600 400 200 - 185 250 520 700 1100
1500(5) 600 - - 900(6) 225 300 570 750 1100

Supply All DRun HSE +
Run1 SRun1 1200 600 - - 800 220 300 570 750 1100
(Cstop) (CStop) 750 600 - - 800 220 300 560 740 1100
600 600 - - 800 220 300 560 740 1100
1500(5) 600 - - 900(6) 170 240 510 690 1100

Run1 SRun1
page 107/234
IDDCORE(7) current in Run peripherals (CRun: HSI + 1200 600 - - 800 170 240 510 680 1100 mA
(Cstop) (CStop)
750 600 - - 800 170 240 500 680 1100
DS14284 - Rev 2
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C

Run1 SRun1
IDDCORE(7) current in Run peripherals (CRun: HSI + 600 600 - - 800 170 240 500 680 1100 mA
(Cstop) (CStop)
1500(5) 600 - - - 170 240 510 680 1100

Supply All DRun HSE + 1200 600 - - - 170 240 500 680 1100

Run1 SRun1
(Cstop) (CStop) 750 600 - - - 170 240 500 680 1100
600 600 - - - 170 240 500 680 1100
1500(5) 600 - - - 160 230 490 670 1000

Supply All HSE + 1200 600 - - - 160 230 490 670 1000
DRun Run1 SRun1
IDDCORE(9) current in Run peripherals HSI + mA
(CRun: P0) (Cstop) (CStop) 750 600 - - - 160 230 490 670 1000
mode Enabled(4) PLL
600 600 - - - 160 230 490 670 1000
1500(5) 600 400 200 900(6) 97 160 420 600 940

Run1 SRun1
(CRun) (CRun) 750 600 400 200 800 96.5 160 420 600 940
mode Disabled P0&P1) PLL
600 600 400 200 800 96.5 160 420 600 930
1500(5) 600 400 200 - 97 160 420 600 930

Supply All DRun HSE + 1200 600 400 200 - 97 160 420 600 930
Run1 SRun1
(CRun) (CRun) 750 600 400 200 - 96.5 160 420 600 930
600 600 400 200 - 96.5 160 420 600 930
1500(5) 600 400 200 - 97 160 420 600 930

Supply All HSE + 1200 600 400 200 - 97 160 420 600 930
DRun Run1 SRun1
IDDCORE current in Run peripherals HSI + mA
(CRun: P0) (CRun) (CRun) 750 600 400 200 - 96.5 160 420 600 930
mode Disabled PLL
600 600 400 200 - 96.5 160 420 600 930
1500(5) 600 - - - 49.5 100 370 540 870
1200 600 - - - 49 100 370 540 870

Run1 SRun1
IDDCORE(11) current in Run peripherals (CRun: HSI + 750 600 - - - 49 100 360 540 870 mA
(Cstop) (CStop)
page 108/234
600 600 - - - 48.5 100 360 540 870

300 300 - - - 43.5 94 360 530 860
DS14284 - Rev 2
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
HSE +
HSI + 150 150 - - - 41 91 350 530 860
Supply All DRun PLL
Run1 SRun1
IDDCORE(11) current in Run peripherals (CRun: mA
(Cstop) (CStop) HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850
mode Disabled P0&P1)
HSE + HSE HSE

- - - 35.5 84 350 520 850
HSI 40 40
1500(5) 600 - - - 49 100 370 540 870
1200 600 - - - 49 100 360 540 870

HSE + 750 600 - - - 48.5 100 360 540 870

HSI +
Supply All PLL 600 600 - - - 48.5 100 360 540 870
DRun Run1 SRun1
IDDCORE current in Run peripherals mA
(CRun: P0) (Cstop) (CStop) 300 300 - - - 43.5 94 360 530 860
mode Disabled
150 150 - - - 41 91 350 530 860
HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850
HSE + HSE HSE
- - - 35.5 84 350 520 850
HSI 40 40
- HSI 64 400 - - 83 140 400 580 910
HSE +
HSI + - HSI 64 200 - - 56 110 370 550 870
PLL
Supply All - HSI 64 100 - - 43 92 360 530 860
DStop1 Run1 SRun1
(CStop) (CRun) (CStop) HSI
mode Disabled HSI - HSI 64 - - 38.5 89 350 520 850
64
HSE + HSE
- HSI 64 - - 34 82 350 520 850
HSI 40
- HSI 64 400 - - 83 160 400 580 910
HSE +
HSI + - HSI 64 200 - - 56 120 370 550 870
PLL
Supply All DStandby(12) - HSI 64 100 - - 43 95 360 530 860
Run2 SRun1
IDDCORE current in Run peripherals (13) mA
(CRun) (CStop) HSI
mode Disabled (CStandby) HSI - HSI 64 - - 38.5 90 350 520 850
64
HSE + HSE
- HSI 64 - - 34 83 350 520 840
HSI 40
page 109/234
Supply All DStandby HSE + - HSI 64 400 200 - 85 170 410 580 910
Run2 SRun1
IDDCORE current in Run peripherals (CStandby)(12) HSI + mA
(CRun) (CRun) - HSI 64 200 100 - 57.5 120 370 550 870
mode Disabled (13) PLL
DS14284 - Rev 2
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
HSE +
HSI + - HSI 64 100 50 - 43.5 95 360 530 860
PLL
Supply All DStandby
Run2 SRun1
IDDCORE current in Run peripherals (CStandby)(12) HSI HSI mA
(CRun) (CRun) HSI - HSI 64 - 39 91 350 530 850
mode Disabled (13) 64 64

HSE + HSE HSE
- HSI 64 - 34.5 83 350 520 850
HSI 40 40
1500(5) 600 - - - 49 100 360 540 870

1200 600 - - - 49 100 360 540 870

HSE + 750 600 - - - 48.5 100 360 540 870
HSI +
Supply All PLL 600 600 - - - 48.5 100 360 540 870
DRun Run1 SRun1
(CSleep) (Cstop) (CStop) 300 300 - - - 43.5 94 360 530 860
mode Disabled
150 150 - - - 41 91 350 530 860
HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850
HSE + HSE HSE
- - - 35.5 84 350 520 850
HSI 40 40
1500(5) 600 - - - 48.5 99 360 540 870
1200 600 - - - 48.5 99 360 540 870

HSE + 750 600 - - - 48.5 99 360 540 870
HSI +
Supply All PLL 600 600 - - - 48.5 99 360 540 870
DRun(14) Run1 SRun1
(eCSleep) (Cstop) (CStop) 300 300 - - - 43.5 94 360 530 860
mode Disabled
150 150 - - - 41 91 350 530 860
HSI HSI 64 HSI 64 - - - 36.5 86 350 520 850
HSE + HSE HSE
- - - 35.5 84 350 520 850
HSI 40 40
- HSI 64 400 - - 65.5 120 380 560 890
HSE +
HSI + - HSI 64 200 - - 47.5 97 360 540 860
Supply All
DStop1 Run1 SRun1 PLL
IDDCORE current in Run peripherals - HSI 64 100 - - 38.5 87 350 530 850 mA
(CStop) (CSleep) (CStop)
mode Disabled
page 110/234
HSI
HSI - HSI 64 - - 35.5 85 350 520 850
64
DS14284 - Rev 2
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
Supply All
DStop1 Run1 SRun1 HSE + HSE
IDDCORE current in Run peripherals - HSI 64 - - 32.5 80 340 520 850 mA
(CStop) (CSleep) (CStop) HSI 40
mode Disabled
- HSI 64 400 - - 65.5 130 380 560 880
HSE +
HSI + - HSI 64 200 - - 47.5 110 360 540 860

PLL
Supply All DStandby - HSI 64 100 - - 38.5 88 350 530 850
Run2 SRun1
IDDCORE current in Run peripherals (CStandby)(12) mA
(CSleep) (CStop) HSI
mode Disabled (13) HSI - HSI 64 - - 35.5 86 350 520 850
64
HSE + HSE
- HSI 64 - - 32.5 80 340 520 840
HSI 40
1. P0 and P1 are state of cores inside CPU1 when in CRun state. 'P0&P1' indicate that both cores are executing a test software. 'P0' indicate that only P0 is executing a test software
while other core is clock gated (either in WFI or WFE or not present in the device).
2. ck_icn_ddr.
3. Values for STM32MP257x.
4. Activity on peripherals and bus masters other than processors, could lead to additional power consumption above these values, largely dependent on the amount of initialized
peripherals and their activity.
5. Typical value given with VDDCPU = 0.91 V, maximum values given with VDDCPU = 0.935 V.
6. Typical value given with VDDGPU = 0.9 V, maximum values given with VDDGPU = 0.961 V.
10. Values for STM32MP257x and STM32MP255x.
11. Not relevant for STM32MP251x.
12. CStandby = CStop and PDDS_D1 = 1.
13. VDDCPU is shutdown..
14. eCSleep mean CPU1 in enhanced CSleep with PLL1 automatically stopped (RCC_C1SREQSETR.ESLPREQ=1).
page 111/234
Table 23. Current consumption (IDDCPU) in Run modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Conditions Typ Max
AXI
Symbol Parameter D1 (CPU1) D2 D3 CPU1 CPU2 CPU3 GPU Unit
(1) clk TJ = TJ = TJ = TJ = TJ =
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
mode mode mode (MHz) (2) (MHz) (MHz) (MHz)
1500(5) 600 400 200 900(6) 245 290 360 410 510

All DRun HSE + 1200 600 400 200 800 165 210 270 320 410
Supply current Run1 SRun1
IDDCPU(3) peripherals (CRun: HSI + mA
in Run mode (CRun) (CRun) 750 600 400 200 800 105 130 200 240 330
Enabled(4) P0&P1) PLL
600 600 400 200 800 84.5 110 170 220 310
1500(5) 600 400 200 900(6) 245 290 360 410 510
All DRun HSE + 1200 600 400 200 800 165 210 270 320 410
600 600 400 200 800 84 110 170 220 310
1500(5) 600 400 200 - 245 290 360 410 510

All DRun HSE + 1200 600 400 200 - 165 210 270 320 410
in Run mode (CRun) (CRun) 750 600 400 200 - 105 130 200 240 330
600 600 400 200 - 84.5 110 170 220 310
1500(5) 600 400 200 - 130 160 230 280 370

All HSE + 1200 600 400 200 - 89.5 120 180 220 310
Supply current DRun Run1 SRun1
IDDCPU(9) peripherals HSI + mA
in Run mode (CRun: P0) (CRun) (CRun) 750 600 400 200 - 57 73 140 180 270
Enabled(4) PLL
600 600 400 200 - 46 61 130 170 260
1500(5) 600 - - 900(6) 245 290 360 410 510

All DRun HSE + 1200 600 - - 800 165 210 270 320 410
in Run mode (Cstop) (CStop) 750 600 - - 800 105 130 200 240 330
600 600 - - 800 84.5 110 170 220 310
1500(5) 600 - - 900(6) 245 290 360 410 510

All DRun HSE + 1200 600 - - 800 165 210 270 320 410
in Run mode (Cstop) (CStop)
page 112/234
Enabled(4) P0&P1) PLL 750 600 - - 800 105 130 200 240 330
600 600 - - 800 84.5 110 170 220 310
DS14284 - Rev 2
Conditions Typ Max
AXI
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
1500(5) 600 - - - 245 290 360 410 530

All DRun HSE + 1200 600 - - - 165 210 270 320 420
in Run mode (Cstop) (CStop) 750 600 - - - 105 130 200 240 330
600 600 - - - 84 110 170 220 300

1500(5) 600 - - - 130 160 230 270 380
All HSE + 1200 600 - - - 89.5 120 180 220 310
in Run mode (CRun: P0) (Cstop) (CStop)
Enabled(4) PLL 750 600 - - - 57 73 140 180 270

600 600 - - - 46 61 130 170 260
1500(5) 600 400 200 900(6) 245 290 360 410 540
All DRun HSE + 1200 600 400 200 800 165 210 270 320 410
Disabled P0&P1) PLL
600 600 400 200 800 84 110 170 220 310
1500(5) 600 400 200 - 245 290 360 410 510

All DRun HSE + 1200 600 400 200 - 165 210 270 320 410
in Run mode (CRun) (CRun) 750 600 400 200 - 105 130 200 240 330
Disabled P0&P1) PLL
600 600 400 200 - 84 110 170 220 310
1500(5) 600 400 200 - 130 160 230 280 370

All HSE + 1200 600 400 200 - 89.5 120 180 220 310
in Run mode (CRun: P0) (CRun) (CRun) 750 600 400 200 - 57 73 140 190 270
Disabled PLL
600 600 400 200 - 46 60 130 170 260
1500(5) 600 - - - 245 290 360 410 510
1200 600 - - - 165 210 270 320 410
HSE + 750 600 - - - 105 130 200 240 330
All DRun HSI +
IDDCPU (10)
peripherals (CRun: PLL 600 600 - - - 84 110 170 220 310 mA
in Run mode (Cstop) (CStop)
Disabled P0&P1)
300 300 - - - 43.5 58 120 170 250
150 150 - - - 22.5 34 95 140 230
page 113/234
HSI HSI 64 HSI 64 - - - 11 23 81 130 220

DS14284 - Rev 2
Conditions Typ Max
AXI
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
All DRun
Supply current Run1 SRun1 HSE + HSE
IDDCPU(10) peripherals (CRun: HSE 40 - - - 7.45 16 77 130 210 mA
in Run mode (Cstop) (CStop) HSI 40
Disabled P0&P1)
1500(5) 600 - - - 130 160 230 280 370
1200 600 - - - 89.5 120 180 220 310

HSE + 750 600 - - - 57 73 140 180 270
HSI +
All PLL 600 600 - - - 46 61 130 170 260
IDDCPU
peripherals 300 300 - - - 24 35 97 150 230 mA

in Run mode (CRun: P0) (Cstop) (CStop)
Disabled
150 150 - - - 13 23 84 130 220
HSI HSI 64 HSI 64 - - - 6.85 17 76 120 210
HSE + HSE
HSE 40 - - - 5 14 74 120 210
HSI 40
- HSI 64 400 - - 2.25 10 71 120 200
- HSI 64 200 - - 2.3 9.9 71 120 200
All HSE +
Supply current DStop1 Run1 SRun1 - HSI 64 100 - - 2.25 9.9 71 120 200
IDDCPU peripherals HSI + mA
in Run mode (CStop) (CRun) (CStop)
Disabled PLL - HSI 64 HSI 64 - - 2.25 9.9 71 120 200
HSE
- HSI 64 - - 2.25 9.9 71 120 200
40
1500(5) 600 - - - 19 29 93 140 230
1200 600 - - - 13.5 23 84 130 220

HSE + 750 600 - - - 9.15 18 79 130 210
HSI +
All PLL 600 600 - - - 7.75 17 77 130 210
IDDCPU peripherals mA
in Run mode (CSleep) (Cstop) (CStop) 300 300 - - - 5.05 14 74 120 210
Disabled
150 150 - - - 3.65 12 72 120 210
HSI HSI 64 HSI 64 - - - 2.85 11 71 120 200
HSE + HSE
HSE 40 - - - 2.6 11 71 120 200
HSI 40
1500(5) 600 - - - 3.35 12 76 130 210

page 114/234
All HSE +
Supply current DRun(11) Run1 SRun1
1200 600 - - - 2.85 11 72 120 200
IDDCPU peripherals HSI + mA
in Run mode (eCSleep) (Cstop) (CStop)
Disabled PLL
750 600 - - - 2.85 11 72 120 200
DS14284 - Rev 2
Conditions Typ Max
AXI
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
600 600 - - - 2.85 11 72 120 200

HSE +
HSI + 300 300 - - - 2.85 11 72 120 200
All PLL
Supply current DRun(11) Run1 SRun1 150 150 - - - 2.85 11 72 120 200
in Run mode (eCSleep) (Cstop) (CStop)
Disabled HSI HSI 64 HSI 64 - - - 2.8 11 72 120 200

HSE + HSE
HSE 40 - - - 2.65 11 71 120 200
HSI 40
- HSI 64 400 - - 2.3 9.9 71 120 200
HSE +
HSI + - HSI 64 200 - - 2.25 9.9 71 120 200
All PLL
Supply current DStop1 Run1 SRun1 - HSI 64 100 - - 2.25 9.9 71 120 200
in Run mode (CStop) (CSleep) (CStop)
Disabled HSI - HSI 64 HSI 64 - - 2.25 9.9 71 120 200
HSE + HSE
- HSI 64 - - 2.25 9.9 71 120 200
HSI 40
2. ck_icn_ddr.
11. eCSleep mean CPU1 in enhanced CSleep (RCC_C1SREQSETR.ESLPREQ = 1).
page 115/234
Table 24. Current consumption (IDDGPU) in Run modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Not relevant for STM32MP251x and STM32MP253x.
Value are without GPU activity.
Conditions Typ Max
AXI
Symbol Parameter D1 D2 D3 CPU1 CPU2 CPU3 GPU Unit
clk TJ = TJ = TJ = TJ = TJ =
- (CPU1)(1) (CPU2) (CPU3) Osc. clk clk clk clk
(MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
(MHz) (MHz) (MHz) (MHz)

mode mode mode (2)
1500(5) 600 400 200 900(6) 14 35 160 240 390

All DRun HSE + 1200 600 400 200 800 11.5 31 150 220 370
IDDGPU(3) peripherals (CRun: HSI + mA

in Run mode (CRun) (CRun) 750 600 400 200 800 11.5 31 150 220 370
600 600 400 200 800 11.5 31 150 220 370
1500(5) 600 400 200 900(6) 14 35 160 240 390

All DRun HSE + 1200 600 400 200 800 11.5 31 150 220 370
IDDGPU(7) peripherals (CRun: HSI + mA
600 600 400 200 800 11.5 31 150 220 370
1500(5) 600 400 200 900(6) 6.65 27 150 230 380

All DRun HSE + 1200 600 400 200 800 6.05 24 140 210 360
IDDGPU peripherals (CRun: HSI + mA
Disabled P0&P1) PLL
600 600 400 200 800 6 24 140 210 360
2. ck_icn_ddr.
page 116/234
Table 25. Current consumption (IDD) in Run modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
1500(4) 600 400 200 900(5) 2.7 3.2 3.3 3.4 3.7

HSE + 1200 600 400 200 800 2.7 3.2 3.3 3.4 3.7
IDD (3V3)(3) HSI + mA
PLL 750 600 400 200 800 2.7 3.2 3.3 3.4 3.7
All DRun 600 600 400 200 800 2.7 3.2 3.3 3.4 3.7
peripherals (CRun:
in Run mode (CRun) (CRun)
Disabled P0&P1) 1500(4) 600 400 200 900(5) 1.25 1.6 1.6 1.6 1.7
HSE + 1200 600 400 200 800 1.25 1.6 1.6 1.6 1.7
PLL 750 600 400 200 800 1.25 1.6 1.6 1.6 1.7
600 600 400 200 800 1.25 1.6 1.6 1.6 1.7
1500(4) 600 400 200 - 2.7 3.2 3.3 3.4 3.7

HSE + 1200 600 400 200 - 2.7 3.2 3.3 3.4 3.7
PLL 750 600 400 200 - 2.7 3.2 3.3 3.4 3.7
All DRun 600 600 400 200 - 2.7 3.2 3.3 3.4 3.7
peripherals (CRun:
in Run mode (CRun) (CRun) 1500(4) 600 400 200 - 1.25 1.6 1.6 1.6 1.7
Disabled P0&P1)
HSE + 1200 600 400 200 - 1.25 1.6 1.6 1.6 1.7
PLL 750 600 400 200 - 1.25 1.6 1.6 1.6 1.7
600 600 400 200 - 1.25 1.6 1.6 1.6 1.7
HSI HSI 64 HSI 64 - - - 2.65 3.2 3.3 3.4 3.6
IDD (3V3)(3) HSE + HSE mA
All HSE 40 - - - 2.65 3.2 3.3 3.4 3.6
Supply current DRun Run1 SRun1 HSI 40
peripherals
in Run mode (CRun: P0) (CStop) (CStop) HSI HSI 64 HSI 64 - - - 1.25 1.5 1.6 1.6 1.7
Disabled
IDD (1V8)(6) HSE + HSE mA
HSE 40 - - - 1.25 1.5 1.6 1.6 1.7
HSI 40
IDD (3V3)(3) All DStandby(7) HSI - HSI 64 HSI 64 HSI 64 - 2.65 3.3 3.3 3.4 3.6 mA
Supply current (8)
Run2 SRun1
peripherals
page 117/234
IDD (1V8)(6) in Run mode (CRun) (CRun)

Disabled (CStandby) HSI - HSI 64 HSI 64 HSI 64 - 1.25 1.6 1.6 1.6 1.7 mA
DS14284 - Rev 2
2. ck_icn_ddr.
3. Typical value given with VDD = 3.3 V, maximum value given with VDD = 3.6 V.
6. Typical value given with VDD = 1.8 V, maximum value given with VDD = 1.89 V.
8. VDDCPU is shutdown.

page 118/234
Table 26. Current consumption (IDDA18) in Run modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
1500(3) 600 400 200 900(4) 4.35 5 5.1 5.2 6

Supply current in All DRun HSE + 1200 600 400 200 800 3.85 4.5 4.6 4.7 4.9
Run1 SRun1
IDDA18 Run mode peripherals (CRun: HSI + mA
(VDD = 1.8 V) (CRun) (CRun) 750 600 400 200 800 3.25 3.9 4 4.1 4.2
Disabled P0&P1) PLL
600 600 400 200 800 3.1 3.7 3.8 3.9 4
1500(3) 600 400 200 900(4) 4.35 5 5.1 5.2 5.4

Run1 SRun1
IDDA18 Run mode peripherals (CRun: HSI + mA
(VDD = 3.3 V) (CRun) (CRun) 750 600 400 200 800 3.25 3.9 4 4.1 4.2
Disabled P0&P1) PLL
600 600 400 200 800 3.1 3.7 3.8 3.9 4
1500(3) 600 400 200 - 4.35 5.2 5.5 5.7 6.1

All DRun HSE + 1200 600 400 200 - 3.9 4.7 5.1 5.2 5.6
Supply current in Run1 SRun1
IDDA18 peripherals (CRun: HSI + mA
Run mode (CRun) (CRun) 750 600 400 200 - 3.3 4.1 4.4 4.5 4.9
Disabled P0&P1) PLL
600 600 400 200 - 3.15 3.9 4.3 4.3 4.7
All HSI HSI 64 HSI 64 - - - 1.25 2 2.3 2.4 2.8

Supply current in DRun Run1 SRun1
IDDA18 peripherals HSE + HSE mA
Run mode (CRun: P0) (CStop) (CStop) HSE 40 - - - 1.25 1.9 2.3 2.4 2.8
Disabled HSI 40
All DStandby(5)
Supply current in Run2 SRun1
IDDA18 peripherals (6) HSI - HSI 64 HSI 64 HSI 64 - 1.2 1.8 2 2.2 2.9 mA
Run mode (CRun) (CRun)
Disabled (CStandby)
2. ck_icn_ddr.
page 119/234
Table 27. Current consumption (IDDA18AON) in Run modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
1500(3) 600 400 200 900(4) 4.4 5.9 5.4 5.3 5.9

Run1 SRun1
IDDA18AON Run mode (VDD = peripherals (CRun: HSI + mA
(CRun) (CRun) 750 600 400 200 800 4.4 5.9 5.4 5.3 5.1
1.8 V) Disabled P0&P1) PLL
600 600 400 200 800 4.4 5.9 5.4 5.3 5.1
1500(3) 600 400 200 900(4) 4.35 5.8 5.4 5.3 5.1
Run1 SRun1
(CRun) (CRun) 750 600 400 200 800 4.35 5.8 5.4 5.3 5.1
600 600 400 200 800 4.35 5.8 5.4 5.3 5.1
1500(3) 600 400 200 - 4.4 5.9 5.4 5.3 5.1

Supply current in All DRun HSE + 1200 600 400 200 - 4.4 5.9 5.4 5.3 5.1
Run1 SRun1
(CRun) (CRun) 750 600 400 200 - 4.4 5.9 5.4 5.3 5.1
600 600 400 200 - 4.4 5.9 5.4 5.3 5.1
1500(3) 600 400 200 - 4.35 5.8 5.4 5.3 5.1

Supply current in All DRun HSE + 1200 600 400 200 - 4.35 5.8 5.4 5.3 5.1
Run1 SRun1
(CRun) (CRun) 750 600 400 200 - 4.35 5.8 5.4 5.3 5.1
600 600 400 200 - 4.35 5.8 5.4 5.3 5.1
Supply current in All HSI HSI 64 HSI 64 - - - 480 570 590 610 640 μA
DRun Run1 SRun1
IDDA18AON Run mode (VDD = peripherals HSE + HSE HSE
(CRun: P0) (CStop) (CStop) - - - 4.4 5.9 5.4 5.3 5.1 mA
1.8 V) Disabled HSI 40 40
Supply current in All HSI HSI 64 HSI 64 - - - 445 530 550 560 600 μA
DRun Run1 SRun1
IDDA18AON Run mode (VDD = peripherals HSE + HSE HSE
(CRun: P0) (CStop) (CStop) - - - 4.35 5.8 5.4 5.3 5.1 mA
3.3 V) Disabled HSI 40 40
Supply current in All DStandby(5)

Run2 SRun1 HSI HSI
IDDA18AON Run mode (VDD = peripherals (6) HSI - HSI 64 - 490 580 590 610 640 μA
page 120/234
(CRun) (CRun) 64 64
1.8 V) Disabled (CStandby)
DS14284 - Rev 2
Conditions Typ Max
AXI
mode (MHz) 25 °C 25 °C 85 °C 105 °C 125 °C
Supply current in All DStandby

Run2 SRun1 HSI HSI
IDDA18AON Run mode peripherals (CStandby)(5) HSI - HSI 64 - 455 530 550 560 600 μA
(CRun) (CRun) 64 64
(VDD = 3.3 V) Disabled (6)

2. ck_icn_ddr.

Table 28. Current consumption (IBAT) in Run modes

VSW supplied by VDD.
Conditions Typ Max
Symbol Parameter Unit
VBAT voltage TJ = 25 °C TJ = 25 °C TJ = 85 °C TJ = 105 °C TJ = 125 °C
VBAT = 3.0 V 5 5.2 6.1 7.1 9.4

IBAT Supply current in Run mode (VDD = 1.8 V) μA
VBAT = 3.3 V 5.75 5.9 6.9 8 11
VBAT = 3.0 V 5 5.1 4.3 3.4 1.3

IBAT Supply current in Run mode (VDD= 3.3 V) μA
VBAT = 3.3 V 5.7 5.8 6 6 6.1
page 121/234
Table 29. Current consumption in Stop modes
DS14284 - Rev 2

VDDGPU = 0.839 V
Conditions Typ Max
Symbol Parameter CPU3 Unit

D1 (CPU1) D2 (CPU2) D3 (CPU3) VDD TJ = TJ = TJ = TJ = TJ = TJ = TJ = TJ =
clk
mode mode mode voltage 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
(MHz)
IDDCORE 16.5 105 180 295 58 290 430 710 mA

IDDCPU - 2.25 25.5 47 82.5 9.9 71 120 200 mA
IDDGPU(1) 4.95 40 69.5 115 21 120 170 290 mA
VDD =
2.6 2.65 2.7 2.8 3.2 3.3 3.4 3.6 mA

3.3 V(2)
IDD
Supply current in DStop1 Stop1 SSTop1 VDD =
- 1.2 1.2 1.25 1.3 1.5 1.5 1.6 1.7 mA
Stop1 mode (CStop) (CStop) (CStop)
1.8 V(3)
IDDA18 - 1.2 1.3 1.35 1.4 1.8 1.9 2 2.2 mA
VDD =
250 270 275 285 320 330 340 390 μA
3.3 (2)
IDDA18AON
VDD =
280 300 305 315 370 370 380 430 μA
1.8 V(3)
IDDCORE 24 110 185 305 67 290 440 710 mA
IDDCPU - -(6) -
IDDGPU(1) -(6) -
VDD =
2.65 2.7 2.7 2.8 3.2 3.3 3.4 3.5 mA
3.3 V(2)
IDD
HSI 64 VDD =
1.25 1.25 1.25 1.3 1.5 1.5 1.6 1.6 mA
1.8 V(3)
Supply current in DStandby(4) (5) Stop2 SRun2
IDDA18 Stop2 mode (CStandby) (CStop) (CRun) - 1.2 1.35 1.4 1.5 1.8 2 2.2 3 mA
VDD =
250 265 275 285 320 320 340 380 μA
3.3 V(2)
IDDA18AON
VDD =
280 295 305 315 370 370 380 430 μA
1.8 V(3)
IDDCORE 24 110 185 305 67 290 440 710 mA
page 122/234
MSI 4 -
IDDCPU -(6) -
DS14284 - Rev 2
Conditions Typ Max

clk
(MHz)
IDDGPU(1) - -(6) -
VDD =
2.65 2.7 2.7 2.8 3.2 3.3 3.4 3.5 mA
3.3 V(2)
IDD
VDD =
1.25 1.25 1.25 1.3 1.5 1.5 1.6 1.6 mA
Supply current in DStandby(4) (5) Stop2 SRun2 1.8 V(3)

MSI 4
Stop2 mode (CStandby) (CStop) (CRun)
IDDA18 - 1.2 1.35 1.4 1.5 1.8 2 2.2 3 mA
VDD =
250 265 275 285 320 320 340 380 μA
3.3 V(2)
IDDA18AON
VDD =
280 295 305 315 370 370 380 430 μA
1.8 V(3)
IDDCORE 23 110 185 300 66 290 440 710 mA
IDDCPU - -(6) -
IDDGPU(1) -(6) -
VDD =
2.65 2.7 2.7 2.8 3.2 3.3 3.4 3.5 mA
3.3 V(2)
IDD
HSI 64 VDD =
1.25 1.25 1.25 1.3 1.5 1.5 1.6 1.6 mA
1.8 V(3)
IDDA18 - 1.2 1.35 1.4 1.5 1.8 2 2.2 3 mA
VDD =
250 265 275 285 320 320 340 380 μA
DStandby 3.3 V(2)
IDDA18AON Supply current in Stop2 SRun2
Stop2 mode (CStandby)(4)(5) (CStop) (CSleep) VDD =
280 295 305 315 370 370 380 430 μA
1.8 V(3)
IDDCORE 23 110 185 300 66 290 440 710 mA
IDDCPU - -(6) -
IDDGPU(1) -(6) -
MSI 4 VDD =
2.65 2.7 2.7 2.8 3.2 3.3 3.4 3.5 mA
3.3 V(2)
IDD
VDD =
1.25 1.25 1.25 1.3 1.5 1.5 1.6 1.6 mA
page 123/234
1.8 V(3)
IDDA18 - 1.2 1.35 1.4 1.5 1.8 2 2.2 3 mA
DS14284 - Rev 2
Conditions Typ Max

clk
(MHz)
VDD =
250 265 275 285 320 320 340 380 μA
Supply current in DStandby Stop2 SRun2 3.3 V(2)
IDDA18AON MSI 4
Stop2 mode (CStandby)(4)(5) (CStop) (CSleep) VDD =
280 295 305 315 370 370 380 430 μA
1.8 V(3)
IDDCORE 16.5 105 175 295 58 290 430 700 mA

IDDCPU - -(6) -
IDDGPU (1)
-(6) -
VDD =
2.65 2.7 2.7 2.8 3.2 3.3 3.4 3.5 mA
3.3 V(2)
IDD
Supply current in DStandby Stop2 SSTop1 VDD =
- 1.25 1.25 1.25 1.3 1.5 1.5 1.6 1.6 mA
Stop2 mode (CStandby)(4)(5) (CStop) (CStop)
1.8 V(3)
IDDA18 - 1.2 1.35 1.4 1.5 1.8 2 2.2 3 mA
VDD =
250 265 275 285 320 320 340 380 μA
3.3 V(2)
IDDA18AON
VDD =
280 295 305 315 370 370 380 430 μA
1.8 V(3)

2. typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V.
6. Supply is OFF.
page 124/234
Table 30. Current consumption in LPLV-Stop modes
DS14284 - Rev 2

VDDGPU = 0.839 V.
Conditions Typ Max
Symbol Parameter D3 (CPU3) Unit

D1 (CPU1) D2 (CPU2) (1) CPU3 clk VDD TJ = TJ = TJ = TJ = TJ = TJ = TJ = TJ =
mode mode (MHz) voltage 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
mode
IDDCORE 16 110 190 315 120 320 490 820 mA

IDDCPU - 2.25 25.5 47 82.5 9.9 71 120 200 mA
IDDGPU (3)
-(4) -
VDD =
2.95 5.5 7.85 12 4.6 11 15 35 mA

3.3 V(5)
IDD LPLV-
Supply current in DStop3(2) SStop2 VDD =
Stop1(2) - 1.6 4.1 6.45 10.5 3 8.7 14 34 mA
LPLV-Stop1 mode (CStop) (CStop)
(CStop) 1.8 V(6)
IDDA18 - -(4) -
VDD =
250 270 275 285 580 330 340 650 μA
3.3 V(5)
IDDA18AON
VDD =
280 300 305 320 630 370 390 680 μA
1.8 V(6)
IDDCORE 16 110 190 315 63 320 490 810 mA
IDDCPU - -(4) -
IDDGPU(3) -(4) -
VDD =
2.95 5.5 7.9 12 4.1 11 15 24 mA
3.3 V(5)
IDD
MSI 4 VDD =
1.6 4.15 6.45 10.5 2.6 8.8 14 22 mA
LPLV- 1.8 V(6)
Supply current in DStandby SRun3
Stop2(2)
IDDA18 LPLV-Stop2 mode (CStandby) (CRun) - -(4) -
(CStop)
VDD =
250 270 275 285 320 330 340 390 μA
3.3 V(5)
IDDA18AON
VDD =
280 300 305 320 370 370 390 460 μA
1.8 V(6)
IDDCORE 16 110 190 315 110 320 490 810 mA
page 125/234
LSE
-
IDDCPU 0.032768 -(4) -
DS14284 - Rev 2
Conditions Typ Max

mode
IDDGPU(3) - -(4) -
VDD =
2.9 5.45 7.8 12 4.5 11 15 35 mA
3.3 V(5)
IDD
VDD =
LPLV- 1.55 4.05 6.4 10.5 3 8.7 14 34 mA
Supply current in DStandby SRun3 LSE 1.8 V(6)

Stop2(2)
LPLV-Stop2 mode (CStandby) (CRun) 0.032768
IDDA18 (CStop) - -(4) -
VDD =
250 270 275 285 580 330 340 360 μA
3.3 V(5)
IDDA18AON
VDD =
280 300 305 320 520 370 390 440 μA
1.8 V(6)
IDDCORE 16 110 190 320 63 320 490 810 mA
IDDCPU - -(4) -
IDDGPU (3)
-(4) -
VDD =
2.95 5.55 7.9 12 4.1 11 15 24 mA
3.3 V(5)
IDD
MSI 4 VDD =
1.6 4.15 6.5 10.5 2.6 8.8 14 22 mA
1.8 V(6)
IDDA18 - -(4) -
VDD =
250 270 275 285 320 330 340 390 μA
LPLV- 3.3 V(5)
IDDA18AON Supply current in DStandby SRun3
Stop2(2)
LPLV-Stop2 mode (CStandby)(7) (CSleep) VDD =
(CStop) 280 300 305 320 370 370 390 460 μA
1.8 V(6)
IDDCORE 16 110 190 320 110 320 490 820 mA
IDDCPU - -(4) -
IDDGPU (3)
-(4) -
LSE VDD =
0.032768 2.9 5.45 7.8 12 4.5 11 15 36 mA
3.3 V(5)
IDD
VDD =
1.55 4.05 6.4 10.5 3 8.7 14 34 mA
page 126/234
1.8 V(6)
IDDA18 - -(4) -
DS14284 - Rev 2
Conditions Typ Max

mode
VDD =
LPLV- 250 270 275 285 580 330 340 360 μA
Supply current in DStandby SRun3 LSE 3.3 V(5)
IDDA18AON Stop2(2)
LPLV-Stop2 mode (CStandby)(7) (CSleep) 0.032768
(CStop) VDD =
280 300 305 320 340 370 390 440 μA
1.8 V(6)
IDDCORE 16 110 190 315 110 320 490 810 mA

IDDCPU - -(4) -
IDDGPU(3) -(4) -
VDD =
2.9 5.45 7.8 12 4.5 11 15 35 mA
3.3 V(5)
IDD
Supply current in DStandby LPLV-Stop2 SStop2 VDD =
- 1.55 4.05 6.4 10.5 3 8.7 14 34 mA
LPLV-Stop2 mode (CStandby)(7) (CStop)(2) (CStop)
1.8 V(6)
IDDA18 - -(4) -
VDD =
250 270 275 285 580 330 340 360 μA
3.3 V(5)
IDDA18AON
VDD =
280 300 305 320 520 370 390 440 μA
1.8 V(6)
1. Domain clocked by MSI 4 MHz.

2. Typical value given with VDDCORE = 0.67 V, maximum values given with VDDCORE = 0.71 V.
4. Supply is OFF.
5. Typical values given for VDD = 3.3 V, maximum values for VDD = 3.6 V.
page 127/234
Table 31. Current consumption in Standby1 mode
DS14284 - Rev 2

VDDCORE, VDDCPU and VDDGPU are shutdown.
Conditions Typ Max
Symbol Parameter D3 (CPU3) CPU3 clk TJ = TJ = TJ = TJ = TJ = TJ = TJ = TJ = Unit
VDD voltage
mode (MHz) 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
VDD = 3.3 V(1) 2.35 3.6 4.8 6.75 3.2 6.4 8.7 15 mA
IDD
VDD = 1.8 V(2) 960 2300 3400 5300 1800 4900 7100 13000 μA
Supply current in SRun3

IDDA18 MSI 4 - -(3) -
Standby1 mode (CRun)
VDD = 3.3 V(1) 31 41 55.5 60 79 93 130 140 μA
IDDA18AON
VDD = 1.8 V(2) 60 80 80 88.5 110 150 160 180 μA
VDD = 3.3 V(1) 2.15 3.55 4.7 6.65 3.4 6.4 8.6 15 mA
IDD
VDD = 1.8 V(2) 960 2150 3300 5200 1900 4800 6900 13000 μA
IDDA18 LSE 0.032768 - -(3) -
Standby1 mode (CRun)
VDD = 3.3 V(1) 29.5 41 55 60 78 94 130 140 μA
IDDA18AON
VDD = 1.8 V(2) 60 80 80 88 110 150 160 180 μA
VDD = 3.3 V(1) 2.25 3.4 4.45 6.2 3.3 6 8 15 mA

IDD
VDD = 1.8 V(2) 960 2050 3050 4750 1900 4400 6400 14000 μA
IDDA18 MSI 4 - -(3) -
Standby1 mode (CSleep)
VDD = 3.3 V(1) 31 41 55.5 60 79 91 130 140 μA
IDDA18AON
VDD = 1.8 V(2) 60 80 80 87.5 110 150 160 180 μA
VDD = 3.3 V(1) 2.1 3.35 4.4 6.15 3.4 6 7.9 15 mA

IDD
VDD = 1.8 V(2) 960 2000 3000 4700 1900 4300 6300 14000 μA
IDDA18 LSE 0.032768 - -(3) -
Standby1 mode (CSleep)
VDD = 3.3 V(1) 31 41.5 55 60 79 91 130 140 μA
IDDA18AON
VDD = 1.8 V(2) 60 80 80 87.5 110 150 160 180 μA
VDD = 3.3 V(1) 2.1 3.35 4.4 6.15 3.4 5.9 7.9 15 mA
IDD
VDD = 1.8 V(2) 960 2000 3000 4700 1900 4300 6400 14000 μA
Supply current in SStop2
page 128/234
-
IDDA18 Standby1 mode (CStop) - -(3) -
IDDA18AON VDD = 3.3 V(1) 31 41 55 60 79 93 130 140 μA

DS14284 - Rev 2
Conditions Typ Max

Symbol Parameter D3 (CPU3) CPU3 clk TJ = TJ = TJ = TJ = TJ = TJ = TJ = TJ = Unit
VDD voltage
mode (MHz) 25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
Supply current in SStop2
IDDA18AON - VDD = 1.8 V(2) 60 80 80 88 110 150 160 180 μA
Standby1 mode (CStop)
3. Supply is OFF.

page 129/234
Table 32. Current consumption in Standby2 mode
DS14284 - Rev 2

VDDCORE, VDDCPU and VDDGPU are shutdown.
D3 (CPU3) in CStop (SStandby).
Conditions Typ Max
Symbol Parameter TJ = TJ = TJ = TJ = TJ = TJ = TJ = TJ = Unit
RTC/LSE BKPSRAM RETRAM LPSRAM1 VDD voltage
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
OFF 2.45 4 5.55 8.25 3.2 7.4 11 17 mA

OFF
OFF 2.05 2.2 2.45 2.8 3.4 3.4 3.7 18 mA

OFF
Supply current in ON 2.05 2.3 2.5 2.9 3.3 3.3 3.8 18 mA
RTC ON, VDD = 3.3 V(1)
Standby2 mode ON 2.05 2.5 3.1 4.1 3.2 3.9 4.8 17 mA
LSE ON(2) OFF
OFF 2.05 2.3 2.5 2.9 3.3 3.3 3.8 18 mA
ON
ON ON 2.05 2.55 3.25 4.35 3.2 4.2 5.1 17 mA
IDD
OFF 960 2600 4100 6750 1800 5700 8500 15000 μA
OFF
OFF 560 955 1050 1400 1700 1900 1900 17000 μA
OFF
Supply current in ON 560 960 1150 1500 1700 1800 2300 16000 μA
RTC ON, VDD = 1.8 V(3)
Standby2 mode ON 575 1300 1750 2700 1700 2400 3200 15000 μA
LSE ON(2) OFF
OFF 560 955 1150 1500 1700 1800 2200 16000 μA
ON
ON ON 600 1350 1850 2950 1700 2600 3600 15000 μA
VDD = 3.3 V(1) 31.5 41 55.5 60 79 91 130 140 μA

OFF OFF OFF OFF
VDD = 1.8 V(3) 60 80 80 90.5 110 150 160 180 μA
Supply current in
IDDA18AON
Standby2 mode VDD = 3.3 V(1)
RTC ON, 30.5 41.5 56 60 79 93 130 140 μA
ON ON ON
LSE ON(2) VDD = 1.8 V(3) 60 80 80 86 110 150 160 190 μA
2. LSE is set to medium-high drive.
page 130/234
Table 33. Current consumption in VBAT1 mode
DS14284 - Rev 2

D3 (CPU3) in SRun3 (DRun).
Conditions Typ Max
RTC/LSE BKPSRAM RETRAM LPSRAM1 VBAT voltage
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
VBAT = 2.4 V 245 1300 2200 3650 590 3300 5300 8500
Supply current in VBAT1 VBAT = 3.0 V 250 1300 2200 3650 590 3300 5300 8500
RTC ON,
IBAT mode (D3 clocked by OFF OFF ON μA
LSE ON(1)

MSI 4 MHz) VBAT = 3.3 V 255 1300 2200 3650 590 3300 5400 8500
VBAT = 3.6 V 255 1350 2200 3700 600 3400 5400 8600
VBAT = 2.4 V 490 1550 2450 3900 840 3600 5600 8800
Supply current in VBAT1 VBAT = 3.0 V 495 1550 2450 3900 850 3600 5600 8800
RTC ON,
IBAT mode (D3 clocked by OFF OFF ON μA
LSE ON(1) VBAT = 3.3 V 495 1550 2450 3900 850 3600 5600 8800
MSI 16 MHz)
VBAT = 3.6 V 500 1600 2450 3950 850 3600 5600 8800
page 131/234
Table 34. Current consumption in VBAT2 mode
DS14284 - Rev 2

D3 (CPU3) in CStop (SStandby).
Conditions Typ Max
RTC/LSE BKPSRAM RETRAM LPSRAM1 VBAT voltage
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
OFF 14.5 37 47 56.5 20 69 150 210 μA

OFF
OFF 14.5 37.5 54.5 60.5 20 70 150 215 μA
OFF
ON 17.5 66.5 100 190 27 150 310 440 μA

Supply current in
IBAT RTC ON, VBAT = 2.4 V
VBAT2 mode ON 38.5 330 660 1250 82 780 1600 2900 μA
LSE ON(1) OFF
OFF 17 63.5 93.5 175 27 150 300 410 μA
ON
ON ON 44 385 770 1450 97 910 1800 3300 μA

OFF 17.5 40.5 49.5 58.5 23 73 150 215 μA
OFF
OFF 17.5 41 58 64.5 23 74 160 220 μA
OFF
Supply current in ON 20.5 69.5 105 195 31 150 310 440 μA
VBAT2 mode ON 41.5 335 665 1300 85 780 1600 2900 μA
LSE ON(1) OFF
OFF 20 66.5 97 180 30 150 310 420 μA
ON
ON ON 47 385 775 1500 100 910 1800 3300 μA
OFF 20 43.5 52 60 26 76 160 220 μA
OFF
OFF 20 43.5 61 67.5 25 76 160 230 μA
OFF
Supply current in ON 22.5 72.5 110 200 33 160 320 450 μA
VBAT2 mode ON 43.5 335 670 1300 87 780 1600 2900 μA
LSE ON(1) OFF
OFF 22.5 69.5 100 185 32 150 310 420 μA
ON
ON ON 49 390 775 1500 110 920 1800 3300 μA
OFF 24 47.5 58 67.5 30 92 190 260 μA
OFF
OFF 24.5 47.5 61 73 30 91 190 270 μA
OFF
Supply current in ON 27 87.5 135 240 37 170 350 490 μA
VBAT2 mode ON 48.5 350 690 1300 92 800 1600 2900 μA
LSE ON(1) OFF
OFF 26.5 84.5 125 225 37 170 340 470 μA
ON
ON ON 53.5 405 800 1500 110 930 1800 3400 μA

page 132/234
6.3.5.2 I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
6.3.5.3 I/O static current consumption

All the I/Os used as inputs with pull-up generate a current consumption when the pin is externally held low. The
value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in
Table 61. I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to estimate the current
consumption.
An additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is
externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate
the input value. Unless this specific configuration is required by the application, this supply current consumption
can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should
be configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of
external electromagnetic noise. To avoid a current consumption related to floating pins, they must either be
configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-
up/down resistors or by configuring the pins in output mode.
6.3.5.4 I/O dynamic current consumption

The I/Os used by an application contribute to the current consumption. When an I/O pin switches, it uses the
current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load
(internal or external) connected to the pin.
The theoretical formula is provided below:
ISW = VDD × fSW × CL
where
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDDx is the MCU supply voltage
• fSW is the I/O switching frequency
• CL is the total capacitance seen by the I/O pin: C = CINT + CEXT
6.3.6 Wakeup time from low-power modes

The wakeup times given in Table 35 , Table 36 and Section 6.3.6 are measured starting from the wakeup event
trigger up to the first instruction executed by the CPU1, CPU2 or CPU3:
• the CPU1, CPU2 or CPU3 goes in low-power mode after WFI (wait for interrupt) instruction.
• For CSleep modes:
– Interrupt to GIC or NVIC is used to wakeup from low-power modes.
• For CStop modes (except Standby and VBAT):
– For CPU1 and CPU2: EXTI1[x] is used to wakeup from low-power modes.
– For CPU3: EXTI2[x] is used to wakeup from low-power modes.
• For Standby modes:
– WKUPx is used to wakeup from low-power modes.
• For VBAT modes
– TAMP_INx is used to wakeup from low-power modes.
• System mode is equal to D2 domain mode
All timings are derived from tests performed under ambient temperature and VDD = 3.3 V.
General conditions unless otherwise noted:
• CPU1 software in SYSRAM
• CPU2 software in SRAMx
• CPU3 software in LPSRAMx
• HSE is 40 MHz
• When HSI is used, HSIKERON = 0
DS14284 - Rev 2 page 133/234

• PWRLP_DLY = 0
• LPLVDLY_D2 = 187 µs
• tWUCSleep values are measured with internal interrupt
• tWUCStop and tWULPLV-Stop values are measured with EXTI pin
• tWUStandby values are measured with WKUP pin through PWR
• When VDDCORE or VDDCPU are shutdown or reduces, wakeup time value depend on supply characteristics.
– Wakeup time in following tables are measured with 200 μs VDDCORE and VDDCPU setup time
– Longer VDDCPU or VDDCORE startup time than 200 μs should be added to the wakeup time value
– When voltage is reduced, VDDCORE is assumed to be back to nominal value before LPLVDLY_D2
expiration. Otherwise, LPLVDLY_D2 value should be increased accordingly and this directly impact
wakeup time value.
Table 35. D1 (CPU1) low-power mode wakeup timings

Evaluated by characterization, not tested in production. Unless otherwise noted.
D3
D1 (CPU1) D2 (CPU2) Conditions for wakeup
Symbol (CPU3) Typ Max Unit
mode mode domain
mode
CPU1 clock
SEV between CPU1 cores - 15
cycles
DRun Run1 12 + Tck_icn_nic +

(Reset) HSI -
(CSleep) (CStop) 20 Tck_cpu1_ext2f
tWUCSleep_CPU1
12 + Tck_icn_nic +
HSE + PLL1 -
20 TPLL1
DRun Run1 12 + Tck_icn_nic +

(Reset) HSE + PLL1 -
(eCSleep)(1) (CStop) 20 Tck_cpu1_ext2f
DStop1 Run1 HSI 64 MHz 8.2 10 µs

(Reset)
(CStop) (CRun) HSE + PLL1 1200 MHz 180 - µs
HSI 64 MHz(3) 3.3 15 µs

tWUCStop_CPU1 DStop1 Stop1
(Reset) HSI 64 MHz 8.2 10 µs
(CStop)(2) (CStop)(2)
HSE + PLL1 1200 MHz 180 - µs
DStandby Stop2
(Reset) HSI 64 MHz(3)(5) 660 - µs
(CStop)(4) (CStop)(2)
DStop3 LPLV-Stop1 HSI 64 MHz,
(Reset) 1000 1200 µs
tWULPLV- (CStop)(2)(6) (CStop)(2)(6) PWRLP_DLY = 100 us
Stop_CPU1 DStandby LPLV-Stop2 1500
(Reset) HSI 64 MHz(5) - µs(7)
(CStop)(4)(6) (CStop)(2)(6) (1000)
1. eCSleep mean CPU1 in enhanced CSleep with PLL1 automatically stopped (RCC_C1SREQSETR.ESLPREQ = 1). In this
mode, CPU1 wake on ck_cpu1_ext2f, then CPU1 switch back automatically to PLL1 after PLL lock time.
2. PDDS_Dx = 0.
3. HSI active (HSIKERON = 1).
4. PDDS_Dx = 1.
5. CPU1 wake‑up address register points to SYSRAM code.
6. LPDS_Dx=1 and LVDS_Dx = 1.
7. Value in parenthesis is for wakeup using WKUP pin through PWR.
Table 36. D2 (CPU2) low-power mode wakeup timings

Evaluated by characterization, not tested in production. Unless otherwise noted.
DS14284 - Rev 2 page 134/234

D3 (CPU3) Conditions for

Symbol D1 (CPU1) mode D2 (CPU2) mode Typ Max Unit
mode wakeup domain
CPU2
tWUCSleep_CPU2(1) DStop1 (CStop) Run1 (CSleep) (Reset) - - 14 clock
cycles
HSI 64 MHz - 1.2 µs
DRun (CRun) Run1 (CStop) (Reset) HSE + PLL
180 - µs
400 MHz
tWUCStop_CPU2 HSI 64 MHz(3) 2.7 6.2 µs
HSI 64 MHz 7.6 - µs

DStop1 (CStop)(2) Stop1 (CStop)(2) (Reset)
HSE + PLL
180 - µs
400 MHz
DStop3 (CStop)(2) LPLV-Stop1 HSI 64 MHz(5) 900 1200 µs

(Reset)
(4) (CStop)(2)(4) HSI 64 MHz(6) 1000 1300 µs
tWULPLV-Stop_CPU2
DStandby (CStop) LPLV-Stop2 1500
(4)(7) (Reset) HSI 64 MHz - µs
(CStop)(2)(4) (900)(8)
DStandby (CStop) HSI 64 MHz, 1700

tWUStandby_CPU2 (9) Standby2 (CStop)(9) (Reset)(9) - µs
RETRAM (800)(10)

2. PDDS_Dx = 0.
3. HSI active (HSIKERON = 1).
4. LPDS_Dx = 1 and LVDS_Dx = 1.
5. CPU2TMPSKP = 1 or PWRLP_DLY = 0.
6. CPU2TMPSKP = 0 and PWRLP_DLY = 100 µs.
7. PDDS_Dx = 1
8. Value in parenthesis is for wakeup using WKUP pin through PWR or wakeup using EXTI without simultaneous CPU1
wakeup.
9. PDDS_Dx = 1.
10. Value in parenthesis is for RAMCFG_RETRAMCCR1.CRCBS[2:0] = 0 (only 16 Kbytes RETRAM CRC check).
Table 37. Wakeup time using USART/LPUART

Symbol Parameter Conditions Typ Max Unit
tWUUSART Wakeup time needed to calculate the maximum USART/

Stop1/2
LPUART baud rate allowing the wakeup from low-power - 6.4 µs
tWULPUART HSI clock with HSIKERON = 0
mode
Wakeup time needed to calculate the maximum LPUART LPLV-Stop1/2

tWULPUART_LPLV - 580 µs
baud rate allowing the wakeup from low-power mode MSI clock with MSIKERON = 0
6.3.7 External clock source characteristics
6.3.7.1 High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard I/O.
Digital and analog bypass modes are available.
The external clock signal has to respect the Table 61. I/O static characteristics . However, the recommended clock
input waveform is shown in Figure 13 for digital bypass mode and in Figure 14 for analog bypass mode. In analog
bypass mode the clock can be a sinusoidal waveform.
DS14284 - Rev 2 page 135/234

Table 38. High-speed external (HSE) user clock characteristics (digital bypass)
fHSE_ext User external clock source frequency - - 16 40 48 MHz
VHSEH OSC_IN input pin high level voltage - - 0.7 × VDDA18AON - VDDA18AON
V
VHSEL OSC_IN input pin low level voltage - - VSS - 0.3 × VDDA18AON
tW(HSE) OSC_IN high or low time - - 7 - - ns
Figure 13. High-speed external clock source AC timing diagram (digital bypass)
VHSEH
90 %
10 %
VHSEL
tr(HSE) tW(HSE) t
tf(HSE) tW(HSE)
THSE
External fHSE_ext
IL
clock source OSC_IN
DT17528V1
STM32
Table 39. High-speed external (HSE) user clock characteristics (analog bypass)
User external clock source frequency - 16 40 48 MHz

fHSE_ext duty cycle (Square wave) - 45 50 55 %
duty cycle deterioration(1) - - ± 10(2) ±20(3) %
VHSE Absolute input range - 0 - VDDA18AON

V
VPP OSC_IN peak-to-peak amplitude - 0.2(4) - 0.67 × VDDA18AON
tSU(HSE) Time to start(5) - - 1 10(6) µs
Rise and Fall time

tr/tf(HSE) (10% to 90% threshold levels of the input peak-to- - 0.05 × THSE - 0.3 × THSE ns
peak amplitude)

2. With a square wave signal (@25 °C, VDDA18AON = 1.8 V / VPP = 400 mV / VDC = 0.8 V) where VDC is the DC component
of the input signal.
3. With a square wave signal (@25 °C, VDDA18AON = 1.71 V / VPP = 200 mV / VDC = 0.8 V) where VDC is the DC component
of the input signal.
4. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VDDA18AON - 0.1 V) where VDC is the DC component of the input
signal.
5. Startup time measured from the moment it is enabled (by software) to a stabilized analog bypass clock interface is reached.
6. Maximum start-up time is obtained with 200 mV peak-to-peak amplitude.
DS14284 - Rev 2 page 136/234

Figure 14. High-speed external clock source AC timing diagram (analog bypass)
VHSE
90%
VPP
10%
THSE tr(HSE) t
External
fHSE_ext OSC_IN
clock source IL
DT47498V1
STM32
6.3.7.2 Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard I/O. The external clock signal
has to respect the Table 61. I/O static characteristics . However, the recommended clock input waveform is shown
in Figure 15 for digital bypass and Figure 16 for analog bypass.
Table 40. Low-speed external (LSE) user clock characteristics (digital bypass)
fLSE_ext(1) User external clock source frequency - - 32.768 - kHz
VLSEH OSC32_IN input pin high level voltage - 0.75 × VSW - VSW(2)
V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.25 × VSW
tW(LSE) OSC32_IN high or low time - 250 - - ns

2. VSW is equal to VDD when present or VBAT otherwise.
Figure 15. Low-speed external clock source AC timing diagram (digital bypass)
VLSEH
90 %
10 %
VLSEL
t r(LSE) t W(LSE) t
t f(LSE) t W(LSE)
TLSE
External f LSE_ext
OSC32 _IN IL
clock source
DT17529V1
STM32
DS14284 - Rev 2 page 137/234

Table 41. Low-speed external (LSE) user clock characteristics (analog bypass)
fLSE_ext(1) User external clock source frequency - - 32.768 - kHz
VLSE Absolute input range - 0 - VSW(2)

V
VPP OSC32_IN peak-to-peak amplitude - 0.2(3) 1 -

3. Minimum peak-to-peak amplitude (@25 °C, 0.1 < VDC < VSW - 0.1 V) where VDC is the DC component of the input signal.
Figure 16. Low-speed external clock source AC timing diagram (analog bypass)
VLSE
VPP
TLSE t
External
fLSE_ext OSC32_IN
clock source IL
DT63037V1
STM32
6.3.7.3 High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 16 to 48 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph are based on characterization results obtained with typical external
components specified in Table 42 . In the application, the resonator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table 42. High-speed external (HSE) oscillator characteristics

fHSE (1)
Crystal frequency - 16 40 48 MHz
RF(1) Internal feedback equivalent resistor - - 250 - kΩ
During startup - - 10
IVDDA18AON(HSE) HSE current consumption on VDDA18AON mA
Rm = 80 Ω, CL = 6 pF at 40 MHz(3) - 4.6 -
Gmcritmax(1) Maximum critical crystal gm Startup - - 2.5 mA/V
tSU Start-up time(4) - - 2 - ms

2. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
3. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
DS14284 - Rev 2 page 138/234

4. Measured from the moment it is enabled (by software) to a stabilized 40 MHz oscillation is reached. This value is measured
for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 10 pF range
(typical), designed for high-frequency applications, and selected to match the requirements of the crystal or
resonator (see Figure 17 ). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a
load capacitance which is the series combination of CL1 and CL2. The PCB and pin capacitance must be included
(4 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for
STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.
Figure 17. Typical application with a 40 MHz crystal
CL1
OSC_IN fHSE
Bias
40 MHz
RF controlled
crystal
gain
DT63062V1
OSC_OUT
STM32
CL2
6.3.7.4 Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the
information given in this paragraph are based on characterization results obtained with typical external
components specified in Table 43 . In the application, the resonator and the load capacitors have to be placed as
close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to
the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package,
accuracy).
Table 43. Low-speed external (LSE) oscillator characteristics

fLSE(1) Oscillator frequency - - 32.768 - kHz
LSEDRV[1:0] = 00,
- - 0.5
Low drive capability
LSEDRV[1:0] = 10,
- - 0.75
Medium Low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 01,
- - 1.7
Medium high drive capability
LSEDRV[1:0] = 11,
- - 2.7
High drive capability
tSU(2) Startup time VSW is stabilized - 2 - s

2. tSU is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Note: For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for
STM8AF/AL/S, STM32 MCUs and MPUs" available from the ST website www.st.com.
DS14284 - Rev 2 page 139/234

Figure 18. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors CL1
OSC32_IN fLSE
Bias
32.768 kHz
RF controlled
resonator
gain
DT17531V2
OSC32_OUT
STM32
CL2
1. Adding an external resistor between OSC32_IN and OSC32_OUT is forbidden.
6.3.8 External clock source security characteristics
Table 44. High-speed external user clock security system (HSE CSS)
tDCM(HSE_CSS) Time to detect clock missing fHSE = 48 MHz - 1 2 μs
Table 45. Low-speed external user clock security system (LSE CSS)
tDCM(LSE_CSS) Time to detect clock missing - - - 300 μs
fMAX(LSE_CSS) Cut-off frequency - - - 2 MHz
6.3.9 Internal clock source characteristics

The parameters given in Table 46 , Table 47 and Table 48 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17. General operating conditions .
6.3.9.1 64 MHz high-speed internal RC oscillator (HSI)
Table 46. HSI oscillator characteristics

fHSI(1) HSI frequency VDDA18AON = 1.8 V, TJ = 30 °C 63.68 64 64.32 MHz
TRIM HSI trimming step - - 0.25 0.5 %

DuCy(HSI) Duty Cycle - 40 - 60 %
∆VDDA18AON(HSI) + HSI oscillator frequency drift over

voltage and temperature variation (after TJ = -40 to 125 °C -4 - +4 %
∆TJ(HSI)
factory calibration)
HSI oscillator start-up time
tsu(HSI) (Time between Enable rising and First - - - 3 μs
output clock edge.)
tstab(HSI) HSI oscillator stabilization time At 1% of target frequency - - 5 μs
IVDDCORE(HSI) HSI supply current on VDDCORE - - - 10 μA
IVDD18AON(HSI) HSI supply current on VDDA18AON - - 300 400 μA
DS14284 - Rev 2 page 140/234

6.3.9.2 4/16 MHz low-power internal RC oscillator (MSI)
Table 47. MSI oscillator characteristics

MSIFREQSEL=0(1) 3.956 4 4.044

fMSI CSI frequency VDDCORE = 0.82 V, TJ = 30 °C MHz
MSIFREQSEL=1 15.824 16 16.176
Trimming Code is not a multiple of 32 - 0.8 1.1
TRIM MSI trimming step %
Trimming Code is a multiple of 32 - -2.5 -3.8
DuCy(MSI) Duty Cycle At trimmed frequency 45 - 55 %
TJ = -40 °C to 70 °C -5 - +5
MSI oscillator frequency
∆TJ(MSI) %
drift over temperature TJ = -40 °C to 125 °C -6 - +6
tsu(MSI) MSI oscillator start-up time - - - 3.5 μs
MSI Supply current on at 4 MHz MSIFREQSEL = 0 - 20 22

IVDDCORE(MSI) μA
VDDCORE at 16 MHz MSIFREQSEL = 1 - 60 68
6.3.9.3 32 kHz low-speed internal (LSI) RC oscillator
Table 48. LSI oscillator characteristics

TJ = 30 °C(1) 30.5 32 33.5

fLSI LSI Frequency kHz
TJ= -40 to 125° C 28.8 32 33.6
LSI oscillator start-up time (time between enable rising and first output
tsu(LSI) - - - 180 μs
clock edge.)
IVSW(LSI) LSI supply current on VSW(2) - - 250 500 nA

6.3.10 PLL characteristics

The parameters given in Table 49 , Table 50 , Table 51 and Table 52. PLL_LVDS characteristics are derived from
tests performed under temperature and supply voltage conditions summarized in Table 17. General operating
conditions .
Table 49. PLL1 to PLL8 characteristics

Specified by design, not tested in production unless otherwise specified.
Normal mode 5 - 64
fPLL_IN PLL input clock MHz
Sigma delta mode 10 - 64
fPLL_IN/
Normal mode 5 50
FREFDIV
fPFD PFD input clock MHz
min(50,
Sigma delta mode 10 -
fVCO/20)
fFOUTPOSTDIV Divided output clock - 16.32 - 3200 MHz
DS14284 - Rev 2 page 141/234

Division by 1 48 50 52
fFOUTPOSTDIV Divided output clock
Even Division 48 50 52 %
duty cycle
Odd Division 47 50 53
fVCO PLL VCO output - 800 - 3200 MHz
1/fPFD
Frequency lock - - 400
cycles
tLOCK PLL lock time
fPFD = 40 MHz (fPLL_IN = 40 MHz,
- - 10 μs
FREFDIV = 1)
RMS period jitter fVCO = 3200 MHz - - 0.26 +/_ps

Jitter RMS integrated jitter fVCO = 3200 MHz, Integer divider - ±2.7 ±6.6
ps
(10 kHz ‑ 20 MHz) FPFD = 25 MHz fracN divider - - ±11.9
FBDIV < 256 - 5750 6850
PLL supply current on fVCO = 3200 MHz
IVDDA18PLL(1) FBDIV > 255 - 7050 8450
VDDA18PLL (Analog)
fVCO = 800 MHz FBDIV < 256 - 715 860 μA
IVDDCORE(PLL) PLL supply current on fVCO = 3200 MHz - 1200 3650

VDDCORE = 0.82 V
(1) VDDCORE (Digital) fVCO = 800 MHz - 295 910
1. Evaluated by characterization, not tested in production.
Table 50. PLL_USB characteristics

fPLL_IN PLL input clock Only those 3 values (min, typ or max) are possible 19.2 20 38.4 MHz
fPLL_OUT PLL output clock - - 480 - MHz
Table 51. PLL_DSI characteristics

fPLL_IN PLL input clock - - 2 - 64
fPLL_INFIN PFD input clock - - 2 - 24

MHz
fPLL_OUT PLL output clock - - 40 - 1250
fVCO_OUT PLL VCO output - - 320 - 1250
tLOCK PLL lock time(1) - - - - 150

μs
tPDN PLL power down time - - 0.1 - -
Table 52. PLL_LVDS characteristics

fPLL_IN PLL input clock - - 3 - 24
fPLL_INFIN PFD input clock - - 3 - 24 MHz

fPLL_OUT PLL output clock - - - - 1100
DS14284 - Rev 2 page 142/234

fVCO_OUT PLL VCO output - - 1800 2200 3000 MHz
tLOCK (1)
PLL lock time - - - - 355 μs
fMod Modulation frequency - - - 33 - kHz
md Modulation depth - - - 0.25 5 %
IVDDA18LVD S(1) PLL supply current on VDDA18LVDS - - - 4.9 - mA
IVDDLVDS(1) PLL supply current on VDDLVDS - - - 1.4 - mA
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics

The spread spectrum clock generation (SSCG) feature allows the reduction of electromagnetic interferences (see
Section 6.3.13.4 ). It is available only on the PLL2 to PLL8.
Table 53. PLL2 to PLL8 SSCG parameters constraints

FMOD Modulation frequency 5.2 - 391 kHz
MD Peak modulation depth 0.1 - 3.1 %
6.3.12 Memory characteristics
6.3.12.1 OTP characteristics

The characteristics are given at TJ = -40 to 125 °C unless otherwise specified.
Table 54. OTP characteristics

Programming - 3.8 10
mA
IOTP(VDDA18AON) OTP supply current on VDDA18AON Reading - 0.66 1.13
PowerDown - 5 132 μA
Programming - 0.09 0.45
mA
IOTP(VDDCORE) OTP supply current on VDDCORE Reading - 1.8 3.6
PowerDown - 8 500 μA
6.3.13 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
6.3.13.1 Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed
by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional
disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: a burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF
capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
DS14284 - Rev 2 page 143/234

The test results are given in Table 55 . They are based on the EMS levels and classes defined in application note
AN1709 available from the ST website www.st.com.
Table 55. EMS characteristics

Evaluated by characterization, not tested in production.
Level/
Symbol Parameter Conditions
Class
Voltage limits to be applied on any I/O pin to

VFESD VDD = 3.3 V, TA = +25 °C, TFBGA436 package, 2B
induce a functional disturbance
FPLL1 = 1200 or 1500 MHz, Fck_icn_hs_mcu = 400 MHz,
Fast transient voltage burst limits to be Cortex‑M33/Cortex‑M0+ cores not running, conforms to
VFTB applied through 100 pF on VDD and VSS IEC 61000-4-2 5A
pins to induce a functional disturbance
As a consequence, it is recommended to add a serial resistor (1 kΩ) located as close as possible to the device
pins exposed to noise (connected to tracks longer than 50 mm on PCB).
6.3.13.2 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment
and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user
application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation
with the EMC level requested for his application.
6.3.13.3 Software recommendations

The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter
• Unexpected reset
• Critical Data corruption (such as control registers)
See also application note AN1015.
6.3.13.4 Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application, executing EEMBC code,
is running. This emission test is compliant with SAE IEC61967-2 standard which specifies the test board and the
pin loading.
Table 56. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1200 MHz
Monitored
Symbol Parameter Conditions Value Unit
frequency band
0.1 MHz to 30 MHz 14

30 MHz to 130 MHz 9
Peak(1) VDD = 3.6 V, TA = 25 °C, TFBGA436 package, dBµV
SEMI Fck_icn_hs_mcu = 400 MHz, Cortex‑M33/Cortex‑M0+ cores not 130 MHz to 1 GHz 21
running, conforming to IEC61967-2
1 GHz to 2 GHz 8
Level(2) 0.1 MHz to 2 GHz 3 -
1. Refer to AN1709 "EMI radiated test" section.

2. Refer to AN1709 "EMI level classification" section.
DS14284 - Rev 2 page 144/234

Table 57. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1500 MHz
Monitored
Symbol Parameter Conditions Value Unit
frequency band
0.1 MHz to 30 MHz -

30 MHz to 130 MHz -
Peak(1) VDD = 3.6 V, TA = 25 °C, TFBGA436 package, dBµV
SEMI Fck_icn_hs_mcu = 400 MHz, Cortex‑M33/Cortex‑M0+ cores not 130 MHz to 1 GHz -
running, conforming to IEC61967-2
1 GHz to 2 GHz -
Level(2) 0.1 MHz to 2 GHz - -
1. Refer to AN1709 "EMI radiated test" section.

2. Refer to AN1709 "EMI level classification" section.
6.3.14 Absolute maximum ratings (electrical sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to
determine its performance in terms of electrical sensitivity.
6.3.14.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse) are applied to the pins of each sample according to
each pin combination. This test conforms to the ANSI/ESDA/JEDEC JS-001 and ANSI/ESDA/JEDEC JS-002
standards.
Table 58. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Packages Class Unit
value
Electrostatic discharge voltage TA = +25 °C conforming to ANSI/

VESD(HBM) All 2 2000 V
(human body model) ESDA/JEDEC JS-001
Electrostatic discharge voltage TA = +25 °C conforming to ANSI/

VESD(CDM) All C1 250 V
(charge device model) ESDA/JEDEC JS-002
6.3.14.2 Static latchup

Two complementary static tests are required on three parts to assess the latchup performance:
• A supply overvoltage is applied to each power supply pin
• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with JESD78 IC latchup standard.
Table 59. Electrical sensitivities

Symbol Parameter Conditions Class
LU Static latchup class TA = +25 °C conforming to JESD78 II level A
6.3.15 I/O current injection characteristics

As a general rule, a current injection to the I/O pins, due to external voltage below VSS or above VDD should be
avoided during the normal product operation. However, in order to give an indication of the robustness of the
device in cases when an abnormal injection accidentally happens, susceptibility tests are performed on a sample
basis during the device characterization.
DS14284 - Rev 2 page 145/234

6.3.15.1 Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins
programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked
for functional failures.
The failure is indicated by an out of range parameter:
• ADC error above a certain limit: higher than 5 LSB total unadjusted error (TUE),
• Out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range)
• Other functional failure (for example reset, oscillator frequency deviation).
The following tables are the compilation of the SIC1/SIC2 and functional ESD results.
Negative induced A negative induced leakage current is caused by negative injection and positive induced
leakage current by positive injection.
Table 60. I/O current injection susceptibility

Symbol Description Negative Injection Positive Injection Unit
ANA0, ANA1 5 0
OSC32_IN, OSC32_OUT, PC13, PI8, PZ0, PZ1, PZ2, PZ3, PZ4,
IINJ 0 NA mA
PZ5, PZ6, PC3, PC4, PC5, PF6, PF7, PG1, PG3

All other digital I/Os 5 NA
6.3.16 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 61. I/O static characteristics are derived from tests
performed under the conditions summarized in Table 17. General operating conditions . All I/Os are CMOS and
TTL compliant.
Table 61. I/O static characteristics

Symbol Parameter Condition Min Typ Max Unit
2.7 < VDDx < 3.6 V - - 0.3 × VDDx V

VIL(1) I/O input low voltage
1.71 <VDDx < 1.89 V - - 0.35 × VDDx V
2.7 < VDDx < 3.6 V 0.7 × VDDx - - V

VIH(1) I/O input high voltage
1.71 < VDDx < 1.89 V 0.65 × VDDx - - V
2.7 < VDDx < 3.6 V - - 0.4 × VDDx - 0.27 V

VIL(2) I/O input low voltage
1.71 < VDDx < 1.89 V - - 0.36 × VDDx V
2.7 <VDDx < 3.6 V 0.52 × VDDx - 0.11 - - V

VIH(2) I/O input high voltage
1.71 < VDDx < 1.89 V 0.62 × VDDx - - V
2.7 < VDDx < 3.6 V - 0.44 - V

VHYS I/O input hysteresis
1.71 <VDDx < 1.89 V - 0.44 - V
Ileak TT_x input leakage - 50 1000 nA
IVDDx Static current consumption on VDDx - 40 2000 nA
IVDDA18AON Static current consumption on VDDA18AON - 2 80 nA
IVDDCORE Static current consumption on VDDCORE - 1 180 nA
2.7 < VDDx < 3.6 V 30 40 50 kΩ

RPU Weak pull-up equivalent resistor(3)
1.71 < VDDx < 1.89 V 30 40 50 kΩ
DS14284 - Rev 2 page 146/234

Symbol Parameter Condition Min Typ Max Unit
2.7 < VDDx < 3.6 V 30 40 50 kΩ

RPD Weak pull-down equivalent resistor(3)
1.71 < VDDx < 1.89 V 30 40 50 kΩ
CIO I/O pin capacitance - - 5 - pF
1. Guaranteed by testing.
3. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than
the strict CMOS-technology or TTL parameters. The coverage of these requirements for TT I/Os is shown in
Figure 19 .
Figure 19. VIL/VIH for TT I/Os
3.6
3.4
3.2
2.8
VIHmin tested in production
2.6
2.4
2.2
2
VIHmin based on simulations
1.8
1.6
1.4 VIHmin tested in production

VILmax based on simulations
1.2
VIHmin based on simulations
1
0.8 VILmax based on simulations VILmax tested in production
0.6
VILmax tested in production
0.4
0.2
0
DT74105V1
1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6
VILmax tested in production VILmax based on simulations VIHmin tested in production VIHmin based on simulations
6.3.16.1 Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±20 mA (depending on speed setup, supply
voltage range and temperature).
In the user application, I/O drive current must be limited to respect the absolute maximum rating specified in
Section 6.2 , in particular:
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run mode consumption of the
MCU sourced on VDD, cannot exceed the absolute maximum rating ΣIVDD (see Table 15 ).
• The sum of the currents sunk by all the I/Os on VSS plus the maximum Run mode consumption of the MCU
sunk on VSS cannot exceed the absolute maximum rating ΣIVSS (see Table 15 ).
6.3.16.2 Output voltage levels

Unless otherwise specified, the parameters given in Table 62 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 17. General operating conditions . All I/Os are
CMOS and TTL compliant.
DS14284 - Rev 2 page 147/234

Table 62. Output voltage characteristics for all I/Os

Symbol Parameter Conditions(1) (2) (3) (4) Min Max Unit
IIO = 6.5 mA, Speed = 0b00 - 0.4
IIO = 10 mA, Speed = 0b01 - 0.4

VOL Output low level voltage (3.3 V range, 2.7 < VDDx < 3.6 V) V
IIO = 13 mA, Speed = 0b10 - 0.4
IIO = 20 mA, Speed = 0b11 - 0.4
IIO = 6.5 mA, Speed = 0b00 VDDx - 0.4 - V
IIO = 10 mA, Speed = 0b01 VDDx - 0.4 - V

VOH Output high level voltage (3.3 V range, 2.7 < VDDx < 3.6 V)
IIO = 5.5 mA, Speed = 0b00 - 0.4 V
IIO = 8 mA, Speed = 0b01 - 0.4 V

VOL Output low level voltage (1.8 V range, 1.71 < VDDx < 1.89 V)
IIO = 11 mA, Speed = 0b10 - 0.4 V
IIO = 16 mA, Speed = 0b11 - 0.4 V
IIO = 5.5 mA, Speed = 0b00 VDDx - 0.4 - V
IIO = 8m A, Speed = 0b01 VDDx - 0.4 - V

VOH Output high level voltage (1.8 V range, 1.71 < VDDx < 1.89 V)
1. 110 <TJ < 120: 4 mA.

2. 90 < TJ < 110: 10 mA.
3. TJ < 90: 20 mA.
4. Maximum current depend on temperature.
6.3.16.3 Output buffer timing characteristics
Table 63. Output timing characteristics (VDD = 3.0 - 3.6 V or VDDIOx = 2.7 - 3.6 V, VDDIOxVRSEL = 0)
Speed Symbol Parameter Conditions Min Max Unit
C = 50 pF - 30
C = 40 pF - 35
Fmax(1) Maximum frequency C = 30 pF - 45 MHz

C = 20 pF - 67
C = 10 pF - 110
0b00
C = 50 pF - 11.7
C = 40 pF - 9.5
Output high to low level
Tr/Tf(2) fall time and output low C = 30 pF - 7.3 ns
to high level rise time
C = 20 pF - 5.2
C = 10 pF - 3
C = 50 pF - 45
0b01 Fmax(1) Maximum frequency C = 40 pF - 55 MHz

C = 30 pF - 70
DS14284 - Rev 2 page 148/234

C = 20 pF - 100
Fmax(1) Maximum frequency MHz
C = 10 pF - 166
C = 50 pF - 8.1
0b01 C = 40 pF - 6.7
C = 20 pF - 3.6
C = 10 pF - 2.2
C = 50 pF - 60
C = 40 pF - 75

C = 20 pF - 133
C = 10 pF - 190
0b10(3)
C = 50 pF - 6.3
C = 40 pF - 5.1
Tr/Tf(2) fall time and output low C = 30 pF - 4 ns
C = 20 pF - 2.9
C = 10 pF - 1.8
C = 50 pF - 80
C = 40 pF - 100

C = 20 pF - 166
C = 10 pF - 220
0b11(3)
C = 50 pF - 4.4
C = 40 pF - 3.7
C = 20 pF - 2.2
C = 10 pF - 1.5
1. The maximum frequency is defined with the following conditions : (Tr + Tf) ≤ 2/3 T and Skew ≤ 1/20 T and
45% < Duty cycle < 55%.
2. The fall and rise time are defined respectively between 90% and 10%, and between 10% and 90% of the output waveform.
3. IO compensation enabled.
Table 64. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 1)

C = 50 pF - 30
C = 40 pF - 35
0b00 C = 20 pF - 67
C = 10 pF - 110
Output high to low level C = 50 pF - 11
Tr/Tf(2) fall time and output low ns
C = 40 pF - 9
DS14284 - Rev 2 page 149/234

Output high to low level C = 30 pF - 7

0b00 Tr/Tf(2) fall time and output low C = 20 pF - 5 ns
C = 10 pF - 3
C = 50 pF - 45
C = 40 pF - 55

C = 20 pF - 100
C = 10 pF - 166
0b01
C = 50 pF - 7.4
C = 40 pF - 6.1
C = 20 pF - 3.4
C = 10 pF - 2.1
C = 50 pF - 60
C = 40 pF - 75

C = 20 pF - 133
C = 10 pF - 200
0b10(3)
C = 50 pF - 5.7
C = 40 pF - 4.7
C = 20 pF - 2.7
C = 10 pF - 1.7
C = 50 pF - 80
C = 40 pF - 100

C = 20 pF - 166
C = 10 pF - 250
0b11(3)
C = 50 pF - 4.1
C = 40 pF - 3.4
C = 20 pF - 2
C = 10 pF - 1.3
45% < Duty cycle < 55%.
Table 65. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 0 degraded mode)
0b00 Fmax(1) Maximum frequency C 50 pF - 10 MHz
DS14284 - Rev 2 page 150/234

C = 40 pF - 15
C = 30 pF - 20
Fmax(1) Maximum frequency MHz
C = 20 pF - 33
C = 10 pF - 45
0b00 C = 50 pF - 30.2
C = 40 pF - 24.4
C = 20 pF - 13
C = 10 pF - 7.4
C = 50 pF - 15
C = 40 pF - 20

C = 20 pF - 37
C = 10 pF - 60
0b01
C = 50 pF - 21.1
C = 40 pF - 17.2
C = 20 pF - 9.4
C = 10 pF - 5.5
C = 50 pF - 20
C = 40 pF - 25

C = 20 pF - 45
C = 10 pF - 75
0b10(3)
C = 50 pF - 17
C = 40 pF - 13.9
C = 20 pF - 7.8
C = 10 pF - 4.5
C = 50 pF - 30
C = 40 pF - 35

C = 20 pF - 60
C = 10 pF - 85
0b11(3)
C = 50 pF - 11.8
C = 40 pF - 9.8
C = 20 pF - 5.8
C = 10 pF - 3.8
45% < Duty cycle < 55%.
DS14284 - Rev 2 page 151/234

Table 66. GPIO advance config delay characteristics

tinit Initial delay - 0 - 0.05

ps
t∆ Unit Delay - - 0.25 -
6.3.17 NRST pin characteristics

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see
Table 61. I/O static characteristics).
Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 17. General operating conditions .
Table 67. NRST pin characteristics

RPU(1) Weak pull-up equivalent resistor - 30 40 50 kΩ
tGEN NRST minimum generated output pulse - 17.5 - - μs

TFILT NRST input filtered pulse - - - 50 ns
TNFILT NRST input not filtered pulse - 150 - - ns
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
Figure 20. Recommended NRST pin protection
VDD
External
reset circuit(1)
RPU
NRST(2) Internal reset
Filter
0.1 µF
DT14132V1
STM32
1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 67 . Otherwise the reset is not taken into account by the device.
6.3.18 DDR IOs characteristics

Refer to JEDEC standards for more details and characteristics
• DDR3L: JESD79-3F with addendum JESD79-3-1A
• DDR4: JESD79-4D
• LPDDR4: JESD209-4D
DS14284 - Rev 2 page 152/234

6.3.19 FMC characteristics

Unless otherwise specified, the parameters given in Table 68 to Table 81. NAND flash write timings for the FMC
interface are derived from tests performed under the ambient temperature and VDD supply voltage conditions
summarized in Table 17. General operating conditions , with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 11
• Measurement points are done at CMOS levels: 0.5 × VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output characteristics.
6.3.19.1 Asynchronous waveforms and timings

Figure 21 through Figure 24 represent asynchronous waveforms and Table 68 through Table 75 provide the
corresponding timings. The results shown in these tables are obtained with the following FMC configuration:
• AddressSetupTime = 0x1
• AddressHoldTime = 0x1
• DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5)
• DataHoldTime = 0x1 (1 × Tfmc_ker_ck for read operations and 2 × Tfmc_ker_ck for write operations)
• ByteLaneSetup = 0x1
• BusTurnAroundDuration = 0x0
• Capacitive load CL = 30 pF
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings

tw(NE) FMC_NE low time 3Tfmc_ker_ck - 1 - 3Tfmc_ker_ck + 0.5
tv(NOE_NE) FMC_NEx low to FMC_NOE low 0 - 1
tw(NOE) FMC_NOE low time 2Tfmc_ker_ck - 1 - 2Tfmc_ker_ck + 1
th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck - 0.5 - -
tv(A_NE) FMC_NEx low to FMC_A valid - - 1
th(A_NOE) Address hold time after FMC_NOE high Address held until next read operation
ns
tsu(Data_NE) Data to FMC_NEx high setup time 2Tfmc_ker_ck + 14 - -
tsu(Data_NOE) Data to FMC_NOEx high setup time 15 - -
th(Data_NOE) Data hold time after FMC_NOE high 0 - -
th(Data_NE) Data hold time after FMC_NEx high 0 - -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - - 0.5
tw(NADV) FMC_NADV low time - - Tfmc_ker_ck + 0.5
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings

NWAIT pulse width is equal to 1 clock cycle.
tw(NE) FMC_NE low time 8Tfmc_ker_ck - 0.5 - 8Tfmc_ker_ck + 0.5
tw(NOE) FMC_NWE low time 7Tfmc_ker_ck - 0.5 - 7Tfmc_ker_ck + 0.5
tw(NWAIT) FMC_NWAIT low time Tfmc_ker_ck - - ns
tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5Tfmc_ker_ck + 15 - -
th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4Tfmc_ker_ck + 13 - -
DS14284 - Rev 2 page 153/234

Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) tw(NOE) th(NE_NOE)
FMC_NOE
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NOE)
FMC_NBL[1:0]
th(Data_NE)
tsu(Data_NOE) th(Data_NOE)
tsu(Data_NE)
FMC_D[15:0] Data
tv(NADV_NE)
tw(NADV)
FMC_NADV (1)
FMC_NWAIT
DT32753V1
th(NE_NWAIT)
tsu(NWAIT_NE)
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings

tw(NE) FMC_NE low time 3Tfmc_ker_ck - 1 - 3Tfmc_ker_ck + 1
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 - Tfmc_ker_ck + 0.5
tw(NWE) FMC_NWE low time Tfmc_ker_ck - 0.5 - Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - 0.5 - -
th(A_NWE) Address hold time after FMC_NWE high 3Tfmc_ker_ck - 1 - -

ns
tv(BL_NE) FMC_NEx low to FMC_BL valid - - 0.5
th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck + 1 - -
tv(Data_NE) Data to FMC_NEx low to Data valid - - 2
th(Data_NWE) Data hold time after FMC_NWE high 3Tfmc_ker_ck - 1 - -
tv(NADV_NE) FMC_NEx low to FMC_NADV low - - 0.5
tw(NADV) FMC_NADV low time - - Tfmc_ker_ck + 1
DS14284 - Rev 2 page 154/234

Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings

NWAIT pulse width is equal to 1 clock cycle.
tw(NWE) FMC_NWE low time 6Tfmc_ker_ck - 1 - 6Tfmc_ker_ck + 0.5

ns
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
tw(NE)
FMC_NEx
FMC_NOE
tv(NWE_NE) tw(NWE) th(NE_NWE)
FMC_NWE
tv(A_NE) th(A_NWE)
FMC_A[25:0] Address
tv(BL_NE) th(BL_NWE)
FMC_NBL[1:0] NBL
tv(Data_NE) th(Data_NWE)
FMC_D[15:0] Data
tv(NADV_NE)
tw(NADV)
FMC_NADV(1)
FMC_NWAIT
DT32754V1
th(NE_NWAIT)
tsu(NWAIT_NE)
1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used.
Table 72. Asynchronous multiplexed PSRAM/NOR read timings

tv(NOE_NE) FMC_NEx low to FMC_NOE low 2Tfmc_ker_ck - 1 - 2Tfmc_ker_ck + 0.5
ttw(NOE) FMC_NOE low time Tfmc_ker_ck - 1 - Tfmc_ker_ck + 0.5 ns

th(NE_NOE) FMC_NOE high to FMC_NE high hold time Tfmc_ker_ck - -
DS14284 - Rev 2 page 155/234

tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 - 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 - Tfmc_ker_ck + 0.5
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck - 3 - -
th(A_NOE) Address hold time after FMC_NOE high Address held until next read operation
ns
tsu(Data_NE) Data to FMC_NEx high setup time Tfmc_ker_ck + 14 - -
tsu(Data_NOE) Data to FMC_NOE high setup time 15 - -
th(Data_NE) Data hold time after FMC_NEx high 0 - -
th(Data_NOE) Data hold time after FMC_NOE high 0 - -
Table 73. Asynchronous multiplexed PSRAM/NOR read - NWAIT timings


tw(NOE) FMC_NWE low time 6Tfmc_ker_ck - 1 - 6Tfmc_ker_ck + 0.5

ns
DS14284 - Rev 2 page 156/234

Figure 23. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FMC_NE
tv(NOE_NE) th(NE_NOE)
FMC_NOE
tw(NOE)
FMC_NWE
tv(A_NE) th(A_NOE)
FMC_A[25:16] Address
tv(BL_NE) th(BL_NOE)
FMC_NBL[1:0] NBL
th(Data_NE)
tsu(Data_NE)
tv(A_NE) tsu(Data_NOE) th(Data_NOE)
FMC_AD[15:0] Address Data
tv(NADV_NE) th(AD_NADV)
tw(NADV)
FMC_NADV
FMC_NWAIT
DT32755V1
th(NE_NWAIT)
tsu(NWAIT_NE)
Table 74. Asynchronous multiplexed PSRAM/NOR write timings

tw(NE) FMC_NE low time 4Tfmc_ker_ck - 1 - 4Tfmc_ker_ck + 1
tv(NWE_NE) FMC_NEx low to FMC_NWE low Tfmc_ker_ck - 1 - Tfmc_ker_ck + 0.5
tw(NWE) FMC_NWE low time 2Tfmc_ker_ck - 0.5 - 2Tfmc_ker_ck + 0.5
th(NE_NWE) FMC_NWE high to FMC_NE high hold time Tfmc_ker_ck - 0.5 - -
tv(A_NE) FMC_NEx low to FMC_A valid - - 1.5
tv(NADV_NE) FMC_NEx low to FMC_NADV low 0 - 0.5
tw(NADV) FMC_NADV low time Tfmc_ker_ck - 1 - Tfmc_ker_ck + 1 ns
th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high Tfmc_ker_ck - 1 - -
th(A_NWE) Address hold time after FMC_NWE high 3Tfmc_ker_ck - 1 - -
th(BL_NWE) FMC_BL hold time after FMC_NWE high 3Tfmc_ker_ck + 1 - -
tv(BL_NE) FMC_NEx low to FMC_BL valid - - 0
tv(Data_NADV) FMC_NADV high to Data valid - - Tfmc_ker_ck + 1
th(Data_NWE) Data hold time after FMC_NWE high 3Tfmc_ker_ck - 1 - -
DS14284 - Rev 2 page 157/234

Table 75. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings

tw(NWE) FMC_NWE low time 7Tfmc_ker_ck - 1 - 7Tfmc_ker_ck + 0.5

ns
Figure 24. Asynchronous multiplexed PSRAM/NOR write waveforms
t w(NE)
FMC_ NEx
FMC_NOE
t v(NWE_NE) t w(NWE) t h(NE_NWE)
FMC_NWE
t v(A_NE) t h(A_NWE)
FMC_ A[25:16]
Address
t v(BL_NE) t h(BL_NWE)
FMC_ NBL[1:0] NBL
t v(A_NE) t v(Data_NADV) t h(Data_NWE)
FMC_ AD[15:0] Address Data
t v(NADV_NE) th(AD_NADV)
t w(NADV)
FMC_NADV
FMC_NWAIT
DT32756V1
th(NE_NWAIT)
tsu(NWAIT_NE)
6.3.19.2 Synchronous waveforms and timings

Figure 25 through Figure 28 represent synchronous waveforms and Table 76 through Table 79 provide the
corresponding timings. The results shown in these tables are obtained with the following FMC configuration:
• BurstAccessMode = FMC_BurstAccessMode_Enable
• MemoryType = FMC_MemoryType_CRAM
• WriteBurst = FMC_WriteBurst_Enable
• CLKDivision = 1
• DataLatency = 1 for NOR flash; DataLatency = 0 for PSRAM
In all the timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period, with the following FMC_CLK maximum
values:
• For 3.0 V < VDD < 3.6 V, FMC_CLK = 70 MHz at 20 pF
DS14284 - Rev 2 page 158/234

• For 1.71 V < VDD < 1.89 V, FMC_CLK = 70 MHz at 20 pF
Table 76. Synchronous non-multiplexed NOR/PSRAM read timings

tw(CLK) FMC_CLK period R × Tfmc_ker_ck - 0.5(1) - -
t(CLKL‑NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - - 2.5
td(CLKH‑NExH) FMC_CLK high to FMC_NEx high (x = 0..2) R × Tfmc_ker_ck / 2 + 1.5(1) - -
td(CLKL‑NADVL) FMC_CLK low to FMC_NADV low - - 2.5
td(CLKL‑NADVH) FMC_CLK low to FMC_NADV high 0.5 - -
td(CLKL‑AV) FMC_CLK low to FMC_Ax valid (x = 16..25) - - 0
td(CLKH‑AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) R × Tfmc_ker_ck / 2 + 0.5(1) - - ns
td(CLKL‑NOEL) FMC_CLK low to FMC_NOE low - - 0
td(CLKH‑NOEH) FMC_CLK high to FMC_NOE high R × Tfmc_ker_ck / 2 + 1(1) - -

tsu(DV‑CLKH) FMC_D[15:0] valid data before FMC_CLK high 3.5 - -
th(CLKH‑DV) FMC_D[15:0] valid data after FMC_CLK high 2 - -
t(NWAIT‑CLKH) FMC_NWAIT valid before FMC_CLK high 4 - -
th(CLKH‑NWAIT) FMC_NWAIT valid after FMC_CLK high 1 - -
1. Clock ratio R = (FMC_CLK period / fmc_ker_ck period).
DS14284 - Rev 2 page 159/234

Figure 25. Synchronous non-multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK)
FMC_CLK
td(CLKL-NExL) td(CLKH-NExH)
Data latency = 0
FMC_NEx
td(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
td(CLKL-AV) td(CLKH-AIV)
FMC_A[25:0]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
tsu(DV-CLKH) th(CLKH-DV)
tsu(DV-CLKH) th(CLKH-DV)
FMC_D[15:0] D1 D2
tsu(NWAITV-CLKH) th(CLKH-NWAITV)
FMC_NWAIT
(WAITCFG = 1b,
WAITPOL + 0b)
FMC_NWAIT
(WAITCFG = 0b,
DT32759V1
WAITPOL + 0b)
Table 77. Synchronous non-multiplexed PSRAM write timings

t(CLK) FMC_CLK period R × Tfmc_ker_ck -0.5(1) - -
td(CLKL‑NExL) FMC_CLK low to FMC_NEx low (x = 0..2) - - 1.5
t(CLKH‑NExH) FMC_CLK high to FMC_NEx high (x = 0..2) R × Tfmc_ker_ck / 2 + 0.5(1) - -
td(CLKH‑AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) R × Tfmc_ker_ck / 2 + 0.5(1) - - ns

td(CLKL‑NWEL) FMC_CLK low to FMC_NWE low - - 1
td(CLKH‑NWEH) FMC_CLK high to FMC_NWE high R × Tfmc_ker_ck / 2(1) - -
td(CLKL‑Data) FMC_D[15:0] valid data after FMC_CLK low - - 3
td(CLKL‑NBLL) FMC_CLK low to FMC_NBL low - - 0
td(CLKH‑NBLH) FMC_CLK high to FMC_NBL high R × Tfmc_ker_ck / 2 + 2(1) - -
tsu(NWAIT‑CLKH) FMC_NWAIT valid before FMC_CLK high 4 - -
DS14284 - Rev 2 page 160/234

th(CLKH‑NWAIT) FMC_NWAIT valid after FMC_CLK high 1 - - ns
Figure 26. Synchronous non-multiplexed PSRAM write timings
tw(CLK) tw(CLK)
FMC_CLK
Data latency = 0
FMC_NEx
t
d(CLKL-NADVL) td(CLKL-NADVH)
FMC_NADV
FMC_A[25:0]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NW
E
td(CLKL-Data) td(CLKL-Data)
FMC_D[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b) tsu(NWAITV-CLKH) td(CLKH-NBLH)
th(CLKH-NWAITV)
FMC_NBL
DT32760V1
Table 78. Synchronous multiplexed NOR/PSRAM read timings
td(CLKH‑AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) R × Tfmc_ker_ck / 2 + 0.5(1) - -

ns
td(CLKL‑NOEL) FMC_CLK low to FMC_NOE low - - 0
td(CLKH‑NOEH) FMC_CLK high to FMC_NOE high R × Tfmc_ker_ck / 2 + 1(1) - -
td(CLKL‑ADV) FMC_CLK low to FMC_AD[15:0] valid - - 3
td(CLKL‑ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0.5 - -
tsu(ADV‑CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 3.5 - -
th(CLKH‑ADV) FMC_A/D[15:0] valid data after FMC_CLK high 2 - -
DS14284 - Rev 2 page 161/234

th(CLKH‑NWAIT) FMC_NWAIT valid after FMC_CLK high 1 - - ns
Figure 27. Synchronous multiplexed NOR/PSRAM read timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
FMC_A[25:16]
td(CLKL-NOEL) td(CLKH-NOEH)
FMC_NOE
td(CLKL-ADIV) th(CLKH-ADV)
td(CLKL-ADV) tsu(ADV-CLKH) tsu(ADV-CLKH) th(CLKH-ADV)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT tsu(NWAITV-CLKH) th(CLKH-NWAITV)

(WAITCFG = 1b,
WAITPOL + 0b)
DT32757V1
Table 79. Synchronous multiplexed PSRAM write timings

td(CLKL‑NADVL) FMC_CLK low to FMC_NADV low - - 2

ns
td(CLKH‑AIV) FMC_CLK high to FMC_Ax invalid (x = 16..25) R × Tfmc_ker_ck / 2 + 0.5(1) - -
td(CLKL‑NWEL) FMC_CLK low to FMC_NWE low - - 1
t(CLKH‑NWEH) FMC_CLK high to FMC_NWE high R × Tfmc_ker_ck / 2(1) - -
td(CLKL‑ADV) FMC_CLK low to FMC_AD[15:0] valid - - 3
DS14284 - Rev 2 page 162/234

td(CLKL‑ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0.5 - -
td(CLKL‑DATA) FMC_A/D[15:0] valid data after FMC_CLK low - - 3
td(CLKL‑NBLL) FMC_CLK low to FMC_NBL low 0 - -

ns
td(CLKH‑NBLH) FMC_CLK high to FMC_NBL high R × Tfmc_ker_ck / 2 + 2(1) - -
th(CLKH‑NWAIT) FMC_NWAIT valid after FMC_CLK high 1 - -
1. Clock ratio R = ( FMC_CLK period / fmc_ker_ck period).
Figure 28. Synchronous multiplexed PSRAM write timings
tw(CLK) tw(CLK) BUSTURN = 0
FMC_CLK
Data latency = 0
FMC_NEx
FMC_NADV
FMC_A[25:16]
td(CLKL-NWEL) td(CLKH-NWEH)
FMC_NWE
td(CLKL-ADIV) td(CLKL-Data)
td(CLKL-ADV) td(CLKL-Data)
FMC_AD[15:0] AD[15:0] D1 D2
FMC_NWAIT
(WAITCFG = 0b,
WAITPOL + 0b)
td(CLKH-NBLH)
DT32758V1
FMC_NBL
6.3.19.3 NAND controller waveforms and timings

Figure 29 and Figure 30 represent synchronous waveforms, and Table 80 and Table 81 provide the corresponding
timings. The results shown in this table are obtained with the following FMC configuration:
• FMC_SetupTime = 0x01
• FMC_WaitSetupTime = 0x03
• FMC_HoldSetupTime = 0x02
• FMC_HiZSetupTime = 0x01
• Bank = FMC_Bank_NAND
• MemoryDataWidth = FMC_MemoryDataWidth_16b
• ECC = FMC_ECC_Enable
• ECCPageSize = FMC_ECCPageSize_512Bytes
• TCLRSetupTime = 0
• TARSetupTime = 0
DS14284 - Rev 2 page 163/234

• CL = 30‑pF
In all timing tables, the Tfmc_ker_ck is the fmc_ker_ck clock period.
Table 80. NAND flash read timings

tw(N0E) FMC_NOE low width 4Tfmc_ker_ck - 0.5 - 4Tfmc_ker_ck + 0.5
tsu(D‑NOE) FMC_D[15-0] valid data before FMC_NOE high 12.5 - -
th(NOE‑D) FMC_D[15-0] valid data after FMC_NOE high 0 - - ns
td(ALE‑NOE) FMC_ALE valid before FMC_NOE low - - 2Tfmc_ker_ck + 1.5
th(NOE‑ALE) FMC_NWE high to FMC_ALE invalid 3Tfmc_ker_ck - 1 - -
Figure 29. NAND controller waveforms for read access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NOE) th(NOE-ALE)
FMC_NWE
tw(NOE)
FMC_NOE (NRE)
tsu(D-NOE) th(NOE-D)
DT73150V1
FMC_D[y:0]
1. y = 7 or 15 depending on the NAND flash memory interface.
Table 81. NAND flash write timings

tw(NWE) FMC_NWE low width 4Tfmc_ker_ck - 1 - 4Tfmc_ker_ck + 1
tv(NWE‑D) FMC_NWE low to FMC_D[15-0] valid 0 - -
th(NWE‑D) FMC_NWE high to FMC_D[15-0] invalid 5Tfmc_ker_ck - 1 - -

ns
td(D‑NWE) FMC_D[15-0] valid before FMC_NWE high 4Tfmc_ker_ck - 1 - -
td(ALE‑NWE) FMC_ALE valid before FMC_NWE low - - 2Tfmc_ker_ck + 1.5
th(NWE‑ALE) FMC_NWE high to FMC_ALE invalid 3Tfmc_ker_ck - 1 - -
DS14284 - Rev 2 page 164/234

Figure 30. NAND controller waveforms for write access
FMC_NCEx
ALE (FMC_A17)
CLE (FMC_A16)
td(ALE-NWE) tw(NWE) th(NWE-ALE)
FMC_NWE
FMC_NOE (NRE)
td(D-NWE)
tv(NWE-D) th(NWE-D)
DT73151V2
FMC_D[y:0]
1. y = 7 or 15 depending on the NAND flash memory interface.
6.3.20 OCTOSPI interface characteristics

Unless otherwise specified, the parameters given in Table 82 , Table 83 and Table 84 for OCTOSPI are derived
from tests performed under the ambient temperature, frequency and supply voltage conditions summarized in
Table 17. General operating conditions , with the following configuration:
• IO compensation cell activated
• VDDIOxVRSEL = 1 for VDDIOx < 2.7 V
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate function
characteristics.
Table 82. OCTOSPI characteristics in SDR mode

Values in the table applies to octal and quad SPI mode.
3 < VDDIOx < 3.6, CL = 20 pF,

- - 120
OCTOSPIM port1
3 < VDDIOx < 3.6, CL = 20 pF,
- - 133
OCTOSPIM port2
F(CLK) Clock frequency 2.7 < VDDIOx < 3.6, CL = 20 pF, MHz
- - 100
OCTOSPIM port1
2.7 < VDDIOx < 3.6, CL = 20 pF,
- - 110
OCTOSPIM port2
1.71 < VDDIOx < 1.89, CL = 20 pF - - 133
tw(CLKH) Clock high and t(CLK) / 2 - t(CLK)/2 +1

low time - Even PRESCALER[7:0] = n = 0,1,3,5
tw(CLKL) division t(CLK)/2 - 1 - t(CLK)/2
(n/ ns
tw(CLKH) (n/2) × t(CLK) / (n+1) -
Clock high and 2) × t(CLK) / (n+1) + 1
low time - Odd PRESCALER[7:0] = n = 2,4,6,8
division (n/
tw(CLKL) - (n/2+1) × t(CLK) / (n+1)
2+1) × t(CLK) / (n+1) - 1
DS14284 - Rev 2 page 165/234

Data input setup

ts(IN) - 2.5 - -
time
Data input hold
th(IN) - 1.5 - -
time
ns
Data output valid
tv(OUT) - - 0.5 1
time
Data output hold
th(OUT) - 0 - -
time
Figure 31. OCTOSPI timing diagram - SDR mode
tr(CLK) t(CLK) tw(CLKH) tw(CLKL) tf(CLK)
Clock
tv(OUT) th(OUT)
Data output D0 D1 D2
ts(IN) th(IN)
DT36878V1
Data input D0 D1 D2
Table 83. OCTOSPI characteristics in DTR mode (without DQS)

Values in the table applies to octal and quad SPI mode.
(1)
2.7 < VDDIOx <3.6, CL = 20 pF - - 100

Clock
F(CLK) 1.71 < VDDIOx < 1.89, MHz
frequency - - 100
CL = 20 pF
tw(CLKH) Clock high t(CLK) / 2 - t(CLK) / 2 + 1

and low time
PRESCALER[7:0] = n = 0,1,3,5
tw(CLKL) - Even t(CLK)/ 2 - 1 - t(CLK) / 2
division
(n/
tw(CLKH) (n/2) × t(CLK) / (n+1) -
Clock high 2) × t(CLK) / (n+1) + 1
and low time
PRESCALER[7:0] = n = 2,4,6,8 (n/
- Odd (n/
tw(CLKL) division 2+1) × t(CLK) / (n+1) - -
2+1) × t(CLK) / (n+1)
1
tsr(IN), Data input ns
- 2 - -
tsf(IN) setup time
thr(IN), Data input

- 1.5 - -
thf(IN) hold time
tvr(OUT), Data output - 1 + t(CLK) / 4 1.5 + t(CLK) / 4

-
tvf(OUT)(1) valid time - 1 1.5
thr(OUT), Data output t(CLK) / 4 - 0.5 - -

-
thf(OUT)(1) hold time 0 - -
1. When PRESCALER = 0 the DLL must be used for TX delay.
DS14284 - Rev 2 page 166/234

Figure 32. OCTOSPI timing diagram - DTR mode
Clock
tvf(OUT) thr(OUT) tvr(OUT) thf(OUT)
Data output D0 D1 D2 D3 D4 D5
tsf(IN) thf(IN) tsr(IN) thr(IN)
DT36879V1
Data input D0 D1 D2 D3 D4 D5
Table 84. OCTOSPI characteristics in DTR mode (with DQS or HyperBus)

(3)
2.7 < VDDIOx < 3.6, CL = 20 pF - - 133

Clock
F(CLK) 1.71 < VDDIOx < 1.89, MHz
frequency - - 133
CL = 20 pF
tw(CLKH) Clock high t(CLK) / 2 - t(CLK) / 2 + 1

and low time
PRESCALER[7:0] = n = 0,1,3,5
tw(CLKL) - Even t(CLK) / 2 - 1 - t(CLK) / 2
division
(n/
tw(CLKH) (n/2) × t(CLK) / (n+1) -
Clock high 2) × t(CLK) / (n+1) + 1
and low time
PRESCALER[7:0] = n = 2,4,6,8 (n/
- Odd (n/
tw(CLKL) division 2+1) × t(CLK) / (n+1) - -
2+1) × t(CLK) / (n+1)
1
Chip select
tw(CS) - 3 × t(CLK) - -
high time
CS to Clock
tv(CK) - - - t(CLK) + 1
valid time
Clock to CS
th(CK) high hold - 3.5×t(CLK) - - ns
time
CK,CK#
crossing
VODr(CK) VDDIOx = 1.8 V 1157 - 1389
level on CK
rising edge
CK,CK#
crossing
VODf(CK) VDDIOx = 1.8 V 1087 - 1312
level on CK
falling edge
tsr(DQ), F(CLK) > 50 MHz(1) 1.5 - t(CLK) / 4 - -

Data input
tsf(DQ) setup time F(CLK) < 50 MHz(2) -1 - -
thrDQN), F(CLK) > 50 MHz(1) 1.5 + t(CLK) / 4 - -

Data input
thf(DQ) hold time F(CLK) < 50 MHz(2) 3 - -
DS14284 - Rev 2 page 167/234

Data strobe
tv(DS) input valid - 0 - -
time
Data strobe
th(DS) input hold - 0 - -
time
Data strobe
tv(RWDS) output valid - - - 3 × t(CLK) ns
time
tvr(OUT), Data output - 1 + t(CLK) / 4 1.5 + t(CLK) / 4

-
tvf(OUT)(3) valid time - 1 1.5
thr(OUT), Data output t(CLK) / 4 - 0.5 - -

-
thf(OUT)(3) hold time 0 - -
1. DLL enabled in lock mode (SYSCFG_DLYBOSxCR.EN = 1) with 25% delay

(SYSCFG_DLYBOSxCR.RX_TAP_SEL[5:0] = 0x8).
2. DLL enabled in bypass mode (SYSCFG_DLYBOSxCR.BYP_EN = 1) with typical settings
(SYSCFG_DLYBOSxCR.RX_TAP_SEL[5:0] = 0x2 and SYSCFG_DLYBOSxCR.BYP_CMD[4:0] = 0x18).

3. When PRESCALER = 0 the DLL must be used for TX delay.
Figure 33. OCTOSPI HyperBus clock

tf(NCLK) t(NCLK) tw(NCLKL) tw(NCLKH) tr(NCLK)
NCLK
DT47732V1
VOD(CLK)
CLK
Figure 34. OCTOSPI HyperBus read
tw(CS)
NCS
tv(CLK) tACC = initial access th(CLK)
CLK, NCLK
tv(RWDS) tv(DS) th(DS)
RWDS
tv(OUT) th(OUT) Latency count tv(DQ) ts(DQ) th(DQ)
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

A B A B
Command address
Memory drives DQ[7:0] and RWDS.
DT47733V1
Host drives DQ[7:0] and the memory drives RWDS.
DS14284 - Rev 2 page 168/234

Figure 35. OCTOSPI HyperBus read with double latency
NCS
tRWR = read/write recovery Additional latency tACC = access
CLK, NCLK
tCKDS
RWDS High = 2x latency count

Low = 1x latency count
RWDS and data
are edge aligned
DQ[7:0] 47:40 39:3231:24 23:16 15:8 7:0 Dn
A
Dn Dn+1 Dn+1
B A B
DT49351V1
Command address Memory drives DQ[7:0] and RWDS
Host drives DQ[7:0] and the memory drives RWDS
Figure 36. OCTOSPI HyperBus write

tw(CS)
NCS
Read write recovery Access latency

tv(CLK) th(CLK)
CLK, NCLK
tv(OUT) th(OUT)
tv(RWDS) High = 2x latency count
Low = 1x latency count
RWDS
Latency count
tv(OUT) th(OUT) tv(OUT) th(OUT)
DQ[7:0] 47:40 39:32 31:24 23:16 15:8 7:0 Dn Dn Dn+1 Dn+1

A B A B
Command address
DT47734V1
Host drives DQ[7:0] and RWDS.

Host drives DQ[7:0] and the memory drives RWDS.
6.3.21 Delay block (DLYB) characteristics

Unless otherwise specified, the parameters given in Table 85 for the delay block are derived from tests performed
under the ambient temperature and VDD supply voltage summarized in Table 17. General operating conditions .
Table 85. DLYB characteristics

tinit Initial delay Bypass mode 100 150 300
Bypass mode 30 31 49 ps
t∆ Unit delay
Lock mode - T/ 32(1) -
DS14284 - Rev 2 page 169/234


t∆ Unit delay Lock mode -1 - +15 %
1. T is the period of the DLL clock.
6.3.22 12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 86. ADC characteristics are derived from tests
performed under the ambient temperature, frequency and VDDA supply voltage conditions summarized in
Table 17. General operating conditions.
Table 86. ADC characteristics

ADC adc_ker_ck clock

fADC frequency (clock after ADC - 0.7 - 70 MHz
prescaler)
resolution = 12 bits 0.0467 - 4.666

fs Sampling rate MSps
resolution = 8 bits 0.07 - 7
resolution = 12 bits - 13.5 -
tc(1) Conversion cycle 1 / fADC
- - 3.888 MHz
fTRIG External trigger frequency fADC = 70 MHz, Resolution = 12 bits
18 - - 1 / fADC
Single ended 0 - VREF+

VAIN(1) Conversion voltage range(2) V
Differential -VREF+ - VREF+
VCMIV(1) Common mode input voltage Differential - VREF+ / 2 - V
Internal sample and hold

CADC - - 2.56 - pF
capacitor
tSTAB ADC power-up time DEEPPWD from 1 to 0 - 5 - μs
tEN ADC enable time ADEN from 0 to 1 - 5 - 1 / fADC
Trigger conversion latency CKMODE = 0 2.5 - 3.5

tLATR(1) regular and injected channels 1 / fADC
without conversion abort CKMODE = 1 - 3 -
Trigger conversion latency CKMODE = 0 3.5 - 4.5

tLATRINJ(1) regular injected channels 1 / fADC
aborting a regular conversion CKMODE = 1 - 4 -
tS(1) Sampling time - 1.5 - 1499.5 1 / fADC
fs = 4.666 Msps, resolution = 12 bits - 315 -
fs = 5.384 Msps, resolution = 10 bits - 330 -

ADC supply current on
IADC(VDDA18ADC) μA
VDDA18ADC Power down, ADEN = 0 - 2.05 -
Deep power down, ADEN = 0,
- 1.65 -
DEEPPWD = 1

2. All analog inputs must be between VSSA and VDDA18ADC.
DS14284 - Rev 2 page 170/234

Table 87. ADC accuracy

Single ended with dedicated ANA input - 4.6 40 +/-

Differential with dedicated ANA input - 5.2 22 LSB
Total unadjusted
ET
error (TUE) Single ended with general purpose IO (GPIO) input - 13 24 +/-
Differential with general purpose IO (GPIO) input - 6.3 18 LSB
Single ended with dedicated ANA input - 0.9 2 +/-

Differential with dedicated ANA input - 0.8 2 LSB
Differential linearity
ED
error (DNL) Single ended with general purpose IO (GPIO) input - 0.9 2 +/-
Differential with general purpose IO (GPIO) input - 0.9 2 LSB
Single ended with dedicated ANA input - 2 6 +/-

Differential with dedicated ANA input - 2 5 LSB
Integral linearity
EL
error (INL) Single ended with general purpose IO (GPIO) input - 4 6 +/-
Differential with general purpose IO (GPIO) input - 3 8 LSB
Single ended with dedicated ANA input - 9.9 -

Bits
Effective number of Differential with dedicated ANA input - 10.5 -
ENOB
bits Single ended with general purpose IO (GPIO) input - 9.35 -
Bits
Differential with general purpose IO (GPIO) input - 10.5 -
dB
Signal-to-noise and Differential with dedicated ANA input - 66 -
SINAD
distortion ratio(1) Single ended with general purpose IO (GPIO) input - 58 -
dB
Differential with general purpose IO (GPIO) input - 64 -
dB
Differential with dedicated ANA input - 66.5 -
SNR Signal-to-noise ratio
Single ended with general purpose IO (GPIO) input - 58.5 -
dB
Differential with general purpose IO (GPIO) input - 65 -
Single ended with dedicated ANA input - -76 -
dB
Total harmonic Differential with dedicated ANA input - -79 -
THD
distortion Single ended with general purpose IO (GPIO) input - -74.5 -
dB
Differential with general purpose IO (GPIO) input - -73.5 -
Versus VREF+ value with dedicated ANA input -1 - +1 %Full
EG Gain error Versus VREF+ value with general purpose IO (GPIO) -Scal
-1 - +1 e
input
%Full
Without calibration with ANA input -1 - +1 -Scal
e
After calibration with ANA input -2 - +2 LSB
EO Offset error
%Full
Without calibration with general purpose IO (GPIO)
-1 - +1 -Scal
input
e
After calibration with general purpose IO (GPIO) input -2 - +2 LSB
1. Value measured with a -0.5dBFS input signal and then extrapolated to full scale.
DS14284 - Rev 2 page 171/234

Figure 37. ADC accuracy characteristics
VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
VSSA
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
DT19880V6
1. Refer to Table 88 for the values of RAIN, RADC and CADC.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad
capacitance (refer to Table 61. I/O static characteristics). A high Cparasitic value downgrades conversion
accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 61. I/O static characteristics for value of Ilkg.
4. Refer to Figure 11. Power supply scheme .
Table 88. Minimum sampling time versus RAIN

Symbol Parameter Conditions (Resolution / RAIN in ohms) Min Typ Max Unit
47 32 - -
68 33 - -
100 34 - -
150 36 - -
ts_min Minimum sampling time 12 bits 220 38 - - ns
330 42 - -
470 47 - -
680 55 - -
1000(1) 70 - -
47 23 - -
68 24 - -
100 25 - -
150 26 - -

330 30 - -
470 33 - -
680 38 - -
1000 45 - -
DS14284 - Rev 2 page 172/234

Symbol Parameter Conditions (Resolution / RAIN in ohms) Min Typ Max Unit
1500 55 - -
2200 71 - -
4700 133 - -
6800(1) 238 - -
47 17 - -
68 17 - -
100 18 - -
150 19 - -
220 20 - -
330 22 - -
470 25 - -
680 28 - -

1500 42 - -
2200 53 - -
3300 70 - -
4700 94 - -
6800 128 - -
10000 183 - -
15000 277 - -
22000(1) 435 - -
1. Maximum external input impedance value authorized for the given Resolution.
Figure 38. Typical connection diagram using the ADC with TT pins featuring analog switch function
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
Cparasitic(2) Ilkg(3) CADC

VAIN Sampling
switch with
multiplexing
DT67871V3
VSS VSS VSSA
6.3.22.1 General PCB design guidelines

PCB design guidelines are provided in AN5489 "Getting started with STM32MP25xx lines hardware development"
available from the ST website www.st.com.
DS14284 - Rev 2 page 173/234

6.3.23 Voltage reference buffer (VREFBUF) characteristics
Table 89. VREFBUF characteristics

Analog supply VRS = 000 1.62 1.8 1.89(1)

VDDA18ADC -
voltage VRS = 001 1.75 1.8 1.89(1)
V
@30 °C, VRS = 000 1.203 1.21 1.216
Voltage Reference @ILOAD = 10 μA,
VREFBUF_OUT
Buffer Output VRS = 001 1.491 1.5 1.506
VDDA18ADC = 1.8 V
TRIM Trim step resolution - - ±0.05 ±0.1 %

CL Load Capacitor - 0.5 1.1 1.5 μF
Equivalent Serial
esr - - - 1 Ω
Resistor of CL
External DC load All ADCs ON - - 0.8

ILOAD mA
current All ADCs OFF - - 2
ILINE_REG Line regulation 1.62 V ≤ VDDA18ADC ≤ 1.89 V - 7500 11000 ppm/V
ppm/m
ILOAD_REG Load regulation 100 μA ≤ ILOAD ≤ 800 μA - 4700 6000
A
-40 °C < TJ < +30 °C +89 - +305
Temperature ppm/°
Tcoeff
coefficient +30 °C < TJ < +125 °C -15 - +68 C
Acoeff Long term stability 1000 hours, TJ = 125 °C -2000 - +2000 ppm
Power supply DC 48 76 -
PSRR dB
rejection 100 kHz 51 60 -
tSTART Start-up time - - 260 388 μs
Control of max. DC current drive on VREFBUF_OUT during start‑up

IINRUSH - - 10 mA
phase (tSTART)
ILOAD = 0.8 mA DC - 9 21
VREFBUF supply
current VDDA18ADC ENVR = 1 Peak during 2 × ADC μA
IVDDA18ADC(VREFBUF) - 48 56
(excluding internal conversion
and external load)
ENVR = 0 - 3 6.5 μA
1. Static condition. 1.98 V allowed during transients.
6.3.24 Digital Temperature Sensor (DTS) characteristics
Table 90. DTS characteristics

fDTS Operating frequency - 4 - 8 MHz
Res Resolution - 8 10 12 Bits

Step Step size For respecively 8, 10 and 12 bits resolution 0.86 0.22 0.06 °C
tconv Conversion time For respecively 8, 10 and 12 bits resolution 512 2048 8192
1 / fDTS
tpwrup Power up time - - - 256
TA Accuracy From -20 to +125 °C - - 3(1) °C
DS14284 - Rev 2 page 174/234


TA Accuracy From -40° C to -20 °C - - 6 °C
G G constant Refer to reference manual for the formula 59.7 °C

H H constant Refer to reference manual for the formula 204.4 °C
J J constant Refer to reference manual for the formula -0.16 °C / MHz
Cal5 Cal5 constant Refer to reference manual for the formula 4094 -
TS0 sensor Inside padring(2) -

TSloc Sensor location
TS1 sensor Inside device logic(2) -
fDTS = 8 MHz, continuous measurements, single

- 120 160
sensor
DTS supply current on
IDTS(VDDA18AON) μA
VDDA18AON At 1 measurement/s - - 1
fDTS clock stopped - - 1
DTS supply current on

IDTS(VDDCORE) fDTS = 8 MHz - - 15 μA
VDDCORE

2. Temperature in padring sensor (side of the silicon die) is usually slightly lower than device logic sensor as most heat is
generated inside device logic.
6.3.25 VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics
Table 91. VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics

R Resistor bridge for VBAT - - 130 - kΩ
Q Ratio on VBAT measurement - - 4 - -
Er Error on Q - -1 - +1 %
tS_VBAT(1) ADC sampling time when reading the VBAT - 34 - - ns
tS_VDDCPU (1) ADC sampling time when reading the VDDCPU - 34 - - ns
tS_VDDCORE(1) ADC sampling time when reading the VDDCORE - 34 - - ns
tS_VDDGPU (1) ADC sampling time when reading the VDDGPU - 34 - - ns
6.3.26 Temperature and VBAT monitoring characteristic for tamper detection
Table 92. TEMP and VBAT Monitoring characteristics

TEMPH High TJ temperature monitoring - 110 - 125

°C
TEMPL Low TJ temperature monitoring - -40 - -30
V08CAPH High V08CAP supply monitoring(1) - 0.88 - 1 V
V08CAPL Low V08CAP supply monitoring(1) - 0.6 - 0.72 -
V08CAP_filter V08CAP supply monitoring glitch filter(1) - - - 1 μs
1. V08CAP is an internal regulator supplied by VSW. VSW is equal to VDD when present or VBAT otherwise.
DS14284 - Rev 2 page 175/234

6.3.27 Voltage monitoring characteristics
Table 93. Voltage monitoring characteristics (VDDCORE, VDDCPU, VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4,
VDD33USB, VDD33UCPD)
VDDCORE monitoring
Threshold on rising
VOV_VDCORE To set VCOREH bit (overvoltage) 0.88(1) - -
edge
V
Threshold on falling
VUV_VDDCORE To set VCOREL bit (undervoltage) 0.72 - 0.78(1)
edge
Hysteresis on
Vhyst_VDDCORE To clear VCOREL or VCOREH bit - 20 - mV
monitoring
Supply current on
IUV_OV_VDDCORE(VDDA18AON) VCOREMONEN = 1 - 0.75 - μA
VDDA18AON
VDDCPU monitoring
Threshold on rising
VOV_VDDCPU To set VCPUH bit (overvoltage) 0.99(1) - -
edge
V
Threshold on falling To set VCPUL bit VCPULLS = 0 0.72 - 0.78(1)
VUV_VDDCPU
edge (undervoltage) VCPULLS = 1 0.81 - 0.87
Hysteresis on
Vhyst_VDDCPU To clear VCPUL or VCPUH bit - 20 - mV
monitoring
Supply current on
IUV_OV_VDDCPU(VDDA18AON) VCPUMONEN = 1 - 0.75 - μA
VDDA18AON
VDDGPU monitoring
Threshold on rising To set VDDGPURDY GPULVTEN = 0 0.63(1) - -

VRDY_VDDDGPU V
edge bit GPULVTEN = 1 0.55 - -
Hysteresis on falling
Vhyst_VDDGPU To clear VDDGPURDY bit - 23 - mV
edge
To set VDDGPURDY bit 180 400 750
Tdelay_VDDGPU Delay after detection μs
To clear VDDGPURDY bit - 0 -
Supply current on
IRDY_VDDGPU(VDDA18AON) GPUVMEN = 1 - 0.75 - μA
VDDA18AON
PVD_IN monitoring
Threshold on rising
VPVD_IN - - 0.815 - V
edge
Hysteresis on
Vhyst_PVD - - 30 - mV
monitoring
Supply current on
IPVD(VDDA18AON) PVDEN = 1 - 0.75 - μA
VDDA18AON
VDDA18ADC monitoring
Threshold on rising
VRDY_VDDA18ADC - - - 1.55(1) V
edge
Hysteresis on
Vhyst_VDDA18ADC - - 40 - mV
monitoring
Supply current on
IRDY_VDDA18ADC(VDDA18AON) AVMEN = 1 - 0.75 - μA
VDDA18AON
DS14284 - Rev 2 page 176/234

Supply current on
IRDY_VDDA18ADC AVMEN = 1 - 1 - μA
VDDA18ADC
VDDIO1 monitoring
Threshold on rising
VRDY_VDDIO1 - - - 1.55(1) V
edge
Hysteresis on
Vhyst_VDDIO1 - - 40 - mV
monitoring
Supply current on
IRDY_VDDIO1(VDDA18AON) VDDIO1VMEN = 1 - 0.75 - μA
VDDA18AON
Supply current on VDDIO1 = 1.8 V - 0.5 -

IRDY_VDDIO1 Always ON μA
VDDIO1 VDDIO1 = 3.3 V - 1 -
VDDIO2 monitoring
Threshold on rising
VRDY_VDDIO2 - - - 1.55(1) V
edge
Hysteresis on
monitoring
Supply current on
VDDA18AON

VDDIO3 monitoring
Threshold on rising
VRDY_VDDIO3 - - - 1.55(1) V
edge
Hysteresis on
monitoring
Supply current on
VDDA18AON

VDDIO4 monitoring
Threshold on rising
VRDY_VDDIO4 - - - 1.55(1) V
edge
Hysteresis on
monitoring
Supply current on
VDDA18AON

VDD33USB monitoring
Threshold on rising
VRDY_VDD33USB - - - 1.55(1) V
edge
Hysteresis on
Vhyst_VDD33USB - - 40 - mV
monitoring
Supply current on
IRDY_VDD33USB(VDDA18AON) USB33VMEN = 1 - 0.75 - μA
VDDA18AON
Supply current on
IRDY_VDD33USB Always ON - 1 - μA
VDD33USB
DS14284 - Rev 2 page 177/234

VDD33UCPD monitoring
Threshold on rising
VRDY_VDD33UCPD - - - 1.55(1) V
edge
Hysteresis on
Vhyst_VDD33UCPD - - 40 - mV
monitoring
Supply current on
IRDY_VDD33UCPD(VDDA18AON) UCPDVMEN = 1 - 0.75 - μA
VDDA18AON
Supply current on
IRDY_VDD33UCPD Always ON - 1 - μA
VDD33UCPD
6.3.28 Compensation cell characteristics
Table 94. Compensation cell characteristics

ICOMPCELL VDDA18AON current consumption during code calculation - 250 - μA
Time needed to have the first code calculation after

Tready Using a 8 MHz clock (HSI / 8) - 96 -
enabling μs
Tmeasure Time needed to update the code - 832 -
6.3.29 Multi-function digital filter (MDF) characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests performed under the
ambient temperature, frequency and supply voltage conditions summarized in Table 17. General operating
conditions, with the following configuration:
• Measurement points done at CMOS levels: 0.5 × VDD
• I/O compensation cell activated
• VDDxVRSEL activated when VDDx ≤ 2.7 V
Table 95. MDF characteristics

Input clock frequency via

fCKI MDF_CKIx pin, in SLAVE SPI - - - 25
mode
fCCKI MDF_CCK[1:0] pin, in SLAVE SPI - - - 25
mode
MHz
Output clock frequency in MASTER
fCCKO - - - 25
SPI mode
Output clock frequency in
fCCKOLF - - - 5
LF_MASTER SPI mode
Input symbol rate in Manchester
fSYMB - - - 20
mode
MDF_CKIx input clock high and low
tHCKI tLCKI In SLAVE SPI mode 2 × Tmdf_proc_ck(1) - -
time
ns
MDF_CCK[1:0] input clock high
tHCCKI tLCCKI In SLAVE SPI mode 2 × Tmdf_proc_ck(1) - -
and low time
DS14284 - Rev 2 page 178/234

MDF_CCK[1:0] output clock high

tHCCKO tLCCKO In MASTER SPI mode 2 × Tmdf_proc_ck(1) - -
and low time
tHCCKOLF MDF_CCK[1:0] output clock high
In LF_MASTER SPI mode Tmdf_proc_ck(1) - -
tLCCKOLF and low time
Data setup time with respect to

tSUCKI 7.5 - -
MDF_CKIx input In SLAVE SPI mode, measured on
Data hold time with respect to rising and falling edge
tHDCKI 0.5 - -
MDF_CKIx input
Data setup time with respect to In SLAVE SPI mode:
tSUCCKI 8.5 - -
MDF_CCK[1:0] input MDF_CCK[1:0] configured in ns
Data hold time with respect to input, measured on rising and
tHDCCKI falling edge 0.5 - -
MDF_CCK[1:0] input
Data setup time with respect to In MASTER SPI mode:
tSUCCKO 8.5 - -
MDF_CCK[1:0] output MDF_CCK[1:0] configured in
Data hold time with respect to output, measured on rising and
tHDCCKO falling edge 0.5 - -
MDF_CCK[1:0] output
Data setup time with respect to In LF_MASTER SPI mode,

tSUCCKOLF 14.5 - -
MDF_CCK[1:0] output MDF_CCK[1:0] configured in
tHDCCKOLF falling edge 0.5 - -
MDF_CCK[1:0] output
1. Tmdf_proc_ck is the period of the MDF processing clock.
Figure 39. MDF timing diagram
tSUCKI tHDCKI tSUCKI tHDCKI

fCKI, fCCKI, FCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCKI, tLCCKI, tHCKI, tHCCKI,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKO tHCCKO
MDF_CKIx (I)
MDF_CCK (I/O)
DT69125V1
MDF_SDIx (I)
6.3.30 Audio digital filter (ADF) characteristics

Table 96. ADF characteristics


fCCKI ADF_CCK[1:0] pin, in SLAVE SPI - - - 25
mode
MHz
fCCKO - - - 25
MASTER SPI mode
DS14284 - Rev 2 page 179/234


fCCKOLF - - - 5
LF_MASTER SPI mode
MHz
Input symbol rate in Manchester
fSYMB - - - 20
mode
ADF_CCK[1:0] input clock high
tHCCKI tLCCKI In SLAVE SPI mode 2 × Tadf_proc_ck(1) - -
and low time
ADF_CCK[1:0] output clock high
tHCCKO tLCCKO In MASTER SPI mode 2 × Tadf_proc_ck(1) - -
and low time
tHCCKOLF ADF_CCK[1:0] output clock high
In LF_MASTER SPI mode Tadf_proc_ck(1) - -
tLCCKOLF and low time
Data setup time with respect to In SLAVE SPI mode:

tSUCCKI 2.5 - -
ADF_CCK[1:0] input ADF_CCK[1:0] configured in input,
Data hold time with respect to measured on rising and falling
tHDCCKI edge 0.5 - - ns
ADF_CCK[1:0] input
Data setup time with respect to In MASTER SPI mode:
tSUCCKO 2 - -
ADF_CCK[1:0] output ADF_CCK[1:0] configured in
output, measured on rising and
Data hold time with respect to

tHDCCKO falling edge 1 - -
ADF_CCK[1:0] output
Data setup time with respect to In LF_MASTER SPI mode,
tSUCCKOLF 7 - -
ADF_CCK[1:0] output ADF_CCK[1:0] configured in
tHDCCKOLF falling edge 0.5 - -
ADF_CCK[1:0] output
1. Tadf_proc_ck is the period of the ADF processing clock.
Figure 40. ADF timing diagram

fCCKI, fCCKO, fCCKOLF
tSUCCKI tHDCCKI tSUCCKI tHDCCKI
tSUCCKO tHDCCKO tSUCCKO tHDCCKO tLCCKI, tLCCKO, tHCCKI, tHCCKO,
tSUCCKOLF tHDCCKOLF tSUCCKOLF tHDCCKOLF tLCCKOLF tHCCKOLF
ADF_CCK (I/O)
DT69124V1
ADF_SDIx (I)
6.3.31 Camera interface (DCMI) characteristics

• DCMI_PIXCLK polarity: falling
• DCMI_VSYNC and DCMI_HSYNC polarity: high
• Data formats: 14 bits
DS14284 - Rev 2 page 180/234

Table 97. DCMI characteristics

clock_ratio Frequency ratio DCMI_PIXCLK / fHCLK - - 0.4 -
DCMI_PIXCLK Pixel clock input - - 80 MHz

DPIXEL Pixel clock input duty cycle 30 - 70 %
tsu(DATA) Data input setup time 3 - -
th(DATA) Data hold time 1 - -

ns
tsu(HSYNC) tsu(VSYNC) DCMI_HSYNC and DCMI_VSYNC input setup times 3 - -
th(HSYNC) th(VSYNC) DCMI_HSYNC and DCMI_VSYNC input hold times 1 - -
Figure 41. DCMI timing diagram
1/DCMI_PIXCLK
DCMI_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMI_HSYNC
tsu(VSYNC) th(HSYNC)
DCMI_VSYNC
tsu(DATA) th(DATA)
DATA[0:13]
DT32414V1
6.3.32 Camera interface (DCMIPP) characteristics

Unless otherwise specified, the parameters given in Table 98 for DCMIPP are derived from tests performed under
the ambient temperature, frequency and supply voltage conditions summarized in Table 17. General operating
• DCMIPP_PIXCLK polarity: falling (refer to AN5489 "Getting started with STM32MP25xx lines hardware
development") available from the ST website www.st.com.
• DCMIPP_VSYNC and DCMIPP_HSYNC polarity: high
• Data formats: 16 bits
• Capacitive load C = 30 pF
DS14284 - Rev 2 page 181/234

Table 98. DCMIPP characteristics

DCMIPP_PIXCLK Pixel clock input - - - 120 MHz

DPixel Pixel clock input duty cycle - 30 - 70 %
tsu(DATA) Data input setup time - 2 - -
th(DATA) Data input hold time - 3 - -

ns
tsu(HSYNC) tsu(VSYNC) DCMIPP_HSYNC / DCMIPP_VSYNC input setup time - 2 - -
th(HSYNC) th(VSYNC) DCMIPP_HSYNC / DCMIPP_VSYNC input hold time - 3 - -
Figure 42. DCMIPP timing diagram
1/DCMIPP_PIXCLK
DCMIPP_PIXCLK
tsu(HSYNC) th(HSYNC)
DCMIPP_HSYNC
tsu(VSYNC) th(HSYNC)
DCMIPP_VSYNC
tsu(DATA) th(DATA)
DT73149V1
DATA[15:0]
6.3.33 Parallel interface (PSSI) characteristics

• PSSI_PDCK polarity: falling
• PSSI_RDY and PSSI_DE polarity: low
• Bus width: 16 lines
• Data width: 32 bits
Table 99. PSSI transmit characteristics

clock_ratio Frequency ratio DCMI_PDCK/fHCLK - - - 0.4 -
PSSI_PDCK PSSI clock input - - - 74(1) MHz
DPIXEL PSSI clock input duty cycle - 30 - 70 %
tOV(DATA) Data output valid time - - - 13.5

ns
tOH(DATA) Data output hold time - 5.5 - -
DS14284 - Rev 2 page 182/234

tOV(DE) DE output valid time - - 10

-
tOH(DE) DE output hold time 6.5 - -
ns
tSU(RDY) RDY input setup time 0 - -
-
tH(RDY) RDY input hold time 5.5 - -
1. This maximal frequency does not consider receiver setup and hold timings.
Figure 43. PSSI transmit timing diagram
tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
tv(DATA) tho(DATA)
PSSI D[15:0]
Invalid data OUT Valid data OUT Invalid data OUT
(output)
tv(DE) tho(DE)
DEPOL=0
PSSI_DE
(output)
DEPOL=1
ts(RDY) th(RDY)
PSSI_RDY
RDYPOL=0
(input)
RDYPOL=1
DT63437V1
Table 100. PSSI receive characteristics
clock_ratio Frequency ratio DCMI_PDCK/fHCLK - - - 0.4 -
PSSI_PDCK PSSI clock input - - - 80 MHz

DPIXEL PSSI clock input duty cycle - 30 - 70 %
tSU(DATA) Data input setup time - 2.5 - -
tH(DATA) Data input hold time - 1.5 - -
tSU(DE) DE input setup time - 1.5 - -

ns
tH(DE) DE input hold time - 1 - -
tOV(RDY) RDY output valid time - - - 11.5
tOH(RDY) RDY output hold time - 8 - -
DS14284 - Rev 2 page 183/234

Figure 44. PSSI receive timing diagram
tc(PDCK)
tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK)

PSSI_PDCK
CKPOL=0
(input)
CKPOL=1
ts(DATA)
th(DATA)
PSSI D[15:0]
Invalid data IN Valid data IN Invalid data IN
(input)
ts(DE)
th(DE)
DEPOL=0
PSSI_DE
(input)
DEPOL=1
tv(RDY) tho(RDY)
PSSI_RDY
RDYPOL=0
(output)
DT63436V1
RDYPOL=1
6.3.34 LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 101 for the LTDC interface are derived from tests
performed under the ambient temperature, frequency and supply voltage conditions summarized in
Table 17. General operating conditions, with the following configuration:
• LCD_CLK polarity: low (signals change on CLK rising edge)
• LCD_DE polarity: low
• LCD_VSYNC and LCD_HSYNC polarity: high
• Pixel formats: 24 bits
• Output speed is set to:
– LTDC Clock: OSPEEDRy[1:0] = 11
– Other LTDC signals: OSPEEDRy[1:0] = 01
• Advanced I/O configurations:
– LTDC Clock: RET = 0, INVCLK = 0, DE = 0, DLYPATH = 0
– Other LTDC signals: RET = 1, INVCLK = 0, DE = 0, DLYPATH = 0
• I/O compensation cell enabled
Table 101. LTDC characteristics

C = 20 pF 148.5
fCLK LTDC clock output frequency - - MHz
C = 30 pF 120
DCLK LTDC clock output duty cycle - 45 - 55 %
DS14284 - Rev 2 page 184/234

tw(CLKH), tw(CLKL) Clock high time, low time - tw(CLK) / 2 - 0.5 - tw(CLK) / 2 + 0.5
tv(DATA) Data output valid time - - - 4
th(DATA) Data output hold time - 1 - -

ns
tv(HSYNC), tv(VSYNC),
HSYNC/VSYNC/DE output valid time - - - 3.5
tv(DE)
th(HSYNC), th(VSYNC),
HSYNC / VSYNC / DE output hold time - 0.5 - -
th(DE)
Figure 45. LCD-TFT horizontal timing diagram
tCLK
LCD_CLK
LCD_VSYNC
tv(HSYNC) tv(HSYNC)
LCD_HSYNC
tv(DE) th(DE)
LCD_DE
tv(DATA)
LCD_R[0:7]
Pixel Pixel Pixel
LCD_G[0:7] 1 2 N
LCD_B[0:7]
th(DATA)
HSYNC Horizontal Horizontal

Active width
width back porch back porch
DT32749V1
One line
DS14284 - Rev 2 page 185/234

Figure 46. LCD-TFT vertical timing diagram
tCLK
LCD_CLK
tv(VSYNC) tv(VSYNC)
LCD_VSYNC
LCD_R[0:7]
LCD_G[0:7] M lines data
LCD_B[0:7]
VSYNC Vertical Vertical

Active width
width back porch back porch
DT32750V1
One frame
6.3.35 Timer characteristics

The parameters given in Table 102 are specified by design, not tested in production.
Refer to Section 6.3.16: I/O port characteristics for details on the input/output alternate function characteristics
(output compare, input capture, external clock, PWM output).
Table 102. TIMx characteristics

TIMx is used as a general term to refer to the TIM1 to TIM20 timers.
tres(TIM) Timer resolution time 1 - tTIMxCLK
fTIMxCLK Timer kernel clock 0 200

MHz
fEXT Timer external clock frequency on CH1 to CH4 0 fTIMxCLK / 2
Timer resolution - 16
ResTIM bit
Timer resolution (TIM2 to TIM5) - 32
Maximum possible count with 16‑bit counters - 65536
tMAX_COUNT tTIMxCLK
Maximum possible count with 32‑bit counter (TIM2 to TIM5) - 65536 × 65536
Table 103. LPTIMx characteristics

LPTIMx is used as a general term to refer to the LPTIM1 to LPTIM5 timers.
tres(LPTIM) Timer resolution time 1 - tLPTIMxCLK
Timer kernel clock 0 100 MHz

fLPTIMxCLK
Timer kernel clock (autonomous mode) 0 32768 Hz
fEXT Timer external clock frequency on IN1 and IN2 0 fLPTIMxCLK/2 MHz
ResLPTIM Timer resolution - 16 bit
tMAX_COUNT Maximum possible count - 65536 tLPTIMxCLK
DS14284 - Rev 2 page 186/234

6.3.36 Communications interfaces
6.3.36.1 I2C interface characteristics

The I2C interface meets the timings requirements of the I2C-bus specification for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s.
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The I2C timings requirements are specified by design, not tested in production, when the I2C peripheral is
properly configured (refer to product reference manual):
The SDA and SCL I/O requirements are met with the following restriction:
• The SDA and SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
All I2C SDA and SCL I/Os embed an analog filter. Refer to Table 104. I2C analog filter characteristics for the
analog filter characteristics:
Table 104. I2C analog filter characteristics

Symbols Parameters Min Max Unit
tAF Maximum pulse width of spikes that are suppressed by the analog filter 50(1) 260(2) ns
1. Spikes with widths below tAF(min) are filtered. At TJ = -40 °C, the guaranteed minimum is 40 ns.
2. Spikes with widths above tAF(max) are not filtered.
6.3.36.2 I3C interface characteristics

The I3C timings are in line with timings requirements of the MIPI® I3C specification v1.1, except for the ones
given in Table 105. This can be mitigated by increasing the corresponding SCL low duration in the I3C_TIMINGR0
register.
The I3C peripheral supports:
• I3C SDR-only as controller
• I3C SDR-only as target
• I3C SCL bus clock frequency up to 12.5 MHz
Unless otherwise specified, the parameters given in Table 105 for the I3C interface are derived from tests
Table 17. General operating conditions, with the following configuration:
Table 105. I3C specific timings

tSU_OD SDA data setup time during Open-Drain mode Controller 19.5 - - ns
tSU_PP SDA sata setup time in Push-Pull mode Controller 15 - - ns
Table 106. I3C pin characteristics

RPU(I3C) I3C pull‑up 1600 2200 2800 Ω
DS14284 - Rev 2 page 187/234

RHK(I3C) I3C high keeper (weak pull‑up) 125 160 195 kΩ
6.3.36.3 SPI interface characteristics

Unless otherwise specified, the parameters given in Table 107 for the SPI interface are derived from tests
characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 107. SPI characteristics


Master mode 1.71 V < VDD < 1.89 V - - 115
Master mode 3.0 V < VDD < 3.6 V - - 105

fSCK SPI clock frequency MHz
Slave receiver mode - - 100
Slave mode transmitter/full duplex - - 41.5(1)

tsu(NSS) NSS setup time Slave mode 4 - -
th(NSS) NSS hold time Slave mode 1 - -
tw(SCKH), tw(SCKL) SCK high and low time Master mode Tpclk - 1 Tpclk Tpclk + 1
tsu(MI) Master mode 4.5 - -

Data input setup time
tsu(SI) Slave mode 3 - -
th(MI) Master mode 1 - -

Data input hold time
th(SI) Slave mode 1 - - ns
ta(SO) Data output access time Slave mode 11 15 15
tdis(SO) Data output disable time Slave mode 12.5 14.5 17.5
tv(MO) Master mode - 3 3.5

Data output valid time
tv(SO) Slave mode - 11.5 12
th(MO) Master mode 2 - -

Data output hold time
th(SO) Slave mode 10 - -
1. Maximum frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or
high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%.
DS14284 - Rev 2 page 188/234

Figure 47. SPI timing diagram - master mode
High
NSS input
tc(SCK)
tw(SCKH)
CPHA=0
SCK output
CPOL=0
CPHA=0
CPOL=1
tw(SCKL)
CPHA=1
SCK output
CPOL=0
CPHA=1
CPOL=1
tsu(MI) th(MI)
MISO input First bit IN Next bits IN Last bit IN

MOSI output First bit OUT Next bits OUT Last bit OUT
DT72626V1
tv(MO) th(MO)
Figure 48. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
DT41658V2
MOSI input First bit IN Next bits IN Last bit IN
DS14284 - Rev 2 page 189/234

Figure 49. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH)
CPHA=1
CPOL=0
SCK input
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
DT41659V2
MOSI input First bit IN Next bits IN Last bit IN
6.3.36.4 I2S interface characteristics

Unless otherwise specified, the parameters given in Table 108 for the I2S interface are derived from tests
• Capacitive load C= 30 pF
characteristics (CK, SD, WS).
Table 108. I2S characteristics

fMCK I2S main clock output - - - 50 MHz
Master mode - - 50
fCK I2S clock frequency Slave transmit mode - - 23 MHz
Slave receive mode - - 50
tv(WS) WS valid time Master mode - - 3.5
th(WS) WS hold time Master mode 2.5 - -
tsu(WS) WS setup time Slave mode 3.5 - -
th(WS) WS hold time Slave mode 3 - -
tsu(SD_MR) Master receiver 4 - -

Data input setup time ns
tsu(SD_SR) Slave receiver 3 - -
th(SD_MR) Master receiver 2.5 - -

th(SD_SR) Slave receiver 1.5 - -
tv(SD_ST) Slave transmitter (after enable edge) - - 13

Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - - 3.5
DS14284 - Rev 2 page 190/234

th(SD_ST) Slave transmitter (after enable edge) 8.5 - -

Data output hold time ns
th(SD_MT) Master transmitter (after enable edge) 0 - -
Figure 50. I2S slave timing diagram (Philips protocol)

CK input
DT14881V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
Figure 51. I2S master timing diagram (Philips protocol)

CK ouput
DT14884V1
1. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.
DS14284 - Rev 2 page 191/234

6.3.36.5 SAI interface characteristics

Unless otherwise specified, the parameters given in Table 109 for SAI are derived from tests performed under the
conditions , with the following configuration:
• Measurement points are performed at CMOS levels: 0.5 × VDD
characteristics (SCK,SD,WS).
Table 109. SAI characteristics

fMCK SAI main clock output - - - 50 MHz
Master transmitter - - 38
Master receiver - - 34
fCK SAI bit clock frequency(1) MHz
Slave transmitter - - 40
Slave receiver - - 50
tv(FS) FS valid time Master mode - - 13
tsu(FS) FS setup time Slave mode 9 - -
Master mode 5.5 - -

th(FS) FS hold time
Slave mode 1 - -
tsu(SD_A_MR) Master receiver 5.5 - -
Data input setup time
tsu(SD_B_SR) Slave receiver 5.5 - -
ns
th(SD_A_MR) Master receiver 1 - -
th(SD_B_SR) Slave receiver 1 - -
tv(SD_B_ST) Data output valid time Slave transmitter (after enable edge) - - 12.5
th(SD_B_ST) Data output hold time Slave transmitter (after enable edge) 8 - -
tv(SD_A_MT) Data output valid time Master transmitter (after enable edge) - - 12.5
th(SD_A_MT) Data output hold time Master transmitter (after enable edge) 8.8 - -
1. APB clock frequency must be at least twice SAI clock frequency.
DS14284 - Rev 2 page 192/234

Figure 52. SAI master timing waveforms
1/fSCK
SAI_SCK_X
th(FS)
SAI_FS_X(output)
tv(FS) tv(SD_MT) th(SD_MT)
SAI_SD_X(transmit) Slot n Slot n+2
tsu(SD_MR) th(SD_MR)
SAI_SD_X(receive) Slot n
DT32771V1
Figure 53. SAI slave timing waveforms
1/fSCK
SAI_SCK_X
tw(CKH_X) tw(CKL_X) th(FS)
SAI_FS_X(input)
tsu(FS) tv(SD_ST) th(SD_ST)
SAI_SD_X(transmit) Slot n Slot n+2
tsu(SD_SR) th(SD_SR)
DT32772V1
SAI_SD_X(receive) Slot n
6.3.36.6 SD/SDIO MMC card host interface (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 110 for the SDIO/MMC interface are derived from tests
• Output speed is set as table below
Table 110. SDMMC GPIO OSPEEDR settings for timing measurements
OSPEEDRy[1:0]
Voltage range (V) Max clock frequency (MHz)
Clock Data
1.71 - 1.89 and 2.7 - 3.6 26/25 00 00
DS14284 - Rev 2 page 193/234

OSPEEDRy[1:0]
Voltage range (V) Max clock frequency (MHz)
Clock Data
52/50 01 00
1.71 - 1.89 and 2.7 - 3.6 DDR 52/50 01 01
100 01 00
2.7 - 3.6 120 11 10
1.71 - 1.89 166 11 10
Table 111. SDMMC characteristics for SD-Card or SDIO usage

VDDIOx = 2.7 V to 3.6 V 0 - 120

fPP Clock frequency in data transfer mode MHz
VDDIOx = 1.71 V to 1.89 V 0 - 166
clock_ratio SDMMC_CK / fpclk frequency ratio - - - 8/3 -

tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -

ns
tW(CKH) Clock high time fPP = 52 MHz 8.5 9.5 -
CMD, D inputs (referenced to CK) in High-Speed/SDR/DDR mode(1)

tISU Input setup time HS - 2 - -
tIH Input hold time HS - 2 - - ns
tIDW (2)
Input valid window (variable window) - 2.5 - -
CMD, D outputs (referenced to CK) in high-speed/SDR/DDR mode(1)

tOV Output valid time HS - - 7.5 8
ns
tOH Output hold time HS - 4.5 - -
CMD, D inputs (referenced to CK) in default mode

tISUD Input setup time SD - 2.5 - -
ns
tIHD Input hold time SD - 2 - -
CMD, D outputs (referenced to CK) in default mode

tOVD Output valid default time SD - - 1 2
ns
tOHD Output hold default time SD - 0 - -
1. SD-Card 3 V / 1.8 V support on SDMMC3 requires an external voltage translator for which timings should be taken into
account.
2. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Table 112. SDMMC characteristics for e•MMC usage

VDDIOx = 2.7 V to 3.6 V 0 - 120

fPP Clock frequency in data transfer mode MHz
VDDIOx = 1.71 V to 1.89 V 0 - 166
clock_ratio SDMMC_CK/fpclk frequency ratio - - - 8/3 -
tW(CKL) Clock low time fPP = 52 MHz 8.5 9.5 -

ns
tW(CKH) Clock high time - 8.5 9.5 -
DS14284 - Rev 2 page 194/234

CMD, D inputs (referenced to CK)

tISU Input setup time HS - 2 - -
tIH Input hold time HS - 2 - - ns
tIDW(1) Input valid window (variable window) - 2.5 - -
CMD, D outputs (referenced to CK)

tOV Output valid time HS - - 7.5 8
ns
tOH Output hold time HS - 4.5 - -
1. The minimum window of time where the data needs to be stable for proper sampling in tuning mode.
Figure 54. SD high-speed mode
tC(CK)
tW(CKH) tW(CKL)
CK
tOH
tOV
D, CMD output
tIH
tISU
DT69709V1
D, CMD input
Figure 55. SD default mode
CK
tOV tOH
D, CMD output DT69710V1
Figure 56. SDMMC DDR mode
D input Valid data Valid data
tISU tIH tISU tIH
tW(CKH)
CK
tW(CKL)
tOV tOV
tOH tOH
DT69158V1
D output Valid data Valid data
DS14284 - Rev 2 page 195/234

6.3.36.7 FDCAN (controller area network) interface

characteristics (FDCANx_TX and FDCANx_RX).
6.3.36.8 Ethernet (ETH) characteristics

Unless otherwise specified, the parameters given in Table 113, Table 114 and Table 115 for ETH interface are
derived from tests performed under the ambient temperature, frequency and supply voltage conditions
summarized in Table 17. General operating conditions, with the following configuration:
• Output speed is set to OSPEEDRy[1:0] = 00 (MII or RMII timings), 11 (MDIO/SMA, RGMII or RGMII-ID
timings)
Table 113. Ethernet MAC timings for MDIO/SMA


tMDC MDC cycle time (2.5 MHz) - - 400 -
td(MDIO) Write data valid time - 0 1 2

ns
tsu(MDIO) Read data setup time - 8 - -
th(MDIO) Read data hold time - 0 - -
Figure 57. Ethernet MDIO/SMA timing diagram
tMDC
ETH_MDC
td(MDIO)
ETH_MDIO(O)
tsu(MDIO) th(MDIO) DT31384V1
ETH_MDIO(I)
Table 114. Ethernet MAC timings for RMII

tsu(RXD) Receive data setup time - 2.5 - -
tih(RXD) Receive data hold time - 1.5 - -
tsu(CRS) Carrier sense setup time - 1.5 - -

ns
tih(CRS) Carrier sense hold time - 1.5 - -
td(TXEN) Transmit enable valid delay time - 7.5 11.5 12.5
td(TXD) Transmit data valid delay time - 7.5 11.5 12.5
DS14284 - Rev 2 page 196/234

Figure 58. Ethernet RMII timing diagram
RMII_REF_CLK
td(TXEN)
td(TXD)
RMII_TX_EN
RMII_TXD[1:0]
tsu(RXD) tih(RXD)
tsu(CRS) tih(CRS)
RMII_RXD[1:0]
DT15667V1
RMII_CRS_DV
Table 115. Ethernet MAC timings for MII

tsu(RXD) Receive data setup time - 3.5 - -

tih(RXD) Receive data hold time - 1 - -
tsu(DV) Data valid setup time - 2 - -
tih(DV) Data valid hold time - 1 - -

ns
tsu(ER) Error setup time - 1 - -
tih(ER) Error hold time - 1 - -
td(TXEN) Transmit enable valid delay time - 7.5 11 12
td(TXD) Transmit data valid delay time - 7.5 11 12
Figure 59. Ethernet MII timing diagram
MII_RX_CLK
tsu(RXD) tih(RXD)
tsu(ER) tih(ER)
tsu(DV) tih(DV)
MII_RXD[3:0]
MII_RX_DV
MII_RX_ER
MII_TX_CLK
td(TXEN)
td(TXD)
DT15668V1
MII_TX_EN
MII_TXD[3:0]
6.3.36.9 USART (SPI mode) interface characteristics

Unless otherwise specified, the parameters given in Table 116 for USART are derived from tests performed under
the ambient temperature, frequency and supply voltage conditions summarized in Table 116 , with the following
configuration:
DS14284 - Rev 2 page 197/234

characteristics (NSS, CK, TX, RX for USART).
Table 116. USART (SPI mode) characteristics

SPI master mode - - 16.5

fCK USART clock frequency SPI slave mode - - 33 MHz
SPI slave receiver mode - - 44
tsu(NSS) NSS setup time SPI slave mode tker + 4(1) - - ns
th(NSS) NSS hold time SPI slave mode 1 - - ns

tw(CKH), tw(CKL) CK high and low time SPI master mode 1 / fCK / 2 - 1 1 / fCK / 2 1 / fCK / 2 + 1 ns
SPI master mode 13 - -

tsu(RX) Data input setup time ns
SPI slave mode 5 - -
th(RX) Data input hold time ns
SPI slave mode 0.5 - -
SPI slave mode - 13.5 14
tv(TX) Data output valid time ns
SPI master mode - 4 4.5
SPI slave mode 7 - -
th(TX) Data output hold time ns
1. tker is the usart_ker_ck_pres clock period defined in the product reference manual.
Figure 60. USART timing diagram in SPI master mode
1/fCK
tw(CKH)
CPHA=0
CK output
CPOL=0
CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output
CPOL=0
CPHA=1
CPOL=1
tsu(RX) th(RX)
RX input MSB IN BIT6 IN LSB IN
TX output MSB OUT BIT1 OUT LSB OUT

DT65386V3
tv(TX) th(TX)
DS14284 - Rev 2 page 198/234

Figure 61. USART timing diagram in SPI slave mode
NSS input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input
CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
tsu(RX) th(RX)
DT65387V3
RX input First bit IN Next bits IN Last bit IN
6.3.37 Embedded PHYs characteristics
6.3.37.1 DDR PHY characteristics
Table 117. DDR PHY characteristics

RZQ External resistor on DDR_ZQ - 237.6 240 242.4 Ω
DDR4, 2400 Mbps, 32‑bit, 10 ACx4, 1 Rank, DBI off

Read - 135 235
Write - 175 290
Idle - 80.5 165
IVDDCORE(DDRPHY)(1) Supply current on VDDCORE mA
DFI_LP - 26 97.5
Inactive - 3.65 70
Retention(2) OFF
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
IVDDA18DDR(1) Supply current on VDDA18DDR mA
DFI_LP - 4.3 -
Inactive - 0.12 0.16
Retention(2) OFF
Read - 415 490

Write - 310 360
Idle - 72 84.5
IVDDQDDR(1) Supply current on VDDQDDR mA
DFI_LP - 2.85 5.5
Inactive - 0.12 1.9
Retention(2) - 0.017 1.7
DS14284 - Rev 2 page 199/234

DDR4, 2400 Mbps, 16‑bit, 10 ACx4, 1 Rank, DBI off

Read - 93.5 160
Write - 115 190
Idle - 65 125
DFI_LP - 22 70
Inactive - 3.65 70
Retention(2) OFF
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
DFI_LP - 4.3 -
Retention(2) OFF
Read - 235 275

Write - 180 215
Idle - 37 43
DFI_LP - 1.9 3.6
Retention(2) - 0.017 1.2
DDR3L, 2133 Mbps, 32‑bit, 10 ACx4, 1 Rank

Read - 130 210
Write - 170 275
Idle - 76.5 150
DFI_LP - 25 86.5
Inactive - 3.6 60
Retention(2) OFF
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
DFI_LP - 4.3 -
Retention(2) OFF
Read - 420 475

Write - 475 530
Idle - 71.5 79.5
DFI_LP - 3.25 5.85
Inactive - 0.135 2
Retention(2) - 0.0225 1.75
DDR3L, 2133 Mbps, 16‑bit, 10 ACx4, 1 Rank

Read - 88.5 145
Write - 110 175
DS14284 - Rev 2 page 200/234

Idle - 62.5 115

DFI_LP - 21 62.5
Inactive - 3.6 60
Retention(2) OFF
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
DFI_LP - 4.3 -
Retention(2) OFF
Read - 245 275

Write - 270 305
Idle - 39.5 44.5
DFI_LP - 2.15 3.85

Retention(2) - 0.0225 1.2
LPDDR4, 2400 Mbps, 32‑bit, 10 ACx4, 1 Rank, DBI off

Read - 140 245
Write - 165 285
Idle - 73 160
DFI_LP - 25 99
Retention(2) OFF
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
DFI_LP - 4.3 -
Retention(2) OFF
Read - 125 150

Write - 480 545
Idle - 49.5 57.5
DFI_LP - 2.6 4.85
Retention(2) - 0.0185 1.55
LPDDR4, 2400 Mbps, 16‑bit, 10 ACx4, 1 Rank, DBI off

Read - 91 160
Write - 110 185
IVDDCORE(DDRPHY) (1) Supply current on VDDCORE Idle - 59.5 120 mA

DFI_LP - 22 70
DS14284 - Rev 2 page 201/234


IVDDCORE(DDRPHY)(1) Supply current on VDDCORE Retention(2) OFF mA
Read - 4.3 -
Write - 4.3 -
Idle - 4.3 -
DFI_LP - 4.3 -
Retention(2) OFF
Read - 110 125

Write - 285 325
Idle - 48.5 56
DFI_LP - 1.7 3.2
Retention(2) - 0.0185 1.1

Low power exit latency

DFI_
Exit latency from DFI_LP state - - 2 -
CLK
DDR3L, DDR4 - 3 -
Exit latency from inactive state 3 + 2560

LPDDR4 - DDR_CL -
tEXIT
K
μs
DDR3L, DDR4 - 3 -
Exit latency from retention state after 3 + 2560
supplies restored LPDDR4 - DDR_CL -
K

2. VDDCORE OFF, VDDA18DDR OFF.
6.3.37.2 DSI PHY Characteristics
Table 118. DSI PHY characteristics

fCK DSI link clock frequency High-Speed mode (HS) 40 - 1250 MHz
rate Data rate per lane High-Speed mode (HS) 80 - 2500 Mbps
UI Unit interval equal to 0.5 / fCK (HS) 0.4 - 12.5 ns
REXT External resistor on REXT Connected to ground 198 200 202 Ω
4 lanes @1 Gbps - 1.55 9.6
High-Speed 4 lanes @1.5 Gbps - 2.05 11

Transmit(3) 4 lanes @2 Gbps - 2.55 11.5
(1)
Supply current on
IVDDCORE(DSIPHY) 4 lanes @2.5 Gbps - 3.05 12.5 mA
VDDCORE(2)
Lane 0 @10 Mbps,
LP Transmit - 2.05 10.5
PLL @2.5 Gbps
ULPS Transmit PLL disabled - 0.155 8.05
DS14284 - Rev 2 page 202/234

High-Speed
4 lanes - 5.35 9.55
Transmit(3)
Supply current on
IVDDA18DSI Lane 0 @10 Mbps, mA
VDDA18DSI(2) LP Transmit - 3.85 5.05
PLL @2.5 Gbps
4 lanes @1Gbps - 14.5 19
High-Speed 4 lanes @1.5 Gbps - 17 23

Transmit(3) 4 lanes @2 Gbps - 19.5 26.5
IVDDDSI Supply current on VDDDSI 4 lanes @2.5 Gbps - 22.5 30 mA
Lane 0 @10 Mbps,

LP Transmit - 7.45 10.5
PLL @2.5 Gbps

2. values includes PLL power consumption.
3. HS mode: assume PRBS9 pattern on data lanes and 100% occupation; that is, continuous HS.
6.3.37.3 CSI PHY Characteristics
Table 119. CSI PHY characteristics

REXT External resistor on REXT Connected to ground 198 200 202 Ω
2 lanes @1 Gbps - 2.8 12

2 lanes @1.5 Gbps - 3.7 13
High-speed receive(2)
2 lanes @2 Gbps - 4.7 14.5
IVDDCORE(CSIPHY)(1) Supply current on VDDCORE mA
2 lanes @2.5 Gbps - 5.7 15.5
LP receive Lane 0 @10 Mbps - 0.71 8
ULPS receive ck_ker_csi2phy stopped - 0.35 8.4
2 lanes @1 Gbps - 2.2 2.85
2 lanes @1.5 Gbps - 2.3 3
2 lanes @2 Gbps - 2.6 3.35
IVDDA18CSI(1) Supply current on VDDA18CSI mA
2 lanes @2.5 Gbps - 2.6 3.35
LP receive Lane 0 @10Mbps - 1.7 2.3
2 lanes @1 Gbps - 3.95 5.1
2 lanes @1.5 Gbps - 4.5 5.8
2 lanes @2 Gbps - 3.8 5.5
IVDDCSI(1) Supply current on VDDCSI mA
2 lanes @2.5 Gbps - 4.3 6
LP receive Lane 0 @10 Mbps - 0.9 1.5

2. HS mode: assume PRBS9 pattern on data lanes and 100% occupation; that is, continuous HS.
DS14284 - Rev 2 page 203/234

6.3.37.4 LVDS PHY Characteristics
Table 120. LVDS PHY characteristics

LVDS lane characteristics

VOH Output voltage high -(1) 1350 1400 1450 mV
VOL Output voltage low -(1) 995 1000 1050 mV
|VOD| Output differential voltage -(1) 340 370 420 mV
VOS Output offset voltage -(1) 1150 1200 1250 mV
RO Output impedance, single ended -(1) 44 60.5 76.5 Ω
∆RO Ro mismatch between P and N output - - - 8 %
|∆VOD| Change in |VOD| between 0 and 1 - 0.42 - 2.6 mV
∆VOS Change in VOS between 0 and 1 -(1) 0.22 2.55 26 mV

Static current on 100Ω differential load 2.6 3.3 3.6 mA

Is Output current (drawn from VDDA18LVDS) Outputs shorted to ground 11 15 24 mA
Outputs shorted together 2.25 3.25 8.05 mA
tf VOD fall time, 20 – 80%(3)(4) -(1) 205 245 320 ps
tr VOD rise time, 20 – 80%(3)(4) -(1) 205 255 320 ps
ppVOD Dynamic output signal balance(3)(4) -(2) 41 72 125 mV
LVDS bandgap characteristics

IVDDA18LVDS Bandgap supply current on VDDA18LVDS - - - 0.805 1.25 mA
IVDDLVDS Bandgap supply current on VDDLVDS - - - 3.25 3.95 mA
1. Steady state (~ DC level) @ lowest possible data rate (2 Mbps) with both voltage and current driver enabled.
2. At maximum speed with both voltage and current driver enabled.
3. Loading conditions are: two 50Ω resistors, two 2.5 pF caps at each output, one 2.5 pF cap at middle point.
4. Specification for default configuration (no pre-emphasis).
6.3.37.5 USB2PHY Characteristics
Table 121. USB high-speed PHY characteristics

External resistor on
RTXRTUNE Connected to ground 198 200 202 Ω
TXRTUNE
HS transmit, maximum transition density(2) - 10 27
HS transmit, minimum transition density(3) - 8.15 23.5
HS idle(4) - 9.25 23
IVDDCORE(USB2 Supply current on
FS transmit, maximum transition density(5) - 9.2 27.5 mA
PHY)
(1) VDDCORE
LS transmit, maximum transition density(6) - 7.85 20
Suspend(7) - 0.038 6.05
Sleep(8) - 2.45 13
DS14284 - Rev 2 page 204/234

VDATDETENB = 0,
- 2.4 11.5
IVDDCORE(USB2 Supply current on VDATSRCENB = 1(9)
Battery charging mA
PHY)
(1) VDDCORE
VDATDETENB = 1,
- 4.75 15.5
VDATSRCENB = 1
HS transmit, maximum transition density(2) - 16.5 18.5
HS idle(4) - 4.9 5.85
FS transmit, maximum transition density(5) - 4.9 5.9
Supply current on LS transmit, maximum transition density(6) - 5.1 6.15

IVDDA18USB(1) mA
VDDA1V8USB Suspend(7) - 0.024 0.0945
Sleep(8) - 0.031 0.0945
VDATDETENB = 0,
- 3.55 4.55
VDATSRCENB = 1(9)
Battery charging
VDATDETENB = 1,
- 4.3 5.4
VDATSRCENB = 1
HS transmit, maximum transition density(2) - 3.05 3.2
HS idle(4) - 2.1 2.4
FS transmit, maximum transition density(5) - 12.5 16
Supply current on LS transmit, maximum transition density(6) - 12 16.5

IVDD33USB(1) mA
VDD33USB Suspend(7) - 0.029 0.0785
Sleep(8) - 0.067 0.115
VDATDETENB = 0,
- 2.1 2.4
VDATSRCENB = 1(9)
Battery charging
VDATDETENB = 1,
- 2.1 2.4
VDATSRCENB = 1

2. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM). Loading of 10 pF.
Transfers do not include any interpacket delay.
3. Packet transmission by one transceiver operating in device mode while driving all 1s data (alternating 7-bit strings of J, then K on DP/DM).
Loading of 10 pF. Transfers do not include any interpacket delay.
4. HS receive mode with no traffic on the line.
5. Packet transmission by one transceiver operating in device mode while driving all 0s data (constant JKJK on DP/DM). Loading of 50 pF.
6. Packet transmission by one transceiver operating in host mode while driving all 0s data (constant JKJK on DP/DM). Loading of 600 pF.
7. Suspend when operating in device mode with no far-side host termination on DP/DM during measurements. Measurements taken when
COMMONONN (SYSCFG_USB2PHYxCR.USB2PHYxCMN) is deasserted.
8. Sleep mode when operating in device mode with no far-side host termination on DP/DM during measurements.
9. PHY is in suspend (with clocks turned OFF), non-driving mode and operating as a portable device in the 'dead battery' condition.
6.3.37.6 COMBOPHY Characteristics
Table 122. COMBOPHY characteristics

REXT(1) External resistor on REXT Connected to ground 198 200 202 Ω
DS14284 - Rev 2 page 205/234

5 Gbps - 23.5 38
P0 mode
2.5 Gbps - 14 37.5
5 Gbps - 16.5 33
P0s mode
2.5 Gbps - 13 28
5 Gbps - 9.7 24.5
P1 mode
2.5 Gbps - 9.7 24.5
IVDDCOMBOPHY Supply current on VDDCOMBOPHY mA
P1.CPM - - 1.45 14.5
P1.1 - - 0.215 12.5
P1.2 - - 0 12
P2 - - 9.6 15
P2.CPM - - 1.2 14
Power down - - 0.15 13
5 Gbps - 11 14
P0 mode
2.5 Gbps - 6.4 8.9

5 Gbps - 1.4 2.4
P0s mode
2.5 Gbps - 1.4 2.4
5 Gbps - 1.4 2.4
P1 mode
Supply current on 2.5 Gbps - 1.4 2.4
IVDDCOMBOPHYTX mA
VDDCOMBOPHYTX P1.CPM - - 1.45 2.4
P1.1 - - 1.45 2.4
P1.2 - - 0.005 0.405
P2 - - 1.45 1.9
P2.CPM - - 0.005 0.41
Power down - - 0.01 0.425
5 Gbps - 25 29
P0 mode
2.5 Gbps - 17.5 24
5 Gbps - 14.5 20.5
P0s mode
2.5 Gbps - 14 19.5
5 Gbps - 8.4 11.5
P1 mode
Supply current on 2.5 Gbps - 8.4 11.5
IVDDA18COMBOPHY mA
VDDA18COMBOPHY P1.CPM - - 2.35 2.75
P1.1 - - 2.2 2.55
P1.2 - - 0.375 0.785
P2 - - 14 16.5
P2.CPM - - 0.54 0.985
Power down - - 0.01 0.0305
Minimum number of FTS ordered sets that must be sent for retraining when
NFTS(1) 48 - - FTS
transitioning from P0s to P0
5 Gbps - - 48
tP0s_to_P0 Time from pipe powerdown change to P0 ns
2.5 Gbps - - 96
5 Gbps - - 0.9
tP1_to_P0 Time from pipe powerdown change to P0 μs
2.5 Gbps - - 1.8
DS14284 - Rev 2 page 206/234

100 MHz
tP2_to_P0 Time from pipe powerdown change to P0 - - 260 μs
reference clock
tP0_to_P2 Time from pipe powerdown change to P2 - - - 250 ns
100 MHz
tP2_to_P1 Time from pipe powerdown change to P1 - - 255 μs
reference clock
Time from pipe reset de-assertion to PHY 100 MHz
tReset_to_ready - - 255 -
acknowledgment reference clock
Time from phy_mpll_en assertion to when 100 MHz
tMPLL_lock - - 15 μs
phy_mpll_state is high reference clock
tResistor_tuning Time to complete a resistor tune - - - 8 -
tCommon_mode Time to establish Common mode when exiting reset or P2 state - - 240 μs
tP1.1_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 -
tP1.2_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 μs
Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion and

tP1.2_to_P1_to_P0 - - 16.8 -
pipeN_powerdown request to P0 until PHY acknowledgment
tP1.CPM_to_P1 Time from macN_pclkreq_n assertion to pipeN_clkreq_n assertion - - 15 μs
Time for the Common mode voltage to be reached on pins while

transmitting in Recovery mode. This parameter applies to an exit from P1.2
tCOMMON_MODE_REC - - 55 μs
through P1 to P0 (Recovery) and represents the extra time in which the
MAC is required to send TS1 ordered sets.
Table 123. PCIE REFCLKGEN characteristics

Symbol(1) Parameter Conditions Min Typ Max Unit
IVDDPCIECLK Power consumption on VDDPCIECLK 100 MHz clock - - 3 mA
IMP_CTRL = 0b11000 52 61 70
IMP_CTRL = 0b11001 48 56.5 65
IIMP_CTRL = 0b11010 45 53 64
IMP_CTRL = 0b11011 (default) 42 49.5 57.5
ZO Single ended output impedance Ω
IMP_CTRL = 0b11100 40 47 54
IMP_CTRL = 0b11101 37.5 44.5 51
IMP_CTRL = 0b11110 35.5 42 48.5
IMP_CTRL = 0b11111 34 40 46
IMP_CTRL[4:3] = 0b00000 - 55 -
IMP_CTRL[4:3] = 0b01000 - 70 -
IMP_CTRL[4:3] = 0b10000 - 85 -
IMP_CTRL[4:3] = 0b11000 - 100 -
IMP_CTRL[4:3] = 0b00001 - 66 -
VSWING Singled ended swing in % of VDDPCIECLK %
IMP_CTRL[4:3] = 0b01001 - 77 -
IMP_CTRL[4:3] = 0b10001 - 89 -
IMP_CTRL[4:3] = 0b11001 - 100 -
IMP_CTRL[4:3] = 0b00010 - 61 -
IMP_CTRL[4:3] = 0b01010 - 74 -
DS14284 - Rev 2 page 207/234

Symbol(1) Parameter Conditions Min Typ Max Unit
IMP_CTRL[4:3] = 0b10010 - 87 -
IMP_CTRL[4:3] = 0b11010 - 100 -
IMP_CTRL[4:3] = 0b00011 - 70 -
IMP_CTRL[4:3] = 0b01011 - 90 -
IMP_CTRL[4:3] = 0b10011 - 80 -
IMP_CTRL[4:3] = 0b11011 (default) - 100 - %
IMP_CTRL[4:3] = 0b00100 - 58 -
IMP_CTRL[4:3] = 0b01100 - 70 -
IMP_CTRL[4:3] = 0b10100 - 85 -
IMP_CTRL[4:3] = 0b11100 - 100 -
IMP_CTRL[4:3] = 0b00101 - 68 -
VSWING Singled ended swing in % of VDDPCIECLK
IMP_CTRL[4:3] = 0b01101 - 79 -
IMP_CTRL[4:3] = 0b10101 - 90 -
IMP_CTRL[4:3] = 0b11101 - 100 -

IMP_CTRL[4:3] = 0b00110 - 64 -
IMP_CTRL[4:3] = 0b01110 - 76 -
IMP_CTRL[4:3] = 0b10110 - 88 - %
IMP_CTRL[4:3] = 0b11110 - 100 -
IMP_CTRL[4:3] = 0b00111 - 71 -
IMP_CTRL[4:3] = 0b01111 - 80 -
IMP_CTRL[4:3] = 0b10111 - 90 -
IMP_CTRL[4:3] = 0b11111 - 100 -
tr/tf Rise and Fall time(2) (3) (4) 0.6 - 4 V/ns
VCROSS Absolute crossing point voltage(5)(6)(7) 250 400 550 mV
∆VCROSS Variation of VCROSS over all rising clock edges(5)(6)(8) - - 140 mV
Duty_Cycle Duty cycle(2) 40 50 60 %
Matching Rising edge rate to falling edge rate matching(5)(9) - - 20 %
1.
2. PCIE_CLKOUTP and PCIE_CLKOUTN are to be measured at the load capacitors CL. Single ended probes must be used
for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be
used for differential measurements. Test load CL = 2 pF.
3. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIE_CLKOUTP minus PCIE_CLKOUTN).
The signal must be monotonic through the measurement region for rise and fall time. The 300 mV measurement window is
centered on the differential zero crossing.
4. Measurement taken from differential waveform.
5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all
crossing points for this measurement.
6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIE_CLKOUTP equals the falling
edge of PCIE_CLKOUTN.
7. Measurement taken from single ended waveform.
8. Defined as the total variation of all crossing voltages of rising PCIE_CLKOUTP and falling PCIE_CLKOUTN. This is the
maximum allowed variance in VCROSS for any particular system.
9. Matching applies to rising edge rate for PCIE_CLKOUTP and falling edge rate for PCIE_CLKOUTN. It is measured using a
± 75 mV window centered on the median cross point where PCIE_CLKOUTP rising meets PCIE_CLKOUTN falling. The
median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
rise edge rate of PCIE_CLKOUTP should be compared to the fall edge rate of PCIE_CLKOUTN, the maximum allowed
difference should not exceed 20% of the slowest edge rate.
DS14284 - Rev 2 page 208/234

6.3.37.7 UCPDPHY Characteristics
Table 124. UCPDPHY characteristics

fBITRATE Bit rate (ensured by adequate RCC and UCPD settings) 270 300 330 Kbps
CRECEIVER Local capacitance added on PCB on each CC line 200 470 600 pF
TRANSMITTER
Voltage swing applies on CC pin to both no load condition and under the load
VSWING 1.05 1.125 1.2 V
condition.
TX output impedance. Source output impedance at the Nyquist frequency of
ZDRIVER 33 - 75 Ω
USB2.0 low speed (750 kHz) while the source is driving the CC line.
Rise / Fall Time. 10% to 90% / 90% to 10% amplitude points, minimum is under
Tr / Tf 300 - 735 ns
an unloaded condition. Maximum set by TX mask.
TX duty cycle at 0.5625 V (see Y5Tx , BMC Tx 'ONE' mask and BMC Tx 'ZERO'
DCYCLE 47 - 53 %
mask in the PD Specification)(1)
RECEIVER
VIL - - 0.4825
sourcing power V
VIH Rx receive input thresholds. The position of the center line of the 0.8925 - -
inner mask is dependent on whether the receiver is sourcing or
VIL sinking power or is power neutral(1) - - 0.2325
sinking power
VIH 0.6425 - - V
Hysteresis Rx receive input hysteresis 0.15 - -

Number of transitions for signal detection (number to count to detect non-idle
NCOUNT(2) 3 - - -
bus).
tTRANWIN(2) Time window for detecting non-idle bus. 12 - 20 µs
ZBMCRX(3) Receiver input impedance 1 - - MΩ
1. Refer to the "USB Power Delivery (PD) Specification" Revision 3.1, Version 1.8.
2. BMC packet collision is avoided by the detection of signal transitions at the receiver. Detection is active when a minimum of
NCOUNT transitions occur at the receiver within a time window of tTRANWIN. After waiting tTRANWIN without detecting
NCOUNT transitions, the bus is declared idle. This times are informative for UCPDPHY as it is done digitally inside UCPD
Peripheral.
3. Does not include pull-up or pull-down resistance from cable detect. Transmitter is Hi‑Z.
6.3.38 JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 125 and Table 126 for JTAG/SWD are derived from
tests performed under the ambient temperature, frequency and VDD supply voltage summarized in
DS14284 - Rev 2 page 209/234

Table 125. JTAG dynamic characteristics

Fpp
TCK clock frequency - - - 45 MHz
1/tc(TCK)
tisu(TMS) TMS input setup time - 2 - -
tih(TMS) TMS input hold time - 1 - -
tisu(TDI) TDI input setup time - 3 - -

ns
tih(TDI) TDI input hold time - 0.5 - -
tov (TDO) TDO output valid time - - 9 11
toh(TDO) TDO output hold time - 7 - -
Figure 62. JTAG timing diagram

tc(TCK)
TCK
tsu(TMS/TDI) th(TMS/TDI)
tw(TCKL) tw(TCKH)
TDI/TMS
tov(TDO) toh(TDO)
DT40458V1
TDO
Table 126. SWD dynamic characteristics

Fpp SWCLK
- - - 80 MHz
1/tc(SWCLK) clock frequency
tisu(SWDIO) SWDIO input setup time - 1.5 - -
tih(SWDIO) SWDIO input hold time - 2.5 - -

ns
tov (SWDIO) SWDIO output valid time - - 9 12.5
toh(SWDIO) SWDIO output hold time - 5 - -
DS14284 - Rev 2 page 210/234

Figure 63. SWD timing diagram
tc(SWCLK)
SWCLK
tsu(SWDIO)
th(SWDIO) twSWCLKL) tw(SWCLKH
SWDIO )
(receive)
tov(SWDIO) toh(SWDIO)
SWDIO
(transmit)
DT40459V1
DS14284 - Rev 2 page 211/234

Package information
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 Device marking

Refer to technical note "Reference device marking schematics for STM32 microcontrollers and microprocessors"
(TN1433 ) available on www.st.com, for the location of pin 1 / ball A1 as well as the location and orientation of the
marking areas versus pin 1 / ball A1.
Parts marked as "ES", "E" or accompanied by an engineering sample notification letter, are not yet qualified and
therefore not approved for use in production. ST is not responsible for any consequences resulting from such use.
In no event will ST be liable for the customer using any of these engineering samples in production. ST’s Quality
department must be contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package information subsection.
7.2 VFBGA361 package information (B09U)

This VFBGA is a 361-ball, 10 x 10 mm, very thin fine pitch ball grid array package.
DS14284 - Rev 2 page 212/234

Package information
Figure 64. VFBGA361 - Outline
E1
SE
W
V
U e
T
R
P
N
M
L
K D1
J
H
G
F SD
E
D
C
B
A
b (N balls)
1 3 5 7 9 11 13 15 17 19
A1 corner
2 4 6 8 10 12 14 16 18 C A B
eee M
fff M C
BOTTOM VIEW
A3 ccc C A2
Seating plane
C
ddd C A1 A5
FRONT VIEW
E
A1 corner B
(Datum A)
D
B09U_VFBGA361_ME__V1
aaa C
(4x)
(Datum B)
A
TOP VIEW
DS14284 - Rev 2 page 213/234

Package information
Table 127. VFBGA361 - Mechanical data
millimeters inches(1)
Symbol
Min Typ Max Min Typ Max
A(2) - - 1.00 - - 0.0394
A1(3) 0.155 - - 0.0061 - -
b(4) 0.260 0.310 0.360 0.0102 0.0122 0.0142
D(5) 10.00 BSC 0.3937 BSC
D1 9.000 BSC 0.3543 BSC

E 10.00 BSC 0.3937 BSC
E1 9.000 BSC 0.3543 BSC
e(6) 0.500 BSC 0.0197 BSC
N(7) 361
SD(8) 0.500 0.0197
SE(8) 0.500 0.0197

aaa(9) 0.150 0.0059
ccc(9) 0.200 0.0079
ddd(9) 0.080 0.0031
eee(9) 0.150 0.0059
fff(9) 0.050 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. The profile height, A, is the distance from the seating plane to the highest point on the package. It is measured
perpendicular to the seating plane
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension b is measured at the maximum diameter of the terminal (ball) in a plane parallel to primary datum C.
5. BSC stands for BASIC dimensions. It corresponds to the nominal value and has no tolerance. For tolerances refer to form
and position table
6. e(x) represents the solder ball grid pitch(es).
7. N represents the total number of balls on the BGA.
8. Basic dimensions SD(x) & SE(y) are defined with respect to datums A and B. They define the position of the centre ball(s) of
the ball matrix.
9. Tolerance of form and position drawing.
7.3 VFBGA424 package information (B0MP)

This VFBGA is a 424-ball, 14 x 14 mm, very thin fine pitch ball grid array package.
DS14284 - Rev 2 page 214/234

Package information
Figure 65. VFBGA424 - Outline

E1
SE1
SE e1
e
1 2 3 4 5 6 7 8 9 10 11 12
AG
AF
AE
AD
AC
AB
AA
Y 1M
W 1L
V 1K
SD1 U 1J
T 1H
R 1G
P e1 D1
1F
N 1E
SD M 1D
L 1C
K 1B
J 1A
H
G
F
E
D
C e
B
A
1 3 5 7 9 11 13 15 17 19 21 23 25 27
2 4 6 8 10 12 14 16 18 20 22 24 26
A1 BALL
PAD CORNER
b (N BALLS)
eee M C A B
fff M C
BOTTOM VIEW
ddd C A ccc C
A3
SEATING PLANE(2)
A1
A2 A5
C
SIDE VIEW
A
B E
A1 BALL
PAD CORNER(3)
D
(DATUM A)
(DATUM B)
B0MP_VFBGA424_ME_V1
aaa C
TOP VIEW (4X)
1. Drawing is not to scale.

2. Primary datum C is defined by the plane established by the contact points of three or more solder balls that
support the device when it is placed on top of a planar surface.
DS14284 - Rev 2 page 215/234

Package information
3. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is
allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner
is optional.
Table 128. VFBGA424 - Mechanical data
Symbol
A(2) - - 1.000 - - 0.0394
A1(3) 0.155 - - 0.0061 - -
b(4) 0.260 0.310 0.360 0.0102 0.0122 0.0142
D(5) 14.000 BSC 0.5512 BSC
D1(5) 13.000 BSC 0.5118 BSC
E(5) 14.000 BSC 0.5512 BSC
E1(5) 13.000 BSC 0.5118 BSC

e(5)(6) 0.500 BSC 0.0197 BSC
e1(5)(6) 1.000 BSC 0.0394 BSC
N(7) 424
SD(5)(8) 0.500 BSC 0.0197 BSC
SE(5)(8) 0.500 BSC 0.0197 BSC
SD1(5)(8) 0.250 BSC 0.0098 BSC
SE1(5)(8) 0.250 BSC 0.0098 BSC
aaa(9) 0.150 0.0059
ccc(9) 0.200 0.0079
ddd(9) 0.100 0.0031
eee(9) 0.150 0.0059
fff(9) 0.050 0.0020

and position table
the ball matrix.
7.4 TFBGA436 package information (B0MS)

This TFBGA is a 436-ball, 18 x 18 mm, thin fine pitch ball grid array package.
DS14284 - Rev 2 page 216/234

Package information
Figure 66. TFBGA436 - Outline

E1
e
SE
AB
AA
Y
e
W
V
U
T
R
P
N
M
D1
L
K
SD
J
H
G
F
E
D
C
B
1 3 5 7 9 11 13 15 17 19 21 b (436 BALLS)
2 4 6 8 10 12 14 16 18 20 22
eee C A B
BOTTOM VIEW fff C
ddd C A
A3
SEATING
PLANE(2)
A1
A5
C SIDE VIEW
A
B E
A1 BALL
PAD CORNER(3)
D
(DATUM A)
(DATUM B)
B0MS_TFBGA436_ME_V2_V2
aaa C
TOP VIEW (4X)
1. Drawing is not to scale.

2. Primary datum C is defined by the plane established by the contact points of three or more solder balls that
support the device when it is placed on top of a planar surface.
3. The terminal (ball) A1 corner must be identified on the top surface of the package by using a corner chamfer,
ink or metallized markings, or other feature of package body or integral heat slug. A distinguish feature is
allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner
is optional.
DS14284 - Rev 2 page 217/234

Package information
Table 129. TFBGA436 - Mechanical data
Symbol
A(2) - - 1.20 - - 0.0472
A1(3) 0.240 - - 0.0094 - -
b(4) 0.380 0.430 0.480 0.0150 0.0169 0.0189
D(5) 18.000 BSC 0.7087 BSC
D1(5) 16.800 BSC 0.6614 BSC
E(5) 18.000 BSC 0.7087 BSC
E1(5) 16.800 BSC 0.6614 BSC
e(5)(6) 0.800 BSC 0.0315 BSC
N(7) 436
SD(5)(8) 0.400 BSC 0.0157 BSC
SE(5)(8) 0.400 BSC 0.0157 BSC

aaa(9) 0.150 0.0059
ccc(9) 0.200 0.0079
ddd(9) 0.150 0.0059
eee(9) 0.150 0.0059
fff(9) 0.080 0.0031

and position table
the ball matrix.
Figure 67. TFBGA436 - Footprint example

DT_BGA_WLCSP_FT_V1
Dpad
Dsm
DS14284 - Rev 2 page 218/234

Package information
Table 130. TFBGA436 - Example of PCB design rules
Dimension Values
Pitch 0.8 mm
Dpad 0.320 mm
Dsm 0.420 mm typ. (depends on soldermask registration tolerance)
Stencil opening 0.320 mm
Stencil thickness 0.125 to 0.100 mm
7.5 Package thermal characteristics

The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated using the following
equation:
T J max = TA max + PD max × Θ JA
where:
• TA max is the maximum ambient temperature in °C.
• ΘJA is the package junction-to-ambient thermal resistance in °C/W.
• PD max is the sum of PINT max and PI/O max:

PD max = PINT max + PI/O max
• PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.
PI/O max represents the maximum power dissipation on output pins:
PI/O max = VOL × IOL + VDDIOx − VOH × IOH
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.
Table 131. Package thermal characteristics
Symbol Parameter Package Value Unit
VFBGA361 10×10 mm 23.1

ΘJA Thermal resistance junction-ambient VFBGA424 14×14 mm 20.9
TFBGA436 18×18 mm 19.5
VFBGA361 10×10 mm 9.5
ΘJB Thermal resistance junction-board VFBGA424 14×14 mm 11.8 °C/W
TFBGA436 18×18 mm 11.6
VFBGA361 10×10 mm 5.7
ΘJC Thermal resistance junction-top case VFBGA424 14×14 mm 5.5
TFBGA436 18×18 mm 5.4
7.5.1 Reference documents

• JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
available on www.jedec.org.
• For information on thermal management, refer to application note "Guidelines for thermal management on
STM32 applications" (AN5036) available on www.st.com.
DS14284 - Rev 2 page 219/234

Ordering information
8 Ordering information
Example: STM32 MP 257 F AI 3 ␣ T
Device family
STM32 = Arm® -based 32- or 64-bit processor
Product type
MP = MPU product
Device subfamily
251 = STM32MP251 line
Security option
C = Secure boot, cryptography hardware, 1.2 GHz CPU1, 800 MHz GPU(1)
F = Secure boot, cryptography hardware, 1.5 GHz CPU1, 900 MHz GPU(1)
Package and ball count

AL = VFBGA361 10x10, 361 balls pitch 0.5 mm
AK = VFBGA424 14x14, 424 balls pitch 0.5 mm
AI = TFBGA436 18x18, 436 balls pitch 0.8 mm
Junction temperature range

3 = -40 °C < TJ < +125 °C
Options
␣ (absent) = no options
Packing
T = Tape and reel
No character = tray or tube
1. GPU is absent in some devices (see Section 2 for details).
Note: For a list of available options (such as speed and package) or for further information on any aspect of this
device, contact your nearest ST sales office.
DS14284 - Rev 2 page 220/234

Ordering information
Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security, which is why the ST
product(s) identified in this documentation may be certified by various security certification bodies and/or may
implement our own security measures as set forth herein. However, no level of security certification and/or built-in
security measures can guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an ST product meets the
customer needs both in relation to the ST product alone, as well as when combined with other components and/or
software for the customer end product or application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such as Platform
Security Architecture (www.psacertified.org) and/or Security Evaluation standard for IoT Platforms
(www.trustcb.com). For details concerning whether the ST product(s) referenced herein have received
security certification along with the level and current status of such certification, either visit the relevant
certification standards website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can change from time to
time, customers should re-check security certification status/level as needed. If an ST product is not shown
to be certified under a particular security standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in relation to ST
products. These certification bodies are therefore independently responsible for granting or revoking
security certification for an ST product, and ST does not take any responsibility for mistakes, evaluations,
assessments, testing, or other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open standard
technologies which may be used in conjunction with an ST product are based on standards which were not
developed by ST. ST does not take responsibility for any flaws in such cryptographic algorithms or open
technologies or for any methods which have been or may be developed to bypass, decrypt or crack such
algorithms or technologies.
• While robust security testing may be done, no level of certification can absolutely guarantee protections
against all attacks, including, for example, against advanced attacks which have not been tested for,
against new or unidentified forms of attack, or against any form of attack when using an ST product outside
of its specification or intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance against such
attacks. As such, regardless of the incorporated security features and/or any information or support that
may be provided by ST, each customer is solely responsible for determining if the level of attacks tested for
meets their needs, both in relation to the ST product alone and when incorporated into a customer end
product or application.
• All security features of ST products (inclusive of any hardware, software, documentation, and the like),
including but not limited to any enhanced security features added by ST, are provided on an "AS IS"
BASIS. AS SUCH, TO THE EXTENT PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL
WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
DS14284 - Rev 2 page 221/234

Revision history
Table 132. Document revision history
Date Revision Changes
19-Mar-2024 1 Initial release.

Updated Communication peripherals, Camera interface #1 and Graphics in
Section Features.
Updated Section 2: Description including Table 3. STM32MP25xC/F differences
per packages and Figure 1. STM32MP25xC/F block diagram.
Updated Section 3.4: Graphic processing unit (GPU).
Updated Section 3.7: DDR3L/DDR4/LPDDR4 controller (DDRCTRL).
Updated Table 5. Boot sources.
Updated Section 3.35: Digital camera interface with pixel processing (DCMIPP).
Updated Section 3.37: LCD-TFT display controller (LTDC).
Updated Section 3.39: LVDS display interface (LVDS).
Updated Table 8. USART/UART features.
Updated Table 19. Embedded reset and power control block characteristics.
Updated Table 20. Embedded reference voltage characteristics.
Updated Table 21. Embedded reference voltage calibration value.
Updated Table 22 to Table 34 in Section 6.3.5.1: Typical and maximum current
consumption.
Updated Table 35. D1 (CPU1) low-power mode wakeup timings.
Updated Table 36. D2 (CPU2) low-power mode wakeup timings.
Updated Table 40. Low-speed external (LSE) user clock characteristics (digital
bypass).
Updated Section 6.3.7.3: High-speed external clock generated from a crystal/
27-Jun-2024 2 ceramic resonator including Table 42. High-speed external (HSE) oscillator
characteristics.
Updated Table 43. Low-speed external (LSE) oscillator characteristics.
Updated Table 47. MSI oscillator characteristics.
Updated Table 48. LSI oscillator characteristics.
Updated Table 49. PLL1 to PLL8 characteristics.
Updated Table 62. Output voltage characteristics for all I/Os.
Updated Table 79. Synchronous multiplexed PSRAM write timings.
Updated Figure 29. NAND controller waveforms for read access.
Updated Figure 30. NAND controller waveforms for write access.
Updated Section 6.3.20: OCTOSPI interface characteristics including Table 82 to
Table 84.
Updated Table 86. ADC characteristics.
Updated Table 87. ADC accuracy.
Updated Table 89. VREFBUF characteristics.
Updated Table 93. Voltage monitoring characteristics (VDDCORE, VDDCPU,
VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4, VDD33USB, VDD33UCPD).
Updated Table 94. Compensation cell characteristics.
Updated Section 6.3.29: Multi-function digital filter (MDF) characteristics including
Table 95. MDF characteristics.
Updated Section 6.3.30: Audio digital filter (ADF) characteristics including
Table 96. ADF characteristics.
DS14284 - Rev 2 page 222/234

Date Revision Changes

Updated Section 6.3.31: Camera interface (DCMI) characteristics including
Table 97. DCMI characteristics.
Updated Section 6.3.32: Camera interface (DCMIPP) characteristics.
Updated Section 6.3.33: Parallel interface (PSSI) characteristics including
Table 99. PSSI transmit characteristics and Table 100. PSSI receive
characteristics.
Updated Section 6.3.36.1: I2C interface characteristics including Table 104. I2C
analog filter characteristics.
Updated Section 6.3.36.4: I2S interface characteristics including Table 108. I2S
characteristics.
Updated Section 6.3.36.5: SAI interface characteristics including Table 109. SAI
characteristics.
Updated Section 6.3.36.8: Ethernet (ETH) characteristics including
Table 113. Ethernet MAC timings for MDIO/SMA, Table 114. Ethernet MAC
timings for RMII, Table 115. Ethernet MAC timings for MII.
Updated Section 6.3.36.9: USART (SPI mode) interface characteristics including
Table 116. USART (SPI mode) characteristics.
Updated Section 6.3.37.2: DSI PHY Characteristics.
Updated Section 6.3.37.4: LVDS PHY Characteristics.

Updated Table 121. USB high-speed PHY characteristics.
Updated Table 122. COMBOPHY characteristics.
Updated Section 6.3.38: JTAG/SWD interface characteristics including
Table 125. JTAG dynamic characteristics and Table 126. SWD dynamic
characteristics.
Updated Section 7.5: Package thermal characteristics.
DS14284 - Rev 2 page 223/234

Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1 Dual-core Arm Cortex-A35 subsystem (CA35SS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Arm Cortex-M33 core with TrustZone and FPU (CM33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Arm Cortex-M0+ core (CM0P). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Graphic processing unit (GPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Neural processor unit (NPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6.1 External SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6.2 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7 DDR3L/DDR4/LPDDR4 controller (DDRCTRL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.9 Power supply management (PWR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.9.2 Power-supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.10 Low-power strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Resource isolation framework (RIF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.2 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.12.3 Reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13 Hardware semaphore (HSEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14 Inter-processor communication controller (IPCC1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 General-purpose input/outputs (GPIO). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.16 Bus-interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 High-performance DMA controllers (HPDMA1/2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.18 Low-power DMA controller (LPDMA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.19 Cortex-M33 nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.20 Cortex-M0+ nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.21 Extended interrupt and event controller (EXTI1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.22 Cyclic redundancy check calculation unit (CRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS14284 - Rev 2 page 224/234

Contents
3.23 Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.24 Octo-SPI memory interface (OCTOSPI1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.25 On-the-fly decoder (OTFDEC1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26 Octo-SPI I/O manager (OCTOSPIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.27 Analog-to-digital converters (ADC1/2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.28 Digital temperature sensor (DTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.29 VBAT operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.30 Voltage reference buffer (VREFBUF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.31 Multifunction digital filter (MDF1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.32 Audio digital filter (ADF1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.32.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.33 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.34 Parallel synchronous slave interface (PSSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.35 Digital camera interface with pixel processing (DCMIPP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.36 Camera serial interface (CSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.37 LCD-TFT display controller (LTDC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.38 Display serial interface (DSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.39 LVDS display interface (LVDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.40 Video encoder (VENC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.41 Video decoder (VDEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.42 True random number generator (RNG ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.43 Hash processor (HASH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.44 Cryptographic processor (CRYP1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.45 Secure AES (SAES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.46 Public key accelerator (PKA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.47 Boot and security and OTP control (BSEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.48 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.48.1 Advanced-control timers (TIM1/8/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.48.2 General-purpose timers (TIM2/3/4/5/10/11/12/13/14/15/16/17) . . . . . . . . . . . . . . . . . . . . . 38
3.48.3 Basic timers (TIM6/TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.48.4 Low-power timer (LPTIM1/2/3/4/5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.48.5 Independent watchdog (IWDG1/2/3/4/5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.48.6 System window watchdog (WWDG1/2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.48.7 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.48.8 Cortex-A35 generic timers (CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Contents
3.49 System timer generation (STGEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

3.50 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.51 Tamper and backup registers (TAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.52 Inter-integrated circuit interface (I2C1/2/3/4/5/6/7/8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.53 Improved inter-integrated circuit (I3C1/2/3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.54 Universal synchronous asynchronous receiver transmitter (USART1/2/3/6,
UART4/5/7/8/9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.55 Low-power universal asynchronous receiver transmitter (LPUART1) . . . . . . . . . . . . . . . . . . 42
3.56 Serial peripheral interface (SPI1/2/3/4/5/6/7/8) inter-integrated sound interfaces
(I2S1/2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.57 Serial audio interfaces (SAI1/2/3/4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.58 SPDIF receiver interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.59 Secure digital input/output MultiMediaCard interface (SDMMC1/2/3) . . . . . . . . . . . . . . . . . . 44
3.60 Controller area network (FDCAN1/2/3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.61 Universal serial bus Hi-Speed host (USBH). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.62 USB Type-C Power Delivery controller (UCPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.63 Universal serial bus 3.0 dual role data (USB3DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.64 PCI Express interface (PCIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.65 5-Gbit/s PHY controller (COMBOPHY). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.66 Gigabit Ethernet MAC interface (ETH1/2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.67 Gigabit Ethernet switch (ETHSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.68 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4 Pinouts/ballouts, pin description, and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . .48
4.1 Ballout schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.2 Ball description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.3 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
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Contents
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.6 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
6.3.8 External clock source security characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.9 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
6.3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
6.3.11 PLL spread spectrum clock generation (SSCG) characteristics . . . . . . . . . . . . . . . . . . . 143
6.3.12 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
6.3.13 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

6.3.14 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.15 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
6.3.16 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
6.3.17 NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.18 DDR IOs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
6.3.19 FMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
6.3.20 OCTOSPI interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
6.3.21 Delay block (DLYB) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
6.3.22 12-bit ADC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
6.3.23 Voltage reference buffer (VREFBUF) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.24 Digital Temperature Sensor (DTS) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
6.3.25 VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics . . . . . . . . . . . . . . 175
6.3.26 Temperature and VBAT monitoring characteristic for tamper detection. . . . . . . . . . . . . . . 175
6.3.27 Voltage monitoring characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
6.3.28 Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.29 Multi-function digital filter (MDF) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
6.3.30 Audio digital filter (ADF) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
6.3.31 Camera interface (DCMI) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
6.3.32 Camera interface (DCMIPP) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.3.33 Parallel interface (PSSI) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
6.3.34 LCD-TFT controller (LTDC) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
6.3.35 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
6.3.36 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
6.3.37 Embedded PHYs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
DS14284 - Rev 2 page 227/234

Contents
6.3.38 JTAG/SWD interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

7 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.2 VFBGA361 package information (B09U) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
7.3 VFBGA424 package information (B0MP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
7.4 TFBGA436 package information (B0MS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
7.5 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.5.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
DS14284 - Rev 2 page 228/234

List of tables
List of tables
Table 1. STM32MP25xC/F features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
Table 2. STM32MP25xC/F differences per product lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9
Table 3. STM32MP25xC/F differences per packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Default interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Boot sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Minimum set of default pins used during boot ROM phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 8. USART/UART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 9. I/O power domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 10. Legend/abbreviations used in the ballout table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11. STM32MP25xC/F ball definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 12. Alternate functions AF0 to AF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 13. Alternate functions AF8 to AF15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 14. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 15. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 16. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 17. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 18. Operating conditions at power-up / power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 19. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 20. Embedded reference voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 21. Embedded reference voltage calibration value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 22. Current consumption (IDDCORE) in Run modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 23. Current consumption (IDDCPU) in Run modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
Table 24. Current consumption (IDDGPU) in Run modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 25. Current consumption (IDD) in Run modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Table 26. Current consumption (IDDA18) in Run modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 27. Current consumption (IDDA18AON) in Run modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 28. Current consumption (IBAT) in Run modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 29. Current consumption in Stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 30. Current consumption in LPLV-Stop modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 31. Current consumption in Standby1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 32. Current consumption in Standby2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 33. Current consumption in VBAT1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 34. Current consumption in VBAT2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 35. D1 (CPU1) low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 36. D2 (CPU2) low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 37. Wakeup time using USART/LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Table 38. High-speed external (HSE) user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 39. High-speed external (HSE) user clock characteristics (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 40. Low-speed external (LSE) user clock characteristics (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Table 41. Low-speed external (LSE) user clock characteristics (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 42. High-speed external (HSE) oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Table 43. Low-speed external (LSE) oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Table 44. High-speed external user clock security system (HSE CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 45. Low-speed external user clock security system (LSE CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 46. HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 47. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 49. PLL1 to PLL8 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 50. PLL_USB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 51. PLL_DSI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Table 52. PLL_LVDS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
DS14284 - Rev 2 page 229/234

List of tables
Table 53. PLL2 to PLL8 SSCG parameters constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Table 54. OTP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 55. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 56. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1200 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 57. EMI characteristics for fHSE = 40 MHz and FPLL1 = 1500 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 58. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 59. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 60. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 61. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 62. Output voltage characteristics for all I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 63. Output timing characteristics (VDD = 3.0 - 3.6 V or VDDIOx = 2.7 - 3.6 V, VDDIOxVRSEL = 0) . . . . . . . . . . . . . . 148
Table 64. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 1) . . . . . . . . . . . . . . . . . . . . . . . 149
Table 65. Output timing characteristics (VDD/VDDIOx = 1.71 - 1.89 V, VDDIOxVRSEL = 0 degraded mode) . . . . . . . . . . . 150
Table 66. GPIO advance config delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 67. NRST pin characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 68. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 69. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 70. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 71. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . 155

Table 72. Asynchronous multiplexed PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 73. Asynchronous multiplexed PSRAM/NOR read - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 74. Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 75. Asynchronous multiplexed PSRAM/NOR write - NWAIT timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Table 76. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 77. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Table 78. Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Table 79. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 80. NAND flash read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 81. NAND flash write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 82. OCTOSPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Table 83. OCTOSPI characteristics in DTR mode (without DQS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 84. OCTOSPI characteristics in DTR mode (with DQS or HyperBus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 85. DLYB characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 86. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 87. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 88. Minimum sampling time versus RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Table 89. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 90. DTS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 91. VBAT, VDDCPU, VDDCORE, VDDGPU ADC measurement characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 92. TEMP and VBAT Monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Table 93. Voltage monitoring characteristics (VDDCORE, VDDCPU, VDDGPU, PVD_IN, VDDA18ADC, VDDIO1/2/3/4, VDD33USB,
VDD33UCPD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 94. Compensation cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 95. MDF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 96. ADF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 97. DCMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 98. DCMIPP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 99. PSSI transmit characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 100. PSSI receive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 101. LTDC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 102. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 103. LPTIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 104. I2C analog filter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 105. I3C specific timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
DS14284 - Rev 2 page 230/234

List of tables
Table 106. I3C pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

Table 107. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Table 108. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Table 109. SAI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 110. SDMMC GPIO OSPEEDR settings for timing measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 111. SDMMC characteristics for SD-Card or SDIO usage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 112. SDMMC characteristics for e•MMC usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. Ethernet MAC timings for MDIO/SMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 114. Ethernet MAC timings for RMII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Table 115. Ethernet MAC timings for MII. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Table 116. USART (SPI mode) characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 117. DDR PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 118. DSI PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 119. CSI PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 120. LVDS PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 121. USB high-speed PHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 122. COMBOPHY characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 123. PCIE REFCLKGEN characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 124. UCPDPHY characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 125. JTAG dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

Table 126. SWD dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 127. VFBGA361 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 128. VFBGA424 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Table 129. TFBGA436 - Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Table 130. TFBGA436 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 131. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Table 132. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
DS14284 - Rev 2 page 231/234

List of figures
List of figures
Figure 1. STM32MP25xC/F block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 2. AXI STNoC multi-frequency network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3. MCU multi-Layer AHB 400 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 4. MCU multi-Layer AHB 200 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. SmartRun multi-Layer AHB matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 6. STM32MP25xC/F VFBGA361 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 7. STM32MP25xC/F VFBGA424 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 8. STM32MP25xC/F TFBGA436 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 11. Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 12. Current consumption measurement scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 13. High-speed external clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 14. High-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 15. Low-speed external clock source AC timing diagram (digital bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 16. Low-speed external clock source AC timing diagram (analog bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Figure 17. Typical application with a 40 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Figure 18. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Figure 19. VIL/VIH for TT I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 20. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 23. Asynchronous multiplexed PSRAM/NOR read waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Figure 24. Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 25. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 26. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 27. Synchronous multiplexed NOR/PSRAM read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 28. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 29. NAND controller waveforms for read access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Figure 30. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 31. OCTOSPI timing diagram - SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Figure 32. OCTOSPI timing diagram - DTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 33. OCTOSPI HyperBus clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 34. OCTOSPI HyperBus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Figure 35. OCTOSPI HyperBus read with double latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 36. OCTOSPI HyperBus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Figure 37. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Figure 38. Typical connection diagram using the ADC with TT pins featuring analog switch function . . . . . . . . . . . . . . . 173
Figure 39. MDF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Figure 40. ADF timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Figure 41. DCMI timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Figure 42. DCMIPP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 43. PSSI transmit timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 44. PSSI receive timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Figure 45. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 46. LCD-TFT vertical timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 47. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 48. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Figure 49. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 50. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 51. I2S master timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Figure 52. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 53. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
DS14284 - Rev 2 page 232/234

List of figures
Figure 54. SD high-speed mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 55. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 56. SDMMC DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Figure 57. Ethernet MDIO/SMA timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 58. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 59. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 60. USART timing diagram in SPI master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 61. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 62. JTAG timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 63. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Figure 64. VFBGA361 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Figure 65. VFBGA424 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 66. TFBGA436 - Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 67. TFBGA436 - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
DS14284 - Rev 2 page 233/234

IMPORTANT NOTICE – READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
DS14284 - Rev 2 page 234/234

STM 32 MP 257 F

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STM32MP251C/F STM32MP253C/F

VFBGA361 (10 × 10 mm) pitch 0.5 mm Cores

Product summary – Up to 400 MHz

• Secure boot, TrustZone® peripherals, active tamper, environmental monitors,

Reset and power management

DS14284 - Rev 2 - June 2024 www.st.com

• Controls for PMIC companion chip

– 128-, 64-, 32-bit STNoC interconnect, up to 600 MHz

4 DMA controllers to unload the CPU

• 8× I2C FM+ (1 Mbit/s, SMBus/PMBus®)

DS14284 - Rev 2 page 2/234

• Camera interface #1 (5 Mpixels @30 fps)

• Optional 3D GPU: VeriSilicon® - Up to 900 MHz

• Optional NPU: VeriSilicon® - Up to 900 MHz

Up to 34 timers and 7 watchdogs

DS14284 - Rev 2 page 3/234

• 2× SysTick Cortex®-M33 timer (secure, non-secure)

• Arm® CoreSight™ trace and debug: SWD and JTAG interfaces

12288-bit fuses including 96-bit unique ID

All packages are ECOPACK2 compliant

DS14284 - Rev 2 page 4/234

DS14284 - Rev 2 page 5/234

running at up to 900 MHz.

DS14284 - Rev 2 page 6/234

• two Octo-SPI flash memory interface , with on-the-fly content decryption

Table 1. STM32MP25xC/F features and peripheral counts

VFBGA361 (10×10 pitch 0.5 mm),

TFBGA436 (18×18 pitch 0.8 mm)(1)

- Cortex-M33 FPU TrustZone

Video Encoder (VENC) JPEG 500 Mpixel/s(1)

Video RAM Up to 128 Kbytes(1)

CPU system Up to 384 Kbytes(1)

DS14284 - Rev 2 page 7/234

Low power 16 bits 5

4 (up to 8 audio channels), with I2S master/

Embedded PHYs 3 (2× Hi-Speed + 1x SuperSpeed 5 Gbps)

SDMMC (SD, SDIO, e•MMC)(2) 3 (8 + 8 + 4 bits).

OCTOSPI(2) 2, with AES-128 (CTR) decryption (OTFDEC)

Parallel address/data 8/16 bits 4× CS, up to 4x 64 Mbytes(1)

FMC Parallel AD-Mux 8/16 bits 4× CS, up to 4x 64 Mbytes(1)

NAND 8/16 bits(2) Yes, 4 x CS, SLC, BCH4/8(1)

Gigabit Ethernet interfaces Up to 3(1)

DS14284 - Rev 2 page 8/234

16-bit input or output, path shared with DCMI

Multi-function digital filter (MDF) 8 input channels with 8 filters

with interrupt (total count) Up to 172(1)

GPIOs Wake-up pins Up to 6(1)

Tamper input/active output pins Up to 8 inputs and 8 outputs(1)

ADC channels in total (differential) Up to 23 channels (or 11 differential)(1)

1. See next tables for details.

Table 2. STM32MP25xC/F differences per product lines

Feature STM32MP251x STM32MP253x STM32MP255x STM32MP257x

Cortex-A35 FPU Neon TrustZone Single-core Dual-core

GPU 800 MHz, up to 133 Mtriangle/s or

DS14284 - Rev 2 page 9/234

Feature STM32MP251x STM32MP253x STM32MP255x STM32MP257x

Frequency - 600 MHz

CPU system 256 + 128 Kbytes 256 Kbytes(3)

Gigabit External interfaces 1, R(G)MII, MII 2, R(G)MII, MII 3, R(G)MII