U.S.N.

B.M.S. College of Engineering, Bengaluru-560019

Autonomous Institute Affiliated to VTU

May 2023 Semester End Main Examinations

Programme: B.E. Semester: III

Branch: Electronics and Communication Engineering Duration: 3 hrs.
Course Code: 22EC3PCDSD Max Marks: 100
Course: Digital System Design Date: 08.05.2023

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may be suitably assumed.

UNIT - I
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank

1 a) Simplify the given function using K-Map. Implement the simplified logic 07
function using basic gates.
𝐹(𝑊, 𝑋, 𝑌, 𝑍) = ∑ 𝑚(3,5,6,7,8,9,10) + 𝑑𝑐(4,11,12,14,15)
b) Explain the Verilog data types with syntax and example. 07
c) Explain the port connections rules followed in Verilog HDL programming. 06
pages. Revealing of identification, appeal to evaluator will be treated as malpractice.

UNIT - II
2 a) Derive logic expressions for 2-bit magnitude comparator and implement the 12
same using Verilog data flow description.

b) Design a 16x1 Multiplexer using 4x1 multiplexer. Write the truth table of 4x1 08
and 16x1 multiplexer.
UNIT - III
3 a) Design an N-bit Asynchronous counter with JK flip-flop using Verilog 10
generate statement.
b) Explain the Verilog HDL case statements. Apply the concept of case 10
statement, write the Verilog code to implement the encoder represented by the
following truth table. Also write the test bench to test the functioning of the
encoder given.
Input(a) Output(b)
xxx1 1
xx10 2
x100 4
1000 8
Others 0
OR
4 a) Below is a block with nested sequential and parallel blocks. Analyze, when 10
does the block finish, what is the order of execution of events and at what
simulation time does each statement finish execution?
 always
begin
#4 Dry = 5;
fork
#6 Cun = 7;
begin
Exe = Box;
#5 Jap = Exe;
end
#2 Dop = 3;
#4 Gos = 2;
#8 Pas = 4;
join
#8 Bax = 1;
#2 Zoom = 52;
#6 $stop ;
end

b) Explain Verilog loop statements with syntax and example. Generate the clock 10
pulse of time period 40ns with 10% duty cycle using forever statement.
Initially clock is at logic 1 at 0ns.
UNIT - IV
5 a) Design synchronous counter for sequence: 0 → 1 → 3 → 4 → 5 → 7 → 0 10
using T flip-flop. Assume the unused sequences don’t care.
b) Derive the characteristic equation of JK flip-flop. 05
c) Implement SR flip-flop using Verilog behavioral description. 05

OR
6 a) Design a 4-bit universal shift register using a multiplexer and flip-flop to 10
perform the operation as given in the below table. Explain the design with a
relevant flip-flop and multiplexer truth table.

S0 S1 Mode of Operation
0 0 No-Change
0 1 Shift-left
1 0 Shift-Right
1 1 Parallel-load

b) Convert D flip-flop to T flip-flop. 05

c) Implement a counter to count the sequence 0-3-7-2-0 using Verilog HDL 05
behavioral description.
 UNIT - V
7 a) Analyze the synchronous sequential circuit given in fig 1, write the transition 10
table and state diagram.

fig 1
b) Design a Moore sequence detector to detect the sequence 11011 using Verilog 10
behavioral description by considering non-overlapping condition for the
sequence.

******