B 1100ECT303L22204

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Reg No.:

APJ ABDUL KI.LAM TECHNOLOGICAL UNryERSITY

Fifth Semester B.Tech Degree Regular and Supplementary Examination Dec 2022 (20

Course Code: ECT 303

Course Name: DIGITAL SIGNAL PROCESSING

Max. Marks: 100 Duration:3 Hours

PART A
(Answer all questions; each question carries 3 marks) Marks

Compute the DFT of the sequence x[n] : (j)" Ui=rtd(n - /c))l a

J

Explain Digital signal processing system with a block diagram. J

Discuss the need for FFT. Justify your answer in terms of computational J

complexity, memory requirement etc.

4 Find the DFT of the sequence using DIT FFT algorithm x[n] : { l, -1, 0} a
J

5 Compare FIR and IIR filters. J

TRACE KTU
a
6 Analog transfer function of a digital filter is given by (") = *. Comment J

on the stability of the filter. Obtain the digital transfer function of the same
using impulse invariance method. Where sampling time is T.
What is Multirate signal processing? Obtain interpolated and decimated
versions for the sequence x[n] : {1, 2, 3, 4, 5, 6, 7, 8} by a factor 2.
I
8 Obtain the direct form structure for the FIR filter with transfer function J

H(z) = I.* 2z-1 * 3z-2 * 4z-3 * ;z-a I 6z-6 * 7z-7

a
9 What is meant by pipelining? Give its significance in DSP processors. J

"10 The effect of ADC quantization noiq=e plays very important role in DSP r3
processors. Justifu.

(Answer onefull qaestionfro* *r"fffii*, each question corries 14 marks)

Module -1
I I a) State the following properties of DFT (i) Linearity (ii) Time Reversal
(iii) Parseval's theorem
b) Jllustrate the concept of circular convolution property of a DFT sequence
for the discrete time sequences x[n] : {1,2, I, 2}, h[n] : {2, 4, 6,8}

Page 1 of 3
 11008CT303122204

12 a) What is the significance of zero padding? If number of zeros are padded on 6

(i) Left of the signal (ii) Right of the signal. Comment on its effect on the
sPectrum.

b) Find the linear convolution sum of the sequence x[n] = {1,2, -1,2,3, -2, 8

-3, -L, l, 1,2, -l ) and h[n] : {1,2\ using overlap add method'
Module -2
- 13 a) Write down the principle of in-place computation in FFT. 4

b) Compute the IDFT of the sequence X[k] = {1, -1, l, -1, 1, -1, l, -1} using l0
DIT algorithm.
14 a) Explain the principle of DIF FFT algorithm and obtain the final flow graph 10

for the same.

,.
b) Findthe4-pointDFTof sequencesx[n]: {1,2,0' l} and 4

y[n] : {2,2,1,1} by computing the 4-point DFT only once'

Module -3
15 a) Design a Butterworth filter using bilinear transformation. l0

Specifications of desired LPF are

TRACE KTU 0.707<lH(w)l

lH(w)l <
<1;
3TI
0.2, 4 =w 3II
0t*'Z
n

Given that T= I sec.

4
t'
b) Explain Gibbs Phenomenon.
16 a) Forthe desired frequency response 8

(.^3n3n
----:- Ha(a) = < a <Z'
le-t",-T
( 0, otherwise
Y Determine for N = 7 using rectangular window. t
b) Explain the principle of fr.qu.nry*?rnpling technique for FIR filter 6

design.
Module -4
17 a) Obtain direct form I, direct form II and parallel form structure for the 10

system
L7
- t) + |t(n - 2) + x(n) + x(n - L)
y(n) =
1t("
b) Write a short note on anti-aliasing filter and anti-imaging filter 4

Page 2 of 3
 *,
tr#csmt?;E's4

l8 a) Obtainthe casc* fsm relisatioarsing dircct fs.m II 7

H(z) =
r 2+z-1 +z-2

b) Write down the principle of line,ar phsse in FIR filts with a struchue. 7

Moduh -5
19 a) With a detailed block diag.attu explain the architecture of typioal DSF l0
proccssor family TMS3 2rc67XX.
s., Writc a short note on truncation and rounding with examples? 4
2$ a) fu are the variqrs data form*s in DSP pnocessors? Exphia wifh t
sui8t*e o<amples.
b) MAC # .'kt sfffi P processor. Justiff .

'l

TRACE KTU

Page3d3
DSP – December 2022 (Solutions)
2)

 Input is an analog signal . Analog input signal is fed to a sample and hold device which basically consists of a
switch which samples the analog input at periodic intervals and holds the sampled value constant for some time
so that it can be converted to a digital form, because conversion from analog to digital requires time.
 Input to the A/D converter is a staircase type analog signal from the S/H circuit. After the A/D conversion, we get
a coded signal, whose usual form is binary. This is then processed by a digital processor. DSP combine the
signals by multiplication, addition and by recalling past signals, through delays. There are basically three
operations: delay, multiplication, and addition.
 The output of the digital processor is also digital, a sequence of numbers or a binary data stream, and in order for
that output to be useful, we must convert it back to analog form. So you have a D/A or digital to analog converter.
 The undesired high frequency components present in the signal will be removed by an analog low pass filter, and
finally the desired processed analog output is the one that is delivered at its output.

3)

 The N – point DFT values can be computed only in a total of N2 complex mul plica ons and N(N-1) complex
addi ons
 Direct computa on of DFT is basically inefficient primarily because it does not exploit the symmetry and
periodicity proper es of the phase factor Wn
 FFT is a highly efficient procedure for compu ng the DFT of a finite series and requires less number of
computa ons than that of direct evalua on of DFT
 FFT is based on decomposi on and breaking the transform into smaller transforms and combining them to
get the total transform
 FFT reduces the computa on me required to compute DFT and improves the performance by a factor 100
or more over direct evalua on of the DFT .FFT algorithm makes use of the symmetry and periodicity property
of twiddle factor and reduces the number of complex mul plica ons required to perform DFT from N2 to
 𝑵 /𝟐 𝒍𝒐𝒈𝟐𝑵 and the number of complex addi ons from N(N – 1) to 𝑵𝒍𝒐𝒈𝟐N

5)

FIR
 FIR filters have a finite impulse response, meaning that their output se les to zero in a finite amount of me
a er the input signal is removed.
 FIR filters are characterized by a feedforward structure without feedback. They only use present and past
inputs to calculate the current output.
 Common design methods for FIR filters include windowing, frequency sampling, and op miza on
techniques.
 Computa onal complexity: Typically higher due to larger number of taps (coefficients)
 FIR filters are inherently stable because they lack feedback loops, making them less prone to stability issues
compared to IIR filters
 FIR filters can achieve linear phase responses, which means that all frequency components of the input
signal experience the same delay, making them suitable for applica ons sensi ve to phase distor on, like
audio processing.
IIR
 IIR filters have an infinite impulse response, meaning that their output can have an infinite dura on even a er
the input signal is removed.
 IIR filters have feedback loops in their structure, allowing past outputs to affect the current output, making them
more computa onally efficient for achieving a desired response with fewer coefficients.
 Common design methods for IIR filters include Bu erworth, Chebyshev designs, which are based on analog filter
prototypes and transformed into the digital domain.
 Computa onal complexity: Lower due to fewer taps required to achieve similar responses
 IIR filters can be more suscep ble to stability issues, especially in certain configura ons or when not designed
carefully due to the presence of feedback loops
 IIR filters o en introduce phase distor on due to their feedback structure, resul ng in non-linear phase
responses across different frequency components

7) Mul rate signal processing involves manipula ng signals at different rates. This can include opera ons such as
upsampling (interpola on) and downsampling (decima on).

Upsampling (Interpola on):

Interpola on involves inser ng zeros between the original samples and then applying a low-pass filter to reconstruct
the signal. The interpolated sequence, xi[n], is obtained by inser ng a zero between each pair of original samples:

xi[n]={1,0,2,0,3,0,4,0,5,0,6,0,7,0,8}

Downsampling (Decima on):

Decima on involves reducing the number of samples in a sequence. The decimated sequence, xd[n], is obtained by
selec ng every second sample from the original sequence:

xd[n]={1,3,5,7}

9) Pipelining a processor means breaking down its instruc on into a series of discrete pipeline stages which can be
completed in sequence by specialized hardware. Because an instruc on's Lifecycle consists of four dis nct phases,
the instruc on execu on process is divided into a sequence of four discrete pipeline stages, where each pipeline
stage corresponds to a phase in the standard instruc on Lifecycle. Note that the number of pipeline stages is referred
to as the pipeline depth.

Pipelining leads to drama c improvements in system performance. The more stages that we can break the pipeline
into, the more theore cal speed we can get from it.

 Increased Throughput
 Reduced Latency
 Efficient Resource Utilization
 Improved Instruction-Level Parallelism
 Optimized Hardware Utilization
 Support for Real-Time Processing
 Scalability
 Parallelism Exploitation
10) Effects of adc quan sa on errors are :

 Signal Accuracy: ADC quan za on introduces errors due to the finite number of representable levels, impac ng
the accuracy of the digi zed signal in DSP applica ons.
 Dynamic Range Limita on: Quan za on limits the dynamic range of the signal, affec ng the ability to represent
both small and large amplitude components accurately.
 Noise Introduc on: Quan za on noise is inherent and introduces undesired components into the signal,
influencing the quality of subsequent signal processing opera ons.
 Signal-to-Noise Ra o (SNR): Quan za on affects the SNR, a cri cal metric in DSP, as the ra o between the signal
power and quan za on noise power determines the fidelity of the processed signal.
 Distor on in Signal Processing: The quan za on error contributes to distor on during signal processing,
impac ng applica ons such as audio processing and communica on systems.
 Bit Resolu on Impact: The number of bits in the ADC determines the resolu on, and a lower bit resolu on
results in coarser quan za on, reducing the precision of digi zed signals.
 Error Accumula on: In cascaded processing stages, quan za on errors accumulate, poten ally degrading the
overall performance of DSP algorithms over me.

11 a) LINEARITY :

b) Time reversal:

C) PARSEVALS THEOREM :

12 A)
Zero padding involves adding zeros to the beginning or end of a signal to adjust its length

Spectral Leakage Reduc on:

Zero padding reduces spectral leakage, a phenomenon where energy from one frequency leaks into adjacent
frequencies during the DFT computa on. This is par cularly beneficial in obtaining more accurate frequency
informa on.

Improved Frequency Resolu on:

Both le and right zero padding contribute to enhanced frequency resolu on, allowing for be er iden fica on and
localiza on of frequency components in the signal.

Trade-off with Computa onal Cost:

While zero padding improves spectral analysis, it comes with a trade-off in terms of computa onal cost. Longer
signals require more computa on, so the choice of zero padding should consider the balance between resolu on
improvement and computa onal efficiency.

 Le zero padding does not alter the original part of the signal but extends it by adding zeros at the beginning.In
the frequency domain (spectrum), le zero padding shi s the spectrum to the right, effec vely increasing the
resolu on of the spectral analysis.
 Right zero padding extends the signal by adding zeros at the end.In the frequency domain, right zero padding
does not alter the posi on of the original spectrum but increases the length of the frequency representa on.

13 a)

 FFT is based on decomposi on and breaking the transform into smaller transforms and combining them to get
the total transform
 FFT reduces the computa on me required to compute DFT and improves the performance by a factor 100 or
more over direct evalua on of the DFT
 FFT algorithm makes use of the symmetry and periodicity property of twiddle factor and reduces the number of
complex mul plica ons required to perform DFT from N2 to 𝑵/ 𝟐 𝒍𝒐𝒈𝟐𝑵 and the number of complex addi ons
from N(N – 1) to 𝑵𝒍𝒐𝒈𝟐𝑵
 There are basically 2 classes of FFT algorithms:
1. Decima on in Time (DIT) FFT algorithm
2. Decima on in Frequency (DIF) FFT algorithm
 By adop ng a divide and conquer approach, a computa onally efficient algorithm can be developed This
approach depends on the decomposi on of an N – point DFT into successively smaller size DFTs
 An N – point sequence, if N can be expressed as N = r1 r2 r3 ,…..,rm where r1 = r2 = r3 = …. = rm, then N = r m ,
can be decimated into r – point sequences ➢ For each r-point sequence, r-point DFT can be computed
 The number r is called radix of the FFT algorithm and the number m indicates the number of stages in
computa on
 From r-point DFT, the r 2 - point DFT are computed from which r 3 – point DFTs are computed and so on un l r m
– point DFT is computed

14 a)
14 b)
15 a)
15 b)
16 b)

FREQUENCY SAMPLING:

 In this method, the desired frequency response is sampled at sufficient number of points (N points)
 These samples are the DFT coefficients of impulse response of the filter.
 Hence impulse response of the filter is determined by taking inverse DFT
17 b)

ALIASING EFFECT:

 The spectrum obtained a er downsampling will overlap if the original spectrum is not band limited to 𝝎 = 𝝅/𝑴
This overlap causes aliasing. Therefore aliasing due to downsampling a signal by a factor of M is absent if and
only if the signal x(n) is band limited to ± 𝝅 /𝑴
 If the signal x(n) is not band limited to ± 𝝅/ 𝑴 , then a low pass filter with a cut-off frequency 𝝅/ 𝑴 is used prior
to downsampling This filter is known as an – aliasing filter . The complete process i.e., filtering and then
downsampling is referred to as decima on.

IMAGING EFFECT :

 The frequency spectrum of upsampled signal y(n) with a factor L, contains (L- 1) addi onal images of the input
spectrum. These (L-1) images are due to the addi on of L -1 zero samples between successive samples of x(n).
 Since we are not interested in image spectrum, a lowpass filter with a cut off frequency of 𝝎𝑪 = 𝝅 /𝑳 can be used
a er upsampler
 This filter which is used to remove the image spectrum is known as an -imaging filter. ➢ The complete process
of upsampling and filtering is known as interpola on.

18 b)
19 a)

TMS320C67xx DSP Architecture

The C6000 devices come with program memory, which, on some devices, can be used as a program cache. The
devices also have varying sizes of data memory. Peripherals such as a direct memory access (DMA) controller, power-
down logic, and external memory interface (EMIF) usually come with the CPU, while peripherals such as serial ports
and host ports are on only certain devices. Central Processing Unit (CPU)

The C67x CPU, is common to all the C62x/C64x/C67x devices.

The CPU contains:

 Program fetch unit
 Instruc on dispatch unit
 Instruc on decode unit
 Two data paths, each with four func onal units
 32 32-bit registers
 Control registers
 Control logic
 Test, emula on, and interrupt logic
The program fetch, instruc on dispatch, and instruc on decode units can deliver up to eight
32-bit instruc ons to the func onal units every CPU clock cycle. The processing of
instruc ons occurs in each of the two data paths (A and B), each of which contains four
func onal units (.L, .S, .M, and .D) and 16 32-bit general-purpose registers. A control register
file provides the means to configure and control various processor opera ons. To understand how instruc ons are
fetched, dispatched, decoded, and executed in the data path,
Internal Memory
The C67x DSP has a 32-bit, byte-addressable address space. Internal (on-chip) memory is
organized in separate data and program spaces. When off-chip memory is used, these spaces
are unified on most devices to a single memory space via the external memory interface
(EMIF).
The C67x DSP has two 32-bit internal ports to access internal data memory. The C67x DSP
has a single internal port to access internal program memory, with an instruc on-fetch width
of 256 bits.
Memory and Peripheral Op ons
A variety of memory and peripheral op ons are available for the C6000 pla orm:
• Large on-chip RAM, up to 7M bits
• Program cache
• 2-level caches
• 32-bit external memory interface supports SDRAM, SBSRAM, SRAM, and other asynchronous memories for a broad
range of external memory requirements and maximum system performance
• DMA Controller (C6701 DSP only) transfers data between address ranges in the memory map without interven on
by the CPU. The DMA controller has four programmable channels and a fi h auxiliary channel.
• EDMA Controller performs the same func ons as the DMA controller. The EDMA has 16 programmable channels, as
well as a RAM space to hold mul ple configura ons for future transfers.
• HPI is a parallel port through which a host processor can directly access the CPU’s memory space. The host device
has ease of access because it is the master of the interface. The host and the CPU can exchange informa on via internal
or external memory. In addi on, the host has direct access to memory-mapped peripherals.
• Expansion bus is a replacement for the HPI, as well as an expansion of the EMIF. The expansion provides two dis nct
areas of func onality (host port and I/O port) which can co-exist in a system. The host port of the expansion bus can
operate in eitherasynchronous slave mode, similar to the HPI, or in synchronous master/slave mode. This allows the
device to interface to a variety of host bus protocols. Synchronous FIFOs and asynchronous peripheral I/O devices may
interface to the expansion bus.
• McBSP (mul channel buffered serial port) is based on the standard serial port interface found on the TMS320C2000
and TMS320C5000 devices. In addi on, the port can buffer serial samples in memory automa cally with the aid of the
DMA/EDNA controller. It also has mul channel capability compa ble with the T1, E1, SCSA, and MVIP networking
standards.
• Timers in the C6000 devices are two 32-bit general-purpose mers used for these
func ons:
o Time events
o Count events
o Generate pulses
o Interrupt the CPU
o Send synchroniza on events to the DMA/EDMA controller.
• Power-down logic allows reduced clocking to reduce power consump on. Most of the opera ng power of CMOS
logic dissipates during circuit switching from one logic state to another. By preven ng some or all of the chip’s logic
from switching, you can realize significant power savings without losing any data or opera onal context.

19 b)
Trunca on: In ADC (Analog-to-Digital Conversion), the con nuous amplitude of an analog signal is represented by a
finite number of bits. Trunca on in this context involves discarding the frac onal bits, leading to a loss of precision. For
example, in an 8-bit ADC, if the output is 10101011.101 (in binary), trunca on results in 10101011.000.

Rounding: Rounding in ADC involves selec ng the nearest representable digital value to the analog signal. This helps
reduce quan za on errors but introduces some level of bias. The rounding method used can affect the distribu on of
errors.
Consider a con nuous- me signal with values in the range [−1,1]. In the process of digi zing this signal with a 4-bit
ADC:

Trunca on: If the signal has an amplitude of 0.75, trunca on discards the frac onal bits, resul ng in a digital value of
0.

Rounding: Rounding the same amplitude to the nearest representable digital value would yield 1.

20 b)

 The Mul ply-Accumulate (MAC) opera on is the basis of many digital signal processing algorithms, notably
digital filtering. The term "digital filter" refers to an algorithm by which a digital signal or sequence of numbers is
transformed into another sequence of numbers termed the output digital signal.
 Digital filter involves signals in the digital domain (discrete- me signals) and are used extensively in applica ons
such as digital image processing, pa ern recogni on, and spectral analysis. In general FIR filters are preferred in
lower order solu ons, and since they do not employ feedback, they exhibit naturally bounded response. They are
simpler to implement, and require one RAM loca on and one coefficient for each order.
 For FIR filters the output of the filter is given by

where x(n) is the input to the filter, h(n) is the impulse response of the filter and y(n) is output of the filter. The
output of an FIR filter is simply a finite length weighted sum of the present and previous inputs to the filter. Hence to
perform filtering through above equa on, the minimum requirement is to quickly mul ply two values, and add the
result.

 To make it possible, a fast dedicated hardware MAC, using either fixed point or floa ng-point arithme c is
mandatory. Characteris cs of a typical fixed-point MAC include

I. 16 x 16 bit 2's complement inputs .

2. 16 x 16 bit mul plier with 32-bit product in 25 ns

3. 32140 bit accumulator

The Mul ply-Accumulate (MAC) Func on.

 The MAC speed applies both to finite impulse response (FIR) and infinite impulse response (IIR) fi1ters. The
complexity of the filter response dictates the number MAC opera ons required per sample period. A mul ply-
accumulate step performs the following:
1. Reads a 16-bit sample data (pointed to by a register)
2. Increments the sample data-pointer by 2
3. Reads a. 16-bit coefficient (pointed to by another register)
4. Increments the coefficient register pointer by 2
5. Sign Mul ply (16-bit) data and coefficient 'to yield a 32~bit resu1t
6. Adds the result to the contents of a 32-bit register pair for accumulate
12 b)