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Am29BDD160G
Data Sheet
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Publication Number 24960 Revision D Amendment +1 Issue Date October 21, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
DATASHEET
Am29BDD160G
16 Megabit (1 M x 16-bit/512 K x 32-Bit)
CMOS 2.5 Volt-only Burst Mode, Dual Boot, Simultaneous Read/
Write Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURE ADVANTAGES — Program/Erase: 50 mA max
■ Simultaneous Read/Write operations — Standby mode: CMOS: 60 µA max
— Data can be continuously read from one bank while ■ Minimum 1 million write cycles guaranteed per
executing erase/program functions in other bank sector
(–40°C to 85°C, 56 MHz and below only) ■ 20 year data retention at 125°C
— Zero latency between read and write operations ■ VersatileI/O™ control
— Two bank architecture: 75%/25% — Device generates data output voltages and tolerates
■ User-Defined x16 or x32 Data Bus data input voltages as determined by the voltage on
the VIO pin
■ Dual Boot Block
— Top and bottom boot in the same device — 1.65 V to 2.75 V compatible I/O signals
■ Flexible sector architecture SOFTWARE FEATURES

— Eight 8 Kbytes, thirty 64 Kbytes, and eight 8 Kbytes ■ Persistent Sector Protection
sectors
— A command sector protection method to lock
■ Manufactured on 0.17 µm process technology combinations of individual sectors and sector groups
■ SecSi (Secured Silicon) Sector (256 Bytes) to prevent program or erase operations within that
— Factory locked and identifiable: 16 bytes for secure, sector (requires only VCC levels)
random factory Electronic Serial Number; remainder ■ Password Sector Protection
may be customer data programmed by AMD — A sophisticated sector protection method to lock
— Customer lockable: Can be read, programmed or combinations of individual sectors and sector groups
erased just like other sectors. Once locked, data to prevent program or erase operations within that
cannot be changed sector using a user-definable 64-bit password
■ Programmable Burst interface ■ Supports Common Flash Interface (CFI)

— Interface to any high performance processor ■ Unlock Bypass Program Command
— Modes of Burst Read Operation: — Reduces overall programming time when issuing
Linear Burst: 4 double words (x32), 8 words (x16) multiple program command sequences
and double words (x32), and 32 words (x16) with ■ Data# Polling and toggle bits
wrap around — Provides a software method of detecting program or
■ Single power supply operation erase operation completion
— Optimized for 2.5 to 2.75 volt read, erase, and
HARDWARE FEATURES
program operations
■ Program Suspend/Resume & Erase
■ Compatibility with JEDEC standards (JC42.4) Suspend/Resume
— Software compatible with single-power supply Flash — Suspends program or erase operations to allow
— Backward-compatible with AMD Am29LV and Am29F reading, programming, or erasing in same bank
flash memories
■ Hardware Reset (RESET#), Ready/Busy# (RY/BY#),
PERFORMANCE CHARACTERISTICS and Write Protect (WP#) inputs
■ High performance read access ■ ACC input
— Initial/random access times as fast as 54 ns — Accelerates programming time for higher throughput
during system production
— Burst access time as fast as 9 ns for ball grid array
package ■ Package options
■ Ultra low power consumption — 80-pin PQFP
— Burst Mode Read: 90 mA @ 66 MHz max — 80-ball Fortified BGA
This document contains information on a product under development at Advanced Micro Devices. The information Publication# 24960 Rev: D Amendment/+1
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed Issue Date: October 21, 2003
product without notice.DRAFT 11/4/03
Refer to AMD’s Website (www.amd.com) for the latest information.
D A T A S H E E T
GENERAL DESCRIPTION
The Am29BDD160 is a 16 Megabit, 2.5 Volt-only sin- or sector groups are permitted; WP# Hardware Pro-
gle power supply burst mode flash memory device. tection prevents program or erase in the two outer-
The device can be configured for either 1,048,576 most 8 Kbytes sectors of the larger bank.
words in 16-bit mode or 524,288 double words in
The device defaults to the Persistent Sector Protection
32-bit mode. The device can also be programmed in
mode. The customer must then choose if the Standard
standard EPROM programmers. The device offers a
or Password Protection method is most desirable. The
configurable burst interface to 16/32-bit microproces-
WP# Hardware Protection feature is always available,
sors and microcontrollers.
independent of the other protection method chosen.
To eliminate bus contention, each device has separate
The VersatileI/O™ (VCCQ ) feature allows the output
chip enable (CE#), write enable (WE#) and output en-
voltage generated on the device to be determined
able (OE#) controls. Additional control inputs are re-
based on the VIO level. This feature allows this device
quired for synchronous burst operations: Load Burst
to operate in the 1.8 V I/O environment, driving and re-
Address Valid (ADV#), and Clock (CLK).
ceiving signals to and from other 1.8 V devices on the
Each device requires only a single 2.5 or 2.6 Volt same bus. In addition, inputs and I/Os that are driven
power supply (2.5 V to 2.75 V) for both read and write externally are capable of handling 3.6 V.
functions. A 12.0-volt VPP is not required for program
or erase operations, although an acceleration pin is The host system can detect whether a program or
available if faster programming performance is re- erase operation is complete by observing the RY/BY#
quired. pin, by reading the DQ7 (Data# Polling), or DQ6 (tog-
gle) status bits. After a program or erase cycle has
The device is entirely command set compatible with been completed, the device is ready to read array data
the JEDEC single-power-supply Flash standard. or accept another command.
The software command set is compatible with the
command sets of the 5 V Am29F and 3 V Am29LV The sector erase architecture allows memory sec-
Flash families. Commands are written to the command tors to be erased and reprogrammed without affecting
register using standard microprocessor write timing. the data contents of other sectors. The device is fully
Register contents serve as inputs to an internal erased when shipped from the factory.
state-machine that controls the erase and program- Hardware data protection measures include a low
ming circuitry. Write cycles also internally latch ad-
V CC detector that automatically inhibits write opera-
dresses and data needed for the programming and
tions during power transitions. The password and
erase operations. Reading data out of the device is
software sector protection feature disables both
similar to reading from other Flash or EPROM de-
program and erase operations in any combination of
vices.
sectors of memory. This can be achieved in-system at
The Unlock Bypass mode facilitates faster program- VCC level.
ming times by requiring only two write cycles to pro-
gram data instead of four. The Program/Erase Suspend/Erase Resume fea-
ture enables the user to put erase on hold for any pe-
The Simultaneous Read/Write architecture provides riod of time to read data from, or program data to, any
simultaneous operation by dividing the memory space sector that is not selected for erasure. True back-
into two banks. The device can begin programming or ground erase can thus be achieved.
erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases The hardware RESET# pin terminates any operation
the system from waiting for the completion of program in progress and resets the internal state machine to
or erase operations. See Simultaneous Read/Write reading array data.
Operations Overview and Restrictions on page 13. The device offers two power-saving features. When
The device provides a 256-byte SecSi™ (Secured addresses have been stable for a specified amount of
Silicon) Sector with an one-time-programmable time, the device enters the automatic sleep mode.
(OTP) mechanism. The system can also place the device into the
standby mode. Power consumption is greatly re-
In addition, the device features several levels of sector duced in both these modes.
protection, which can disable both the program and
erase operations in certain sectors or sector groups: AMD’s Flash technology combines years of Flash
Persistent Sector Protection is a command sector memory manufacturing experience to produce the
protection method that replaces the old 12 V con- highest levels of quality, reliability and cost effective-
trolled protection method; Password Sector Protec- ness. The device electrically erases all bits within a
tion is a highly sophisticated protection method that sector simultaneously via Fowler-Nordheim tunnelling.
requires a password before changes to certain sectors The data is programmed using hot electron injection.
2 Am29BDD160G October 21, 2003

D A T A S H E E T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Dynamic Protection Bit (DYB) ............................................. 25
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table 11. Sector Protection Schemes ............................................ 26
Block Diagram of Persistent Sector Protection Mode Locking Bit ....................... 26
Simultaneous Operation Circuit . . . . . . . . . . . . . 6 Password Protection Mode ..................................................... 26
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Password and Password Mode Locking Bit ............................ 26
Special Package Handling Instructions .................................... 8 64-bit Password ................................................................... 27
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Write Protect (WP#) ................................................................ 27
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SecSi™ (Secured Silicon) Sector Protection .......................... 27
x16 Mode .................................................................................. 9 SecSi Sector Protection Bit ..................................................... 28
x32 Mode .................................................................................. 9 Persistent Protection Bit Lock ................................................. 28
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 10 Hardware Data Protection ...................................................... 28
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 11 Low VCC Write Inhibit ........................................................... 28
Table 1. Device Bus Operation .......................................................12 Write Pulse “Glitch” Protection ............................................ 28
VersatileI/O™ (VIO) Control .................................................... 13 Logical Inhibit ....................................................................... 28
Requirements for Reading Array Data ................................... 13 Power-Up Write Inhibit ......................................................... 28
Simultaneous Read/Write VCC and VIO Power-up And Power-down Sequencing ......... 28
Operations Overview and Restrictions ................................... 13 Table 12. Sector Addresses for Top Boot Sector Devices ............. 29
Overview ............................................................................. 13 Table 13. Sector Addresses for Bottom Boot Sector Devices ........ 30
Restrictions .......................................................................... 13 Table 14. CFI Query Identification String ....................................... 31
Table 2. Bank Assignment for Boot Bank Table 15. CFI System Interface String ........................................... 31
Sector Devices ................................................................................13 Table 16. CFI Device Geometry Definition ..................................... 32
Simultaneous Read/Write Operations With Zero Latency ...... 13 Table 17. CFI Primary Vendor-Specific Extended Query ............... 32
Table 3. Top Boot Bank Select .......................................................14 Command Definitions . . . . . . . . . . . . . . . . . . . . . 34
Table 4. Bottom Boot Bank Select ..................................................14 Reading Array Data in Non-burst Mode .................................. 34
Writing Commands/Command Sequences ............................ 14 Reading Array Data in Burst Mode ......................................... 34
Accelerated Program and Erase Operations ....................... 14 Read/Reset Command ........................................................... 34
Autoselect Functions ........................................................... 14 Autoselect Command ............................................................. 35
Automatic Sleep Mode (ASM) ................................................ 14 Program Command Sequence ............................................... 35
RESET#: Hardware Reset Pin ............................................... 15 Accelerated Program Command ............................................ 35
Output Disable Mode .............................................................. 15 Unlock Bypass Command Sequence ..................................... 35
Autoselect Mode ..................................................................... 15 Figure 4. Program Operation ......................................................... 36
Table 5. Am29BDD160 Autoselect Codes (High Voltage Method) .16 Unlock Bypass Entry Command .......................................... 36
Asynchronous Read Operation (Non-Burst) ........................... 16 Unlock Bypass Program Command .................................... 36
Figure 1. Asynchronous Read Operation........................................ 16 Unlock Bypass Chip Erase Command ................................ 36
Synchronous (Burst) Read Operation .................................... 17 Unlock Bypass CFI Command ............................................ 36
Linear Burst Read Operations ................................................ 17 Unlock Bypass Reset Command ......................................... 37
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order .................17 Chip Erase Command ............................................................ 37
CE# Control in Linear Mode ................................................ 18 Sector Erase Command ......................................................... 37
ADV# Control In Linear Mode .............................................. 18 Figure 5. Erase Operation.............................................................. 38
RESET# Control in Linear Mode ......................................... 18 Sector Erase and Program Suspend Command .................... 38
OE# Control in Linear Mode ................................................ 18 Sector Erase and Program Suspend Operation Mechanics ... 38
IND/WAIT# Operation in Linear Mode ................................. 18 Table 18. Allowed Operations During Erase/Program Suspend ... 38
Table 7. Valid Configuration Register Bit Definition for IND/WAIT# 20 Sector Erase and Program Resume Command ..................... 39
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Configuration Register Read Command ................................. 39
Burst Operation............................................................................... 20 Configuration Register Write Command ................................. 39
Burst Access Timing Control ............................................... 21 Common Flash Interface (CFI) Command .............................. 39
Initial Burst Access Delay Control ....................................... 21 SecSi Sector Entry Command ................................................ 41
Table 8. Burst Initial Access Delay ..................................................21 Password Program Command ................................................ 41
Figure 3. Initial Burst Delay Control ................................................ 21 Password Verify Command .................................................... 41
Configuration Register ............................................................ 22 Password Protection Mode Locking Bit Program Command .. 42
Table 9. Configuration Register Definitions .....................................22 Persistent Sector Protection Mode Locking Bit Program Com-
Table 10. Configuration Register After Device Reset .....................24
mand ....................................................................................... 42
Initial Access Delay Configuration .......................................... 24
SecSi Sector Protection Bit Program Command .................... 42
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . 24
PPB Lock Bit Set Command ................................................... 42
Persistent Sector Protection ................................................... 24
DYB Write Command ............................................................. 42
Persistent Protection Bit (PPB) ............................................ 25
Password Unlock Command .................................................. 42
Persistent Protection Bit Lock (PPB Lock) .......................... 25
PPB Program Command ........................................................ 43
October 21, 2003 Am29BDD160G 3

D A T A S H E E T
All PPB Erase Command ....................................................... 43 Key to Switching Waveforms . . . . . . . . . . . . . . . 56

DYB Write ............................................................................... 43 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . 56
PPB Lock Bit Set .................................................................... 43 Figure 13. Input Waveforms and Measurement Levels ................. 56
DYB Status ............................................................................. 43 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 57
PPB Status ............................................................................. 44 Figure 14. VCC and VIO Power-up Diagram ................................. 57
PPB Lock Bit Status ............................................................... 44 Figure 15. Conventional Read Operations Timings ....................... 60
Non-volatile Protection Bit Program And Erase Flow ............. 44 Figure 16. Burst Mode Read (x32 Mode)....................................... 60
Table 19. Memory Array Command Definitions (x32 Mode) ...........45 Figure 17. Asynchronous Command Write Timing ........................ 61
Table 20. Sector Protection Command Definitions (x32 Mode) ......46 Figure 18. Synchronous Command Write/Read Timing................. 61
Table 21. Memory Array Command Definitions (x16 Mode) ...........47 Figure 19. RESET# Timings .......................................................... 63
Table 22. Sector Protection Command Definitions (x16 Mode) ......48 Figure 20. WP# Timing .................................................................. 63
Figure 21. Program Operation Timings.......................................... 65
DQ7: Data# Polling ................................................................. 49
Figure 22. Chip/Sector Erase Operation Timings .......................... 66
RY/BY#: Ready/Busy# ........................................................... 49
Figure 23. Back-to-back Cycle Timings ......................................... 66
Figure 6. Data# Polling Algorithm ................................................... 50
Figure 24. Data# Polling Timings (During Embedded Algorithms). 67
DQ6: Toggle Bit I .................................................................... 50 Figure 25. Toggle Bit Timings (During Embedded Algorithms)...... 67
DQ2: Toggle Bit II ................................................................... 50 Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations...
Reading Toggle Bits DQ6/DQ2 .............................................. 51 68
DQ5: Exceeded Timing Limits ................................................ 51 Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings .. 68
Figure 7. Toggle Bit Algorithm......................................................... 51 Figure 28. Sector Protect/Unprotect Timing Diagram .................... 69
DQ3: Sector Erase Timer ....................................................... 52 Figure 29. Alternate CE# Controlled Write Operation Timings ...... 71
Table 23. Write Operation Status ....................................................52 Erase and Programming Performance . . . . . . . 72
Figure 8. Maximum Negative Overshoot Waveform ....................... 53 Latchup Characteristics . . . . . . . . . . . . . . . . . . . 72
Figure 9. Maximum Positive Overshoot Waveform......................... 53 PQFP and Fortified BGA Pin Capacitance . . . . . 72
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 54 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 73
Currents) ......................................................................................... 55 PQR080–80-Lead Plastic Quad Flat Package ....................... 73
Figure 11. Typical ICC1 vs. Frequency............................................. 55
LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm) ......... 74
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 12. Test Setup...................................................................... 56
Table 24. Test Specifications ..........................................................56

D A T A S H E E T
PRODUCT SELECTOR GUIDE

Part Number Am29BDD160G
Standard Voltage Range: VCC = 2.5 – 2.75 V Synchronous/Burst or Asynchronous
54D 64C 65A
Speed Option (Clock Rate)
(66 MHz) (56 MHz) (40 MHz)
Max Initial/Asynchronous Access Time, ns (tACC) 54 64 67

Max Burst Access Delay (ns) 9 FBGA/9.5 PQFP 10 FBGA/10 PQFP 17
Max Clock Rate (MHz) 66 56 40

Min Initial Clock Delay (clock cycles) 3 3 2
Max CE# Access, ns (tCE) 58 69 71
Max OE# Access, ns (tOE) 20 28
Note: The 54D, 64C, and 65A speed options are tested and guaranteed to operate only at the 66 MHz, 56MHz, and 40MHz
frequencies respectively. Operation and other frequencies is not warranted.
BLOCK DIAGRAM
VCC
VSS DQ0–DQ15
A0–A18
RDY
Buffer RDY
Erase Voltage VIO Input/Output

Generator Buffers
WE#
RESET# State
Control
ACC
WP# Command
Register
WORD# PGM Voltage
Generator
Chip Enable Data
CE# Output Enable Latch
Logic
OE#
Y-Decoder Y-Gating
VCC
Address Latch
Timer
Detector
X-Decoder Cell Matrix

ADV# Burst Burst
State Address
CLK Control IND/ Counter
WAIT#
A0–A20
DQ0–DQ15
A0–A18

D A T A S H E E T
BLOCK DIAGRAM OF
SIMULTANEOUS OPERATION CIRCUIT
VCC OE#
VSS
Latches and Control Logic

A0–A18 Upper Bank Address
Y-Decoder
Upper Bank
DQ0–DQ31
A0–A18
16/32#
X-Decoder
A0–A18
STATE
RESET# CONTROL
Status
WE# & DQ0–DQ31
CE# COMMAND
REGISTER
ADV# Control
DQ0–DQ31
DQ0–DQ31
X-Decoder
A0–A18
Control Logic
Latches and
Y-Decoder
Lower Bank
A0–A18 Lower Bank Address

D A T A S H E E T
CONNECTION DIAGRAM
IND/WAIT#
RESET#
WORD#
RY/BY#
ADV#
VCCQ
WP#
WE#
OE#
CE#
CLK
VCC
VSS
NC
NC
NC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DQ16 1 64 DQ15
DQ17 2 63 DQ14
DQ18 3 62 DQ13
DQ19 4 61 DQ12
VCCQ 5 60 VSS
VSS 6 59 VCCQ
DQ20 7 58 DQ11
DQ21 8 57 DQ10
DQ22 9 56 DQ9
DQ23 10 55 DQ8
DQ24 11 54 DQ7
DQ25 12 80-pin PQFP 53 DQ6
DQ26 13 52 DQ5
DQ27 14 51 DQ4
VCCQ 15 50 VSS
VSS 16 49 VCCQ
DQ28 17 48 DQ3
DQ29 18 47 DQ2
DQ30 19 46 DQ1
DQ31 20 45 DQ0
A-1 21 44 NC
A0 22 43 A18
A1 23 42 A17
A2 24 41 A16
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A15
A3
A4
A5
A6
A7
A8
VSS
ACC
VCC
A9
A10
A11
A12
A13
A14

D A T A S H E E T
CONNECTION DIAGRAMS
80-Ball Fortified BGA
A8 B8 C8 D8 E8 F8 G8 H8 J8 K8
A2 A1 A0 DQ29 VCCQ VSS VCCQ DQ20 DQ16 WORD#
A7 B7 C7 D7 E7 F7 G7 H7 J7 K7
A3 A4 A-1 DQ30 DQ26 DQ24 DQ23 DQ18 IND/WAIT# NC
A6 B6 C6 D6 E6 F6 G6 H6 J6 K6
A6 A5 A7 DQ31 DQ28 DQ25 DQ21 DQ19 OE# WE#
A5 B5 C5 D5 E5 F5 G5 H5 J5 K5
VSS A8 NC NC DQ27 RY/BY# DQ22 DQ17 CE# VCC
A4 B4 C4 D4 E4 F4 G4 H4 J4 K4
ACC A9 A10 NC DQ1 DQ5 DQ9 WP# NC VSS
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3
VCC A12 A11 NC DQ2 DQ6 DQ10 DQ11 ADV# CLK
A2 B2 C2 D2 E2 F2 G2 H2 J2 K2
A14 A13 A18 DQ0 DQ4 DQ7 DQ8 DQ12 DQ14 RESET#
A1 B1 C1 D1 E1 F1 G1 H1 J1 K1
A15 A16 A17 DQ3 VCCQ VSS VCCQ DQ13 DQ15 VCCQ
Special Package Handling Instructions

Special handling is required for Flash Memory prod- body is exposed to temperatures above 150°C for pro-
ucts in molded packages (BGA). The package and/or longed periods of time.
data integrity may be compromised if the package

D A T A S H E E T
PIN CONFIGURATION
A–1 = Least significant address bit for the 16-bit CLK = Clock Input that can be tied to the system
data bus, and selects between the high or microprocessor clock and provides the
and low word. A –1 is not used for the fundamental timing and internal operating
32-bit mode (WORD# = VIH). frequency.
ADV# = Load Burst Address input. Indicates that
A0–A18 = 19-bit address bus for 16 Mb device. A9
the valid address is present on the address
supports 12 V autoselect inputs.
inputs.
DQ0–DQ31 = 32-bit data inputs/outputs/float
IND# = End of burst indicator for finite bursts only.
WORD# = Selects 16-bit or 32-bit mode. When IND is low when the last word in the burst
WORD# = VIH, data is output on sequence is at the data outputs.
DQ31–DQ0. When WORD# = VIL, data is
WAIT# = Provides data valid feedback only when
output on DQ15–DQ0.
the burst length is set to continuous.
CE# = Chip Enable Input. This signal is asynchro-
WP# = Write Protect input. When WP# = VOL, the
nous relative to CLK for the burst mode.
two outermost bootblock sector in the 75%
OE# = Output Enable Input. This signal is asyn- bank are write protected regardless of
chronous relative to CLK for the burst other sector protection configurations.
mode.
ACC = Acceleration input. When taken to 12 V,
WE# = Write enable. This signal is asynchronous program and erase operations are acceler-
relative to CLK for the burst mode. ated. When not used for acceleration, ACC
VSS = Device ground = VSS to VCC.
NC = Pin not connected internally VIO (VCCQ) = Output Buffer Power Supply (1.65 V to
2.75 V)
RY/BY# = Ready/Busy output and open drain. When
RY/BY# = VIH, the device is ready to ac- VCC = Chip Power Supply (2.5 V to 2.75 V)
cept read operations and commands. RESET# = Hardware reset input
When RY/BY# = VOL, the device is either
executing an embedded algorithm or the
device is executing a hardware reset oper-
ation.
LOGIC SYMBOLS
x16 Mode x32 Mode
20 19
A-1 to A18 16 A0–A18 32
DQ0–DQ15 DQ0–DQ31
CLK CLK
CE# CE#
OE# OE#
WE# WE#
RESET# IND/WAIT# RESET# IND/WAIT#
ADV# ADV#
ACC RY/BY# ACC RY/BY#
WP# WP#
VIO (VCCQ) VIO (VCCQ)
WORD# WORD#

D A T A S H E E T
ORDERING INFORMATION
The order number (Valid Combination) is formed by the following:
Am29BDD160 G T 54 D PB E
TEMPERATURE RANGE
I = Industrial (–40°C to +85°C)
E = Extended (–40°C to +125°C)
PACKAGE TYPE
K = 80-Pin Plastic Quad Flat Package (PQFP) PQR080
PB = 80-Ball Fortified Ball Grid Array (Fortified BGA)
1.0 mm pitch, 13 x 11 mm package (LAA080)
CLOCK RATE
A = 40 MHz
C = 56 MHz
D = 66 MHz
SPEED
(See Product Selector Guide and Valid Combinations)
BOOT CODE SECTOR ARCHITECTURE

T = Top Sector
B = Bottom Sector
PROCESS TECHNOLOGY
G = 0.17 µm
DEVICE NUMBER/DESCRIPTION
Am29BDD160
16 Megabit (2 M x 16-Bit/512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode,
Dual Boot, Simultaneous Operation Flash Memory
Valid Combinations for Fortified BGA Packages

Valid Combinations for PQFP Packages
Order Number Package Marking
Am29BDD160GT54D
Am29BDD160GB54D Am29BDD160GT54D BD160GT54D
Am29BDD160GB54D BD160GB54D
Am29BDD160GT64C
KI, KE
Am29BDD160GB64C Am29BDD160GT64C PBI, BD160GT64C
I, E
Am29BDD160GB64C PBE BD160GB64C
Am29BDD160GT65A
Am29BDD160GB65A Am29BDD160GT65A BD160GT65A
Am29BDD160GB65A BD160GB65A
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult the local AMD sales office to confirm
availability of specific valid combinations and to check on newly re-
leased combinations.

D A T A S H E E T
DEVICE BUS OPERATIONS

This section describes the requirements and use of the register serve as inputs to the internal state machine.
device bus operations, which are initiated through the The state machine outputs dictate the function of the
internal command register. The command register itself device. Table 1 lists the device bus operations, the in-
does not occupy any addressable memory location. puts and control levels they require, and the resulting
The register is composed of latches that store the com- output. The following subsections describe each of
mands, along with the address and data information these operations in further detail.
needed to execute the command. The contents of the

D A T A S H E E T
Table 1. Device Bus Operation

Addresses Data
Operation CE# OE# WE# RESET# CLK ADV# (Note 1) (DQ0–DQ31)
A9 = VID, A6 = L, 0000001h
Autoselect Manufacturer Code L L H H X X
A1 = L, A0 = L (Note 2)
A9 = VID, A6 = L, 000007Eh
Read Cycle 1 L L H H X X
Autoselect Device Code
A1 = L, A0 = H (Note 2)
A9 = VID,
Read Cycle 2 L L H H X X 0000008h
A7–A0 = 0Eh
Top Boot Block

0000000h
A9 = VID,
Read Cycle 3 L L H H X X Bottom Boot
A7–A0 = 0Fh
Block
0000001h
Read L L H H X X AIN DOUT
Write L H L H X X AIN DIN

Standby (CE#) H X X H X X X HIGH Z
Output Disable L H H H X X HIGH Z HIGH Z
Reset X X X L X X X HIGH Z
00000001h,
(protected)
Sector Address, A6 = H
PPB Protection Status (Note 4) L L H H X X A9 = VID,
A7 – A0 = 02h 00000000h
(unprotect)
A6 = L
Burst Read Operations

Load Starting Burst Address L X H H AIN X
Advance Burst to next address
with appropriate Data presented L L H H H X Burst Data Out
on the Data bus
Terminate Current Burst Read

H X H H X X HIGH Z
Cycle

X X H L X X X HIGH Z
Cycle with RESET#
Cycle; Start New Burst Read L H H H AIN X
Cycle
Legend:
L = Logic Low = VIL, H = Logic High = VIH, X = Don’t care.
Notes:
1. DQ31–DQ16 are HIGH Z when WORD# = VIL
2. When WORD# = VIL, DQ31-DQ16 are floating
3. WP# controls the two outermost sectors of the top boot block or the two outermost sectors of the bottom boot block.
4. DQ0 reflects the sector PPB (or sector group PPB) and DQ1 reflects the DYB
5. Addresses are A0:A18 for the x32 mode and A–1:A18 for x16 mode.

D A T A S H E E T
VersatileI/O™ (VIO) Control tions and to Figure 15 for the timing diagram. ICC1 in
the DC Characteristics table represents the active cur-
The VersatileI/O (VIO) control allows the host system
rent specification for reading array data.
to set the voltage levels that the device generates at
its data outputs and the voltages tolerated at its data
Simultaneous Read/Write
inputs to the same voltage level that is asserted on the
VIO pin. Operations Overview and Restrictions
The output voltage generated on the device is deter- Overview
mined based on the VIO (VCCQ) level. Simultaneous Operation is an advances functionality
A VIO of 1.65–1.95 volts is targeted to provide for I/O providing enhanced speed and flexibility with minimum
tolerance at the 1.8 volt level. overhead. Simultaneous Operation does this by allow-
ing an operation to be executed (embedded operation)
A VCC and VIO of 2.5–2.75 volts makes the device ap- in a bank (busy bank), then going to the other bank
pear as 2.5 volt-only. (non-busy bank) and performing desired operations.
Address/Control signals are 3.6 V tolerant with the ex- The BDD160’s Simultaneous Operation has been opti-
ception of CLK. mized for applications that could most benefit from this
capability. These applications store code in the big
Word/Double Word Configuration bank, while storing data in the small bank. The best
The WORD# pin controls whether the device data I/O example of this is when a Sector Erase Operation (as
pins operate in the word or double word configuration. an embedded operation) in the small (busy) bank,
If the WORD# pin is set at VIH, the device is in double while performing a Burst/synchronous Read Operation
word configuration, DQ31–DQ0 are active and con- in the big (non-busy) bank.
trolled by CE# and OE#.
Restrictions
If the WORD# pin is set at VIL, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are The BDD160’s Simultaneous Operation is tested by
active and controlled by CE# and OE#. The data I/O executing an embedded operation in the small (busy)
pins DQ31–DQ16 are tri-stated. bank while performing other operations in the big
(non-busy) bank. However, the opposite case is nei-
Requirements for Reading Array Data ther tested nor valid. That is, it is not tested by execut-
ing an embedded operation in the big (busy) bank
To read array data from the outputs, the system must while performing other operations in the small
drive the CE# and OE# pins to VIL. CE# is the power (non-busy) bank. See Table 2 Bank assignment for
control and selects the device. OE# is the output con- Boot Bank Sector Devices.
trol and gates array data to the output pins. WE#
should remain at VIH. Table 2. Bank Assignment for Boot Bank
Sector Devices
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This Bottom Boot Sector
Top Boot Sector Devices Devices
ensures that no spurious alteration of the memory
content occurs during the power transition. No com- Bank
Small Bank Big Bank
1
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid Bank
Big Bank Small Bank
2
addresses on the device address inputs produce valid
data on the device data outputs. The device remains Also see Table 18, “Allowed Operations During
enabled for read access until the command register Erase/Program Suspend,” on page 38. Also see
contents are altered. Table 12, “Sector Addresses for Top Boot Sector De-
vices,” on page 29 and see Table 13, “Sector Ad-
Address access time (tACC) is the delay from stable ad-
dresses for Bottom Boot Sector Devices,” on page 30.
dresses to valid output data. The chip enable access
time (tCE) is the delay from stable addresses and sta-
Simultaneous Read/Write Operations With
ble CE# to valid data at the output pins. The output en-
able access time (t OE ) is the delay from the falling Zero Latency
edge of OE# to valid data at the output pins (assuming The device is capable of reading data from one bank
the addresses have been stable for at least tACC–tOE of memory while programming or erasing in the other
time and CE# has been asserted for at least tCE–tOE bank of memory. An erase operation may also be sus-
time). pended to read from or program to another location
within the same bank (except the sector being
See “Reading Array Data” for more information. Refer
erased). Refer to the DC Characteristics table for
to the AC Read Operations table for timing specifica-

D A T A S H E E T
read-while-program and read-while-erase current The AC Characteristics section contains timing specifi-
specifications. cation tables and timing diagrams for erase or pro-
gram operations.
Simultaneous read/write operations are valid for both
the main Flash memory array and the SecSi OTP sec- Accelerated Program and Erase Operations
tor. Simultaneous operation is disabled during the CFI
and Password Program/Verify operations. PPB Pro- The device offers accelerated program/erase opera-
gram/Erase operations and the Password Unlock options through the ACC pin. When the system asserts
eration permit reading data from the large (75%) bank VHH (12V) on the ACC pin, the device automatically
while reading the operation status of these commands enters the Unlock Bypass mode. The system may
from the small (25%) bank. then write the two-cycle Unlock Bypass program com-
mand sequence to do accelerated programming. The
Table 3. Top Boot Bank Select device uses the higher voltage on the ACC pin to ac-
Bank A18:A17 celerate the operation. A sector that is being protected
Bank 1 00 with the WP# pin will still be protect during accelerated
Bank 2 01, 1X program or Erase. Note that the ACC pin must not be
at V HH during any operation other than accelerated
Table 4. Bottom Boot Bank Select programming, or device damage may result.
Bank A18
Bank 1 0X, 10 Autoselect Functions
Bank 2 11 If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
Writing Commands/Command Sequences system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
To write a command or command sequence (which in-
on DQ7–DQ0. Standard read cycle timings apply in
cludes programming data to the device and erasing
this mode. Refer to the Autoselect Mode and Autose-
sectors of memory), the system must drive WE# and
lect Command Sequence sections for more informa-
CE# to VIL, and OE# to VIH.
tion.
For program operations, in the x32-mode the device
accepts program data in 32-bit words and in the x16 Automatic Sleep Mode (ASM)
mode the device accepts program data in 16-bit The automatic sleep mode minimizes Flash device en-
words. ergy consumption. While in asynchronous mode, the
The device features an Unlock Bypass mode to facili- device automatically enables this mode when ad-
tate faster programming. Once the device enters the dresses remain stable for tACC + 60 ns. The automatic
Unlock Bypass mode, only two write cycles are re- sleep mode is independent of the CE#, WE# and OE#
quired to program a word or byte, instead of four. The control signals. Standard address access timings pro-
Sector Erase and Program Suspend Command sec- vide new data when addresses are changed. While in
tion has details on programming data to the device sleep mode, output data is latched and always avail-
using both standard and Unlock Bypass command se- able to the system. While in synchronous mode, the
quences. device automatically enables this mode when either
the first active CLK level is greater than t ACC or the
An erase operation can erase one sector, multiple sec- CLK runs slower than 5 MHz. Note that a new burst
tors, or the entire device. Tables 12 and 13 indicate operation is required to provide new data.
the address space that each sector occupies. A “sec-
tor address” consists of the address bits required to ICC8 in the “DC Characteristics” section of page 53 rep-
uniquely select a sector. The “Command Definitions” resents the automatic sleep mode current specifica-
section has details on erasing a sector or the entire tion.
chip, or suspending/resuming the erase operation.
Standby Mode
After the system writes the autoselect command se-
When the system is not responding or writing to the
quence, the device enters the autoselect mode. The
device, it can place the device in the standby mode. In
system can then read autoselect codes from the inter-
this mode, current consumption is greatly reduced,
nal register (which is separate from the memory array)
and the outputs are placed in the high impedance
on DQ7–DQ0. Standard read cycle timing applies in
state, independent of the OE# input.
this mode. Refer to the “Autoselect Mode” section for
more information. The device enters the CMOS standby mode when the
CE# and RESET# inputs are both held at Vcc ± 0.2 V.
ICC2 in the DC Characteristics table represents the ac-
The device requires standard access time (t CE) for
tive current specification for erase or program modes.
read access, before it is ready to read data.

D A T A S H E E T
If the device is deselected during erasure or program- operation when RESET# was asserted, the user must
ming, the device draws active current until the opera- wait 11 µs before accessing that bank.
tion is completed.
Asserting RESET# during a program or erase opera-
ICC5 in the “DC Characteristics” section on page 53 tion leaves erroneous data stored in the address loca-
represents the standby current specification. tions being operated on at the time of device reset.
These locations need updating after the reset opera-
Caution: entering the standby mode via the RESET#
tion is complete. See Figure 19 for timing specifica-
pin also resets the device to the read mode and floats
tions.
the data I/O pins. Furthermore, entering ICC7 during a
program or erase operation will leave erroneous data As s er ti ng RE SE T# ac tiv e du ri ng V C C a nd V I O
in the address locations being operated on at the time power-up is required to guarantee proper device ini-
of the RESET# pulse. These locations require updat- tialization until VCC and VIO have reached their steady
ing after the device resumes standard operations. state voltages.
Refer to the “RESET#: Hardware Reset Pin” section
for further discussion of the RESET# pin and its func- Output Disable Mode
tions. See Table 1 Device Bus Operation for OE# Operation
in Output Disable Mode.
RESET#: Hardware Reset Pin
The RESET# pin is an active low signal that is used to Autoselect Mode
reset the device under any circumstances. A logic “0” The autoselect mode provides manufacturer and de-
on this pin forces the device out of any mode that is vice identification, and sector protection verification,
currently executing back to the reset state. The RE- through identifier codes output on DQ7–DQ0. This
SET# pin may be tied to the system reset circuitry. A mode is primarily intended for programming equip-
system reset would thus also reset the device. To ment to automatically match a device to be pro-
avoid a potential bus contention during a system reset, grammed with its corresponding programming
the device is isolated from the DQ data bus by tristat- algorithm. However, the autoselect codes can also be
ing the data output pins for the duration of the RESET accessed in-system through the command register.
pulse. All pins are “don’t care” during the reset opera-
tion. When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
If RESET# is asserted during a program or erase op- A6, A1, and A0 must be as shown in Table 12 (top
eration, the RY/BY# pin remains low until the reset op- boot devices) or Table 13 (bottom boot devices). In ad-
eration is internally complete. This action requires dition, when verifying sector protection, the sector ad-
between 1 µs and 7µs for either Chip Erase or Sector dress must appear on the appropriate highest order
Erase. The RY/BY# pin can be used to determine address bits (see Tables 11 and 12). See Table 5
when the reset operation is complete. Otherwise, shows the remaining address bits that are don’t care.
allow for the maximum reset time of 11 µs. If RESET# When all necessary bits have been set as required,
is asserted when a program or erase operation is not the programming equipment may then read the corre-
executing (RY/BY# = “1”), the reset operation will com- sponding identifier code on DQ7–DQ0.
plete within 500 ns. Since the Am29BDD160 is a Si-
multaneous Operation device the user may read a To access the autoselect codes in-system, the host
bank after 500 ns if the bank was in the read/reset system can issue the autoselect command via the
mode at the time RESET# was asserted. If one of the command. This method does not require V ID . See
banks was in the middle of either a program or erase “Command Definitions” for details on using the autose-
lect mode.

D A T A S H E E T
Table 5. Am29BDD160 Autoselect Codes (High Voltage Method)

A18 A5 DQ7
to to to
Description CE# OE# WE# A11 A10 A9 A8 A7 A6 A4 A3 A2 A1 A0 DQ0
Manufacturer ID:
L L H X X VID X X L X X X L L 0001h
AMD
Autoselect Device Code
Read Cycle 1 L L H X X VID X L L X L L L H 007Eh

Read Cycle 2 L L H X X VID X L L L H H H L 0008h
0000h (top boot
block)
Read Cycle 3 L L H X X VID X L L L H H H H
0001h (bottom boot
block)
PPB Protection 0000h (unprotected)

L L H SA X VID X L L L L L H L
Status 0001h (protected)
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note: The autoselect codes may also be accessed in-system via command sequences. See Tables 18 and 20.
Asynchronous Read Operation and should be used for device selection. OE# is the
(Non-Burst) output control and should be used to gate data to the
output pins if the device is selected.
The device has two control functions which must be
satisfied in order to obtain data at the outputs. CE# is Address access time (tACC) is equal to the delay from
the power control and should be used for device selec- stable addresses to valid output data. The chip enable
tion. OE# is the output control and should be used to access time (t CE ) is the delay from the stable ad-
gate data to the output pins if the device is selected. dresses and stable CE# to valid data at the output
The device is power-up in an asynchronous read pins. The output enable access time is the delay from
mode. In the asynchronous mode the device has two the falling edge of OE# to valid data at the output pins
control functions which must be satisfied in order to (assuming the addresses have been stable for at least
obtain data at the outputs. CE# is the power control tACC–tOE time).
CE#
CLK
ADV#
A0-A18 Address 0 Address 1 Address 2 Address 3
DQ0-DQ31 D0 D1 D2 D3 D3
OE#
WE#
VIH
Float Float
IND/WAIT# VOH
Note: Operation is shown for the 32-bit data bus. For the 16-bit data bus, A-1 is required.
Figure 1. Asynchronous Read Operation

D A T A S H E E T
Synchronous (Burst) Read Operation these locations results in the data remaining valid
while OE# is at VIL, regardless of the number of CLK
The Am29BDD160 is capable of performing burst read
cycles applied to the device.
operations to improve total system data throughput.
The device is available in three burst modes of opera-
Linear Burst Read Operations
tion: linear and burst mode. 2, 4 and 8 double word
(x32) and 4 and 8 word (x16) accesses are config- Linear burst read mode reads either 4, 8, 16, or 32
urable as either sequential burst accesses. 16 and 32 words (1 word = 16 bits), depending upon the Configu-
word (x16) accesses are only configurable as linear ration Register option. If the device is configured with
burst accesses. Additional options for all burst modes a 32 bit interface (WORD# = VIH), the burst access is
include initial access delay configurations (2–16 comprised of 4 clocked reads for 8 words and 16
CLKs) Device configuration for burst mode operation clocked reads for 32 words (See Table 6 for all valid
is accomplished by writing the Configuration Register burst output sequences). The number of clocked
with the desired burst configuration information. Once reads is doubled when the device is configured in the
the Configuration Register is written to enable burst 16-bit data bus mode (WORD# = VIL). The IND/WAIT#
mode operation, all subsequent reads from the array pin transitions active (VIL ) during the last transfer of
are returned using the burst mode protocols. Like the data during a linear burst read before a wrap around,
main memory access, the SecSi Sector memory is ac- indicating that the system should initiate another
cessed with the same burst or asynchronous timing as ADV# to start the next burst access. If the system con-
defined in the Configuration Register. However, the tinues to clock the device, the next access wraps
user must recognize that continuous burst operations around to the starting address of the previous burst
past the 256 byte SecSi boundary returns invalid data. access. The IND/WAIT# signal remains inactive (float-
ing) when not active. See Table 6 for a complete 32
Burst read operations occur only to the main flash and 16 bit data bus interface order. 16 and 32 word
memory arrays. The Configuration Register and pro- options are restricted to sequential burst accesses,
tection bits are treated as single cycle reads, even only.
when burst mode is enabled. Read operations to
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order
Data Transfer Sequence
(Independent of the WORD# Output Data Sequence (Initial Access Address)
pin) (x16)
Two Linear Data Transfers, 0-1 (A0 = 0)

(x32 only) 1-0 (A0 = 1)
0-1-2-3 (A0:A-1/A1-A0 = 00)

1-2-3-0 (A0:A-1/A1-A0 = 01)
Four Linear Data Transfers
2-3-0-1 (A:A-1/A1-A0 = 10)
3-0-1-2 (A0:A-1/A1-A0 = 11)
0-1-2-3-4-5-6-7 (A1:A-1A2-A0 = 000)
1-2-3-4-5-6-7-0 (A1:A-1/A2-A0 = 001)
2-3-4-5-6-7-0-1 (A1:A-1/A2-A0 = 010)
3-4-5-6-7-0-1-2 (A1:A-1/A2-A0 = 011)
Eight Linear Data Transfers
4-5-6-7-0-1-2-3 (A1:A-1/A2-A0 = 100)
5-6-7-0-1-2-3-4 (A1:A-1/A2-A0 = 101)
6-7-0-1-2-3-4-5 (A1:A-1/A2-A0 = 110)
7-0-1-2-3-4-5-6 (A1:A-1/A2-A0 = 111)

D A T A S H E E T
Table 6. 16-Bit and 32-Bit Linear and Burst Data Order (Continued)
Data Transfer Sequence
(Independent of the WORD# Output Data Sequence (Initial Access Address)
pin) (x16)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000)

1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-0 (A2:A-1/ A3-A0 = 0001)
2-3-4-5-6-7-8-9-A-B-C-D-E-F-0-1 (A2:A-1/ A3-A0 = 0010)
3-4-5-6-7-8-9-A-B-C-D-E-F-0-1-2 (A2:A-1/ A3-A0 = 0011)
4-5-6-7-8-9-A-B-C-D-E-F-0-1-2-3 (A:A-1/ A3-A0 = 0100)
5-6-7-8-9-A-B-C-D-E-F-0-1-2-3-4 (A2:A-1/ A3-A0 = 0101)
6-7-8-9-A-B-C-D-E-F-0-1-2-3-4-5 (A2:A-1/ A3-A0 = 0110)
Sixteen Linear Data Transfers 7-8-9-A-B-C-D-E-F-0-1-2-3-4-5-6 (A2:A-1/ A3-A0 = 0111)
(X16 Only) 8-9-A-B-C-D-E-F-0-1-2-3-4-5-6-7 (A2:A-1/ A3-A0 = 1000)
9-A-B-C-D-E-F-0-1-2-3-4-5-6-7-8 (A2:A-1/ A3-A0 = 1001)
A-B-C-D-E-F-0-1-2-3-4-5-6-7-8-9 (A2:A-1/ A3-A0 = 1010)
B-C-D-E-F-0-1-2-3-4-5-6-7-8-9-A (A2:A-1/ A3-A0 = 1011)
C-D-E-F-0-1-2-3-4-5-6-7-8-9-A-B (A2:A-1/ A3-A0 = 1100)
D-E-F-0-1-2-3-4-5-6-7-8-9-A-B-C (A2:A-1/ A3-A0 = 1101)
E-F-0-1-2-3-4-5-6-7-8-9-A-B-C-D (A2:A-1/ A3-A0 = 1110)
F-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E (A2:A-1/ A3-A0 = 1111)
0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000)

1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V-0 (A3:A-1 = 00001)
Thirty-Two Linear Data Transfers
:
U-V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T (A3:A-1 = 11110)
V-0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U (A3:A-1 = 11111)
CE# Control in Linear Mode RESET# Control in Linear Mode

The CE# (Chip Enable) pin enables the Am29BDD160 The RESET# pin immediately halts the linear burst ac-
during read mode operations. CE# must meet the re- cess when taken to V I L . The DQ data bus and
quired burst read setup times for burst cycle initiation. IND/WAIT# signal float. Additionally, the Configuration
If CE# is taken to VIH at any time during the burst lin- Register contents are reset back to the default condi-
ear or burst cycle, the device immediately exits the tion where the device is placed in asynchronous ac-
burst sequence and floats the DQ bus and IND/WAIT# cess mode.
signal. Restarting a burst cycle is accomplished by
taking CE# and ADV# to VIL. OE# Control in Linear Mode
The OE# (Output Enable) pin is used to enable the lin-
ADV# Control In Linear Mode ear burst data on the DQ data bus and the IND/WAIT#
The ADV# (Address Valid) pin is used to initiate a lin- pin. De-asserting the OE# pin to VIH during a burst op-
ear burst cycle at the clock edge when CE# and ADV# eration floats the data bus and the IND/WAIT# pin.
are at VIL and the device is configured for either linear However, the device will continue to operate internally
burst mode operation. A burst access is initiated and as if the burst sequence continues until the linear burst
the address is latched on the first rising CLK edge is complete. The OE# pin does not halt the burst se-
when ADV# is active or upon a rising ADV# edge, quence, this is accomplished by either taking CE# to
whichever occurs first. If the ADV# signal is taken to VIH or re-issuing a new ADV# pulse. The DQ bus and
VIL prior to the end of a linear burst sequence, the pre- IND/WAIT# signal remain in the float state until OE# is
vious address is discarded and subsequent burst taken to VIL.
transfers are invalid until ADV# transitions to VIH be-
fore a clock edge, which initiates a new burst se- IND/WAIT# Operation in Linear Mode
quence. The IND/WAIT#, or End of Burst Indicator signal
(when in linear modes), informs the system that the
last address of a burst sequence is on the DQ data
bus. For example, if a 4-word linear burst access is

D A T A S H E E T
enabled using a 16-bit DQ bus (WORD# = V IL ), the floats and is not driven. If OE# is at VIL, the IND/WAIT#
IND/WAIT# signal transitions active on the fourth ac- signal is driven at VIH until it transitions to VIL indicating
cess. If the same scenario is used, but instead the the end of burst sequence. The IND/WAIT# signal tim-
32-bit DQ bus is enabled, the IND/WAIT# signal transi- ing and duration is (See “Configuration Register” for
tions active on the second access. The IND/WAIT# more information). The following table lists the valid
signal has the same delay and setup timing as the DQ combinations of the Configuration Register bits that
pins. Also, the IND/WAIT# signal is controlled by the impact the IND/WAIT# timing.
OE# signal. If OE# is at V IH, the IND/WAIT# signal

D A T A S H E E T
Table 7. Valid Configuration Register Bit Definition for IND/WAIT#

DOC WC CC Definition
0 0 1 IND/WAIT# = VIL for 1-CLK cycle, Active on last transfer, Driven on rising CLK edge
0 1 1 IND/WAIT# = VIL for 1-CLK cycle, Active on second to last transfer, Driven on rising CLK edge
CE#
CLK
3 Clock Delay
ADV#
Address 1 Latched
A0-A18 Address 1 Address 2
Invalid D1 D2 D3 D0
OE#
IND/WAIT#
Note: Operation is shown for the 32-bit data bus. For a 16-bit data bus, A-1 is required. Figure shown with 3-CLK initial access
delay configuration, linear address, 4-doubleword burst, output on rising CLK edge, data hold for 1-CLK, IND/WAIT# asserted
on the last transfer before wrap-around.
Figure 2. End of Burst Indicator (IND/WAIT#) Timing for Linear 8-Word Burst Operation

D A T A S H E E T
Burst Access Timing Control with the exception that data is valid after the falling
In addition to the IND/WAIT# signal control, burst con- edge.
trols exist in the Control Register for initial access de- Table 8. Burst Initial Access Delay
lay, delivery of data on the CLK edge, and the length
of time data is held. Initial Burst Access
(CLK cycles)
Initial Burst Access Delay Control 54D,
The Am29BDD160 contains options for initial access CR13 CR12 CR11 CR10 64C, 65A
delay of a burst access. The initial access delay has 0 0 0 0 2
no effect on asynchronous read operations.
0 0 0 1 3
Burst Initial Access Delay is defined as the number of
clock cycles that must elapse from the first valid clock 0 0 1 0 4
edge after ADV# assertion (or the rising edge of 0 0 1 1 5
ADV#) until the first valid CLK edge when the data is
0 1 0 0 6
valid.
0 1 0 1 7
The burst access is initiated and the address is
latched on the first rising CLK edge when ADV# is ac- 0 1 1 0 8
tive or upon a rising ADV# edge, whichever comes 0 1 1 1 9
first. (See Table 8 describes the initial access delay
configurations.) If the Clock Configuration bit in the
Control Register is set to falling edge (CR6 = 0), the
definition remains the same for the initial delay setting
1st CLK 2nd CLK 3rd CLK 4th CLK 5th CLK
CLK
ADV# Address 1 Latched
A18-A0 Valid Address
Three CLK Delay

DQ31-DQ03 D0 D1 D2 D3 D4
Four CLK Delay
DQ31-DQ04 D0 D1 D2 D3
Five CLK Delay

DQ31-DQ05 D0 D1 D2
Figure 3. Initial Burst Delay Control

Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 is set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 1 or three clock cycles
4. CR [13-10] = 2 or four clock cycles
5. CR [13-10] = 3 or Five clock cycles

D A T A S H E E T
Burst CLK Edge Data Delivery Configuration Register does not occupy any address-
The Am29BDD160 is capable of delivering data on ei- able memory location, but rather, is accessed by the
ther the rising or falling edge of CLK. To deliver data Configuration Register commands. The Configuration
on the rising edge of CLK, bit 6 in the Control Register Register is readable any time, however, writing the
(CR6) is set to 1. To deliver data on the falling edge of Configuration Register is restricted to times when the
CLK, bit 6 in the Control Register is cleared to 0. The Embedded Algorithm™ is not active. If the user at-
default configuration is set to the rising edge. tempts to write the Configuration Register while the
Embedded Algorithm™ is active, the write operation is
Burst Data Hold Control ignored and the contents of the Configuration Register
The device is capable of holding data for one CLKs. remain unchanged.
The default configuration is to hold data for one CLK The Configuration Register is a 16 bit data field which
and is the only valid state. is accessed by DQ15–DQ0. Data on DQ31–DQ16 is
Asserting RESET# During A Burst Access ignored during a write operation when WORD# = VIL.
During a read operation, DQ31–DQ16 returns all ze-
If RESET# is asserted low during a burst access, the
roes. Table 9 shows the Configuration Register. Also,
burst access is immediately terminated and the device
Configuration Register reads operate the same as Au-
defaults back to asynchronous read mode. Refer to
toselect command reads. When the command is is-
RESET#: Hardware Reset Pin for more information on
sued, the bank address is latched along with the
the RESET# function.
command. Reads operations to the bank that was
specified during the Configuration Register read com-
Configuration Register
mand return Configuration Register contents. Read
The Am29BDD160 contains a Configuration Register operations to the other bank return flash memory data.
for configuring read accesses. The Configuration Reg- Either bank address is permitted when writing the
ister is accessed by the Configuration Register Read Configuration Register read command.
and the Configuration Register Write commands. The
Table 9. Configuration Register Definitions

CR15 CR14 CR13 CR12 CR11 CR10 CR9 CR8
RM Reserved IAD3 IAD2 IAD1 IAD0 DOC WC
BS CC Reserved Reserved Reserved BL2 BL1 BL0
Configuration Register
CR15 = Read Mode (RM)
0 = Synchronous Burst Reads Enabled
1 = Asynchronous Reads Enabled (Default)
CR14 = Reserved for Future Enhancements
These bits are reserved for future use. Set these bits to “0”.

D A T A S H E E T
Table 9. Configuration Register Definitions (Continued)

CR13–CR10 = Initial Burst Access Delay Configuration (IAD3-IAD0)
Speed Options 54D, 64C, 65A:

0000 = 2 CLK cycle initial burst access delay
0111 = 9 CLK cycle initial burst access delay—Default
CR9 = Data Output Configuration (DOC)

0 = Hold Data for 1-CLK cycle—Default
1 = Reserved
CR8 = IND/WAIT# Configuration (WC)

0 = IND/WAIT# Asserted During Delay—Default
1 = IND/WAIT# Asserted One Data Cycle Before Delay
CR7 = Burst Sequence (BS)

0 = Reserved
1 = Linear Burst Order—Default
CR6 = Clock Configuration (CC)
0 = Reserved
1 = Burst Starts and Data Output on Rising Clock Edge—Default
CR5–CR3 = Reserved For Future Enhancements (R)

These bits are reserved for future use. Set these bits to “0.”
CR2–CR0 = Burst Length (BL2–BL0)

000 = Reserved, burst accesses disabled (asynchronous reads only)
001 = 64 bit (8-byte) Burst Data Transfer - x16 and x32 Linear
010 = 128 bit (16-byte) Burst Data Transfer - x16 and x32 Linear
011 = 256 bit (32-byte) Burst Data Transfer - x16 Linear Only and x32 Linear
100 = 512 bit (64-byte) Burst Data Transfer - x16 Linear Only - Default
111 = Reserved

D A T A S H E E T
Table 10. Configuration Register After Device Reset

RM Reserve IAD3 IAD2 IAD1 IAD0 DOC WC
1 0 0 1 1 1 0 0

BS CC Reserve Reserve Reserve BL2 BL1 BL0
1 1 0 0 0 1 0 0
Initial Access Delay Configuration driven active before data will be available. This value
is determined by the input clock frequency.
The frequency configuration informs the device of the
number of clocks that must elapse after ADV# is
SECTOR PROTECTION
The Am29BDD160 features several levels of sector they must set the Persistent Sector Protection
protection, which can disable both the program and Mode Locking Bit. This will permanently set the part
erase operations in certain sectors or sector groups to operate only using Persistent Sector Protection. If
the customer decides to use the password method,
Sector and Sector Groups
they must set the Password Mode Locking Bit. This
The distinction between sectors and sector groups is will permanently set the part to operate only using
fundamental to sector protection. Sector are individual password sector protection.
sectors that can be individually sector protected/un-
protected. These are the outermost 4 kword boot sec- It is important to remember that setting either the Per-
tors, that is, SA0 to SA7 and SA38 to SA45. See sistent Sector Protection Mode Locking Bit or the
tables 11 and 12. Password Mode Locking Bit permanently selects
the protection mode. It is not possible to switch be-
Sector groups are a collection of three or four adjacent tween the two methods once a locking bit has been
32 kword sectors. For example, sector group SG8 is set. It is important that one mode is explicitly se-
comprised of sector SA8 to SA10. When any sector in lected when the device is first programmed, rather
a sector group is protected/unprotected, every sector than relying on the default mode alone. This is so
in that group is protection/unprotected. See Tables 11 that it is not possible for a system program or virus to
and 12. later set the Password Mode Locking Bit, which would
Persistent Sector Protection cause an unexpected shift from the default Persistent
Sector Protection Mode into the Password Protection
A command sector protection method that replaces Mode.
the old 12 V controlled protection method.
The WP# Hardware Protection feature is always avail-
Password Sector Protection able, independent of the software managed protection
A highly sophisticated protection method that requires method chosen.
a password before changes to certain sectors or sec-
tor groups are permitted Persistent Sector Protection
WP# Hardware Protection The Persistent Sector Protection method replaces the
old 12 V controlled protection method while at the
A write protect pin that can prevent program or erase
same time enhancing flexibility by providing three dif-
to the two outermost 8 Kbytes sectors in the 75% bank
ferent sector protection states:
All parts default to operate in the Persistent Sector
■ Persistently Locked—A sector is protected and
Protection mode. The customer must then choose if
cannot be changed.
the Persistent or Password Protection method is most
desirable. There are two one-time programmable ■ Dynamically Locked—The sector is protected and
non-volatile bits that define which sector protection can be changed by a simple command
method will be used. If the customer decides to con- ■ Unlocked—The sector is unprotected and can be
tinue using the Persistent Sector Protection method, changed by a simple command

D A T A S H E E T
In order to achieve these states, three types of “bits” switch back and forth between the protected and un-
are going to be used: protected conditions. This allows software to easily
protect sectors against inadvertent changes yet does
Persistent Protection Bit (PPB) not prevent the easy removal of protection when
A single Persistent (non-volatile) Protection Bit is as- changes are needed. The DYBs maybe set or cleared
signed to a maximum of four sectors (see the sector as often as needed.
address tables for specific sector protection group- The PPBs allow for a more static, and difficult to
ings). All 8 Kbyte boot-block sectors have individual change, level of protection. The PPBs retain their state
sector Persistent Protection Bits (PPBs) for greater across power cycles because they are Non-Volatile.
flexibility. Each PPB is individually modifiable through Individual PPBs are set with a command but must all
the PPB Write Command. be cleared as a group through a complex sequence of
Note: If a PPB requires erasure, all of the sector PPBs program and erasing commands. The PPBs are lim-
must first be preprogrammed prior to PPB erasing. All ited to 100 erase cycles.
PPBs erase in parallel, unlike programming where in- The PPB Lock bit adds an additional level of protec-
dividual PPBs are programmable. It is the responsibil- tion. Once all PPBs are programmed to the desired
ity of the user to perform the preprogramming settings, the PPB Lock may be set to “1”. Setting the
operation. Otherwise, an already erased sector PPBs PPB Lock disables all program and erase commands
has the potential of being over-erased. There is no to the Non-Volatile PPBs. In effect, the PPB Lock Bit
har dwar e m ech anis m t o pr ev ent s ec tor PP Bs locks the PPBs into their current state. The only way to
over-erasure. clear the PPB Lock is to go through a power cycle.
System boot code can determine if any changes to the
Persistent Protection Bit Lock (PPB Lock)
PPB are needed e.g. to allow new system code to be
A global volatile bit. When set to “1”, the PPBs cannot downloaded. If no changes are needed then the boot
be changed. When cleared (“0”), the PPBs are code can set the PPB Lock to disable any further
changeable. There is only one PPB Lock bit per de- changes to the PPBs during system operation.
vice. The PPB Lock is cleared after power-up or hard-
ware reset. There is no command sequence to unlock The WP# write protect pin adds a final level of hard-
the PPB Lock. ware protection to the two outermost 8 Kbytes sectors
in the 75% bank. When this pin is low it is not possible
Dynamic Protection Bit (DYB) to change the contents of these two sectors.
A volatile protection bit is assigned for each sector. It is possible to have sectors that have been persis-
After power-up or hardware reset, the contents of all tently locked, and sectors that are left in the dynamic
DYBs is “0”. Each DYB is individually modifiable state. The sectors in the dynamic state are all unpro-
through the DYB Write Command. tected. If there is a need to protect some of them, a
simple DYB Write command sequence is all that is
When the parts are first shipped, the PPBs are
necessary. The DYB write command for the dynamic
cleared, the DYBs are cleared, and PPB Lock is de-
sectors switch the DYBs to signify protected and un-
faulted to power up in the cleared state – meaning the
protected, respectively. If there is a need to change
PPBs are changeable.
the status of the persistently locked sectors, a few
When the device is first powered on the DYBs power more steps are required. First, the PPB Lock bit must
up cleared (sectors not protected). The Protection be disabled by either putting the device through a
State for each sector is determined by the logical OR power-cycle, or hardware reset. The PPBs can then
of the PPB and the DYB related to that sector. For the be changed to reflect the desired settings. Setting the
sectors that have the PPBs cleared, the DYBs control PPB lock bit once again will lock the PPBs, and the
whether or not the sector is protected or unprotected. device operates normally again.
By issuing the DYB Write command sequences, the
Note: to achieve the best protection, it’s recommended
DYBs will be set or cleared, thus placing each sector
to execute the PPB lock bit set command early in the
in the protected or unprotected state. These are the
boot code, and protect the boot code by holding WP#
so-called Dynamic Locked or Unlocked states. They
= VIL.
are called dynamic states because it is very easy to

D A T A S H E E T
Table 11. Sector Protection Schemes could not place the device in password protection
mode.
PPB
DYB PPB Lock Sector State Password Protection Mode
Unprotected—PPB and DYB are The Password Sector Protection Mode method allows
0 0 0 an even higher level of security than the Persistent
changeable
Sector Protection Mode. There are two main differ-
Unprotected—PPB not
0 0 1 ences between the Persistent Sector Protection and
changeable, DYB is changeable
the Password Sector Protection Mode:
0 1 0
■ When the device is first powered on, or comes out
Protected—PPB and DYB are
1 0 0 of a reset cycle, the PPB Lock bit set to the locked
changeable
state, rather than cleared to the unlocked state.
1 1 0
■ The only means to clear the PPB Lock bit is by writ-
0 1 1 ing a unique 64-bit Password to the device.
Protected—PPB not
1 0 1 The Password Sector Protection method is otherwise
changeable, DYB is changeable
1 1 1 identical to the Persistent Sector Protection method.
A 64-bit password is the only additional tool utilized in
Table 11 contains all possible combinations of the this method.
DYB, PPB, and PPB lock relating to the status of the The password is stored in a one-time programmable
sector. (OTP) region of the flash memory. Once the Password
In summary, if the PPB is set, and the PPB lock is set, Mode Locking Bit is set, the password is permanently
the sector is protected and the protection can not be set with no means to read, program, or erase it. The
removed until the next power cycle clears the PPB password is used to clear the PPB Lock bit. The Pass-
lock. If the PPB is cleared, the sector can be dynami- word Unlock command must be written to the flash,
cally locked or unlocked. The DYB then controls along with a password. The flash device internally
whether or not the sector is protected or unprotected. compares the given password with the pre-pro-
grammed password. If they match, the PPB Lock bit is
If the user attempts to program or erase a protected cleared, and the PPBs can be altered. If they do not
sector, the device ignores the command and returns to match, the flash device does nothing. There is a
read mode. A program command to a protected sector built-in 2 µs delay for each “password check.” This
enables status polling for approximately 1 µs before delay is intended to thwart any efforts to run a program
the device returns to read mode without having modi- that tries all possible combinations in order to crack
fied the contents of the protected sector. An erase the password.
command to a protected sector enables status polling
for approximately 50 µs after which the device returns Password and Password Mode Locking
to read mode without having erased the protected sec- Bit
tor.
In order to select the Password sector protection
The programming of the DYB, PPB, and PPB lock for scheme, the customer must first program the pass-
a given sector can be verified by writing a word. One method of choosing a password would be
DYB/PPB/PPB lock verify command to the device. to correlate it to the unique Electronic Serial Number
(ESN) of the particular flash device. Another method
could generate a database where all the passwords
Persistent Sector Protection Mode are stored, each of which correlates to a serial number
on the device. Each ESN is different for every flash
Locking Bit device; therefore each password should be different
Like the password mode locking bit, a Persistent Sec- for every flash device. While programming in the pass-
tor Protection mode locking bit exists to guarantee that word region, the customer may perform Password
the device remain in software sector protection. Once Verify operations.
set, the Persistent Sector Protection locking bit pre-
vents programming of the password protection mode Once the desired password is programmed in, the
locking bit. This guarantees that an unauthorized user customer must then set the Password Mode Locking
Bit. This operation achieves two objectives:

D A T A S H E E T
1. It permanently sets the device to operate using the during the entire program or erase operation of the two
Password Protection Mode. It is not possible to re- outermost sectors in the 75% bank.
verse this function.
2. It also disables all further commands to the pass- SecSi™ (Secured Silicon) Sector
word region. All program, and read operations are Protection
ignored. The SecSi Sector is a 256-byte flash memory area
Both of these objectives are important, and if not care- that is either programmable at the customer or by
fully considered, may lead to unrecoverable errors. AMD at the request of the customer. The SecSi Sector
The user must be sure that the Password Protection Entry command enables the host system to address
method is desired when setting the Password Mode the SecSi Sector for programming or reading. The
Locking Bit. More importantly, the user must be sure SecSi sector address range is 00000h–0003Fh for the
that the password is correct when the Password Mode top bootblock configuration and 7FFC0h–7FFFFh for
Locking Bit is set. Due to the fact that read operations the bottom bootblock configuration. Address range
are disabled, there is no means to verify what the 00040h–007FFh for the top bootblock and
password is afterwards. If the password is lost after 7F800h–7FFBFh return invalid data when addressed
setting the Password Mode Locking Bit, there will be with the SecSi sector enabled.
no way to clear the PPB Lock bit. Unlike previous flash memory devices, the
The Password Mode Locking Bit, once set, prevents Am29BDD160 allows simultaneous operation while
reading the 64-bit password on the DQ bus and further the SecSi sector is enabled. However, there are a
password programming. The Password Mode Locking number of restrictions associated with simultaneous
Bit is not erasable. Once Password Mode Locking Bit operation and device operation when the SecSi sector
is programmed, the Persistent Sector Protection Lock- is enabled:
ing Bit is disabled from programming, guaranteeing 1. The SecSi sector is not available for reading while
that no changes to the protection scheme are allowed. the Password Unlock, any PPB program/erase op-
eration, or Password programming are in progress.
64-bit Password Reading to any location in the small (25%) sector
The 64-bit Password is located in its own memory will return the status of these operations until these
space and is accessible through the use of the Pass- operations have completed execution.
word Program and Verify commands (see Password 2. Writing the corresponding DYB associated with the
Verify Command). The password function works in overlaid bootblock sector results in the DYB NOT
conjunction with the Password Mode Locking Bit, being updated. This is only accomplished when the
which when set, prevents the Password Verify com- SecSi sector is not enabled.
mand from reading the contents of the password on
the pins of the device. 3. Reading the corresponding DYB associated with
the overlaid bootblock sector results in reading in-
Write Protect (WP#) valid data when the PPB Lock/DYB Verify com-
mand is issued. This function is only accomplished
The device features a hardware protection option when the SecSi sector is not enabled.
using a write protect pin that prevents programming or
erasing, regardless of the state of the sector’s Persis- 4. All commands are available for execution when the
tent or Dynamic Protection Bits. The WP# pin is asso- SecSi sector is enabled except the following list. Is-
ciated with the two outermost 8Kbytes sectors in the suing the following commands while the SecSi sec-
75% bank. The WP# pin has no effect on any other tor is enabled results in the command being
sector. When WP# is taken to VIL, programming and ignored.
erase operations of the two outermost 8 Kbytes sec- ■ All Unlock Bypass commands
tors in the 75% bank are disabled. By taking WP# ■ CFI
back to VIH, the two outermost 8 Kbytes sectors are
enabled for program and erase operations, depending ■ Accelerated Program
upon the status of the individual sector Persistent or ■ Program and Sector Erase Suspend
Dynamic Protection Bits. If either of the two outermost ■ Program and Sector Erase Resume
sectors Persistent or Dynamic Protection Bits are pro-
grammed, program or erase operations are inhibited. 5. Executing the Sector Erase command is permitted
If the sector Persistent or Dynamic Protection Bits are when the SecSi sector is enabled, however, there is
both erased, the two sectors are available for pro- no provision for erasing the SecSi sector with the
gramming or erasing as long as WP# remains at VIH. Sector Erase command, regardless of the protec-
The user must hold the WP# pin at either V IH or VIL tion status. The Sector Erase command will erase
all other sectors when the SecSi sector is enabled.

D A T A S H E E T
6. Executing the Chip Erase command is permitted Hardware Data Protection

when the SecSi sector is enabled. The Chip Erase
The command sequence requirement of unlock cycles
command erases all sectors in the memory array
for programming or erasing provides data protection
except for sector 0 in top-bootblock configuration
against inadvertent writes. In addition, the following
and sector 45 in bottom-bootblock configuration.
hardware data protection measures prevent accidental
The SecSi Sector is a one-time programmable
erasure or programming, which might otherwise be
memory area that cannot be erased.
caused by spurious system level signals during VCC
7. Executing the SecSi Sector Entry command during power-up and power-down transitions, or from system
program or erase suspend mode is allowed. The noise.
Sector Erase/Program Resume command is dis-
abled while the SecSi sector is enabled, and the Low VCC Write Inhibit
user cannot resume programming of the memory When VCC is less than VLKO, the device does not ac-
array until the Exit SecSi Sector command is writ- cept any write cycles. This protects data during VCC
ten. power-up and power-down. The command register
and all internal erase/program circuits are disabled,
SecSi Sector Protection Bit and the device resets. Subsequent writes are ignored
The SecSi Sector Protection Bit prevents program- until VCC is greater than VLKO. The system must pro-
ming of the SecSi sector memory area. Once set, the vide the proper signals to the control pins to prevent
SecSi sector memory area contents are non-modifi- unintentional writes when VCC is greater than VLKO.
able.
Write Pulse “Glitch” Protection
Persistent Protection Bit Lock Noise pulses of less than 5 ns (typical) on OE#, CE#,
The Persistent Protection Bit (PPB) Lock is a volatile or WE# do not initiate a write cycle.
bit that reflects the state of the Password Mode Lock-
ing Bit after power-up reset. If the Password Mode Logical Inhibit
Locking Bit is set, which indicates the device is in Write cycles are inhibited by holding any one of OE# =
Password Protection Mode, the PPB Lock Bit is also VIL, CE# = VIH, or WE# = VIH. To initiate a write cycle,
set after a hardware reset (RESET# asserted) or a CE# and WE# must be a logical zero (VIL) while OE#
power-up reset. The ONLY means for clearing the is a logical one (VIH).
PPB Lock Bit in Password Protection Mode is to issue
the Password Unlock command. Successful execution Power-Up Write Inhibit
of the Password Unlock command clears the PPB If WE# = CE# = VIL and OE# = VIH during power-up,
Lock Bit, allowing for sector PPBs modifications. As- the device does not accept commands on the rising
serting RESET#, taking the device through a power-on edge of WE#. The internal state machine is automati-
reset, or issuing the PPB Lock Bit Set command sets cally reset to reading array data on power-up.
the PPB Lock Bit back to a “1”.
VCC and VIO Power-up And Power-down
If the Password Mode Locking Bit is not set, indicating
Sequencing
Persistent Sector Protection Mode, the PPB Lock Bit
is cleared after power-up or hardware reset. The PPB The device imposes no restrictions on V CC and V IO
Lock Bit is set by issuing the PPB Lock Bit Set com- power-up or power-down sequencing. Asserting RE-
mand. Once set the only means for clearing the PPB SET# to VIL is required during the entire VCC and VIO
Lock Bit is by issuing a hardware or power-up reset. power sequence until the respective supplies reach
The Password Unlock command is ignored in Persis- their operating voltages. Once, VCC and VIO attain their
tent Sector Protection Mode. respective operating voltages, de-assertion of RE-
SET# to VIH is permitted.

D A T A S H E E T
Table 12. Sector Addresses for Top Boot Sector Devices

x16 x32
Address Range Address Range Sector Size
Sector Sector Group (A18:A-1) (A18:A0) (Kwords)
SA0 (Note 1) SG0 00000h-00FFFh 00000h-007FFh 4
SA1 SG1 01000h-01FFFh 00800h-00FFFh 4
SA2 SG2 02000h-02FFFh 01000h-017FFh 4
SA3 SG3 03000h-03FFFh 01800h-01FFFh 4
SA4 SG4 04000h-04FFFh 02000h-027FFh 4
SA5 SG5 05000h-05FFFh 02800h-02FFFh 4
SA6 SG6 06000h-06FFFh 03000h-037FFh 4
Bank 1
SA7 SG7 07000h-07FFFh 03800h-03FFFh 4
(Note 2)
SA8 08000h-0FFFFh 04000h-07FFFh 32
SA9 SG8 10000h-17FFFh 08000h-0BFFFh 32
SA10 18000h-1FFFFh 0C000h-0FFFFh 32
SA11 20000h-27FFFh 10000h-13FFFh 32
SA12 28000h-2FFFFh 14000h-17FFFh 32
SG9
SA13 30000h-37FFFh 18000h-1BFFFh 32
SA15 40000h-47FFFh 20000h-23FFFh 32
SA16 48000h-4FFFFh 24000h-27FFFh 32
SG10
SA17 50000h-57FFFh 28000h-2BFFFh 32
SA19 60000h-67FFFh 30000h-33FFFh 32
SA20 68000h-6FFFFh 34000h-37FFFh 32
SG11
SA21 70000h-77FFFh 38000h-3BFFFh 32
SA23 80000h-87FFFh 40000h-43FFFh 32
SA24 88000h-8FFFFh 44000h-47FFFh 32
SG12
SA25 90000h-97FFFh 48000h-4BFFFh 32
SA27 A0000h-A7FFFh 50000h-53FFFh 32
SA28 A8000h-AFFFFh 54000h-57FFFh 32
SG13
SA29 B0000h-B7FFFh 58000h-5BFFFh 32
Bank 2
SA30 B8000h-BFFFFh 5C000h-5FFFFh 32
(Note 2)
SA31 C0000h-C7FFFh 60000h-63FFFh 32
SA32 C8000h-CFFFFh 64000h-67FFFh 32
SG14
SA33 D0000h-D7FFFh 68000h-6BFFFh 32
SA34 D8000h-DFFFFh 6C000h-6FFFFh 32
SA35 E0000h-E7FFFh 70000h-73FFFh 32
SA36 SG15 E8000h-EFFFFh 74000h-77FFFh 32
SA37 F0000h-F7FFFh 78000h-7BFFFh 32
SA38 SG16 F8000h-F8FFFh 7C000h-7C7FFh 4
SA39 SG17 F9000h-F9FFFh 7C800h-7CFFFh 4
SA40 SG18 FA000h-FAFFFh 7D000h-7D7FFh 4
SA41 SG19 FB000h-FBFFFh 7D800h-7DFFFh 4
SA42 SG20 FC000h-FCFFFh 7E000h-7E7FFh 4
SA43 SG21 FD000h-FDFFFh 7E800h-7EFFFh 4
SA44 (Note 3) SG22 FE000h-FEFFFh 7F000h-7F7FFh 4
SA45 (Note 3) SG23 FF000h-FFFFFh 7F800h-7FFFFh 4
Notes:
1. SecSi Sector overlays this sector when enabled.
2. The bank address is determined by A18 and A17. BA = 00 for Bank 1 and BA = 01, 10, or 11 for Bank 2.
3. This sector has the additional WP# pin sector protection feature.

D A T A S H E E T
Table 13. Sector Addresses for Bottom Boot Sector Devices

x16 x32
Address Range Address Range Sector Size
Sector Sector Group (A18:A-1) (A18:A0) (Kwords)
SA0 (Note 1) SG0 00000h-00FFFh 00000h-007FFh 4
SA1 (Note 1) SG1 01000h-01FFFh 00800h-00FFFh 4
SA2 SG2 02000h-02FFFh 01000h-017FFh 4
SA3 SG3 03000h-03FFFh 01800h-01FFFh 4
SA4 SG4 04000h-04FFFh 02000h-027FFh 4
SA5 SG5 05000h-05FFFh 02800h-02FFFh 4
SA6 SG6 06000h-06FFFh 03000h-037FFh 4
SA7 SG7 07000h-07FFFh 03800h-03FFFh 4
SA8 08000h-0FFFFh 04000h-07FFFh 32
SA9 SG8 10000h-17FFFh 08000h-0BFFFh 32
SA11 20000h-27FFFh 10000h-13FFFh 32
SA12 28000h-2FFFFh 14000h-17FFFh 32
SG9
SA13 30000h-37FFFh 18000h-1BFFFh 32
Bank 1
SA15 40000h-47FFFh 20000h-23FFFh 32
(Note 2)
SA16 48000h-4FFFFh 24000h-27FFFh 32
SG10
SA17 50000h-57FFFh 28000h-2BFFFh 32
SA19 60000h-67FFFh 30000h-33FFFh 32
SA20 68000h-6FFFFh 34000h-37FFFh 32
SG11
SA21 70000h-77FFFh 38000h-3BFFFh 32
SA23 80000h-87FFFh 40000h-43FFFh 32
SA24 88000h-8FFFFh 44000h-47FFFh 32
SG12
SA25 90000h-97FFFh 48000h-4BFFFh 32
SA27 A0000h-A7FFFh 50000h-53FFFh 32
SA28 A8000h-AFFFFh 54000h-57FFFh 32
SG13
SA29 B0000h-B7FFFh 58000h-5BFFFh 32
SA30 B8000h-BFFFFh 5C000h-5FFFFh 32
SA31 C0000h-C7FFFh 60000h-63FFFh 32
SA32 C8000h-CFFFFh 64000h-67FFFh 32
SG14
SA33 D0000h-D7FFFh 68000h-6BFFFh 32
SA34 D8000h-DFFFFh 6C000h-6FFFFh 32
SA35 E0000h-E7FFFh 70000h-73FFFh 32
SA36 SG15 E8000h-EFFFFh 74000h-77FFFh 32
SA37 F0000h-F7FFFh 78000h-7BFFFh 32
Bank 2
SA38 SG16 F8000h-F8FFFh 7C000h-7C7FFh 4
(Note 2)
SA39 SG17 F9000h-F9FFFh 7C800h-7CFFFh 4
SA40 SG18 FA000h-FAFFFh 7D000h-7D7FFh 4
SA41 SG19 FB000h-FBFFFh 7D800h-7DFFFh 4
SA42 SG20 FC000h-FCFFFh 7E000h-7E7FFh 4
SA43 SG21 FD000h-FDFFFh 7E800h-7EFFFh 4
SA44 SG22 FE000h-FEFFFh 7F000h-7F7FFh 4
SA45 (Note 3) SG23 FF000h-FFFFFh 7F800h-7FFFFh 4
Notes:
1. This sector has the additional WP# pin sector protection feature.
2. The bank address is determined by A18 and A17. BA = 00, 01, or 10 for Bank 1 and BA = 11 for Bank 2.
3. SecSi Sector overlays this sector when enabled.

D A T A S H E E T
COMMON FLASH MEMORY INTERFACE system can read CFI information at the addresses
(CFI) given in Tables 13–16. To terminate reading CFI data,
the system must write the reset command.
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation The system can also write the CFI query command
handshake, which allows specific vendor-specified when the device is in the autoselect mode. The device
software algorithms to be used for entire families of enters the CFI query mode, and the system can read
devices. Software support can then be device-inde- CFI data at the addresses given in Tables 13–16. The
pendent, JEDEC ID-independent, and forward- and system must write the reset command to return the de-
backward-compatible for the specified flash device vice to the autoselect mode.
families. Flash vendors can standardize their existing For further information, please refer to the CFI Specifi-
interfaces for long-term compatibility. cation and CFI Publication 100, available via the
This device enters the CFI Query mode when the sys- World Wide Web at http://www.amd.com/prod-
tem writes the CFI Query command, 98h, to address ucts/nvd/overview/cfi.html. Alternatively, contact an
55h in word mode (or address AAh in byte mode), any AMD representative for copies of these documents.
time the device is ready to read array data. The
Table 14. CFI Query Identification String

Addresses Addresses
(x32 Mode) (x16 Mode) Data Description
10h 20h 0051h
11h 22h 0052h Query Unique ASCII string “QRY”
12h 24h 0059h
13h 26h 0002h
Primary OEM Command Set
14h 28h 0000h
15h 2Ah 0040h
Address for Primary Extended Table
16h 2Ch 0000h
17h 2Eh 0000h
Alternate OEM Command Set (00h = none exists)
18h 30h 0000h
19h 32h 0000h
Address for Alternate OEM Extended Table (00h = none exists)
1Ah 34h 0000h
Table 15. CFI System Interface String

Addresses Addresses
VCC Min. (write/erase)
1Bh 36h 0023h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
VCC Max. (write/erase)
1Ch 38h 0027h
DQ7–DQ4: volts, DQ3–DQ0: 100 millivolt
1Dh 3Ah 0000h VPP Min. voltage (00h = no VPP pin present)
1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present)
1Fh 3Eh 0004h Typical timeout per single word/doubleword program 2N µs
20h 40h 0000h Typical timeout for Min. size buffer program 2N µs (00h = not supported)
21h 42h 0009h Typical timeout per individual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supported)
23h 46h 0005h Max. timeout for word/doubleword program 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0007h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)

D A T A S H E E T
Table 16. CFI Device Geometry Definition

Addresses Addresses
N
27h 4Eh 0015h Device Size = 2 byte
Flash Device Interface description (for complete description, please refer
to CFI publication 100)
0000 = x8-only asynchronous interface
28h 50h 0005h 0001 = x16-only asynchronous interface
29h 52h 0000h
0002 = supports x8 and x16 via BYTE# with asynchronous interface
0003 = x 32-only asynchronous interface
0005 = supports x16 and x32 via WORD# with asynchronous interface
2Ah 54h 0000h Max. number of byte in multi-byte program = 2N

2Bh 56h 0000h (00h = not supported)
0003h Number of Erase Block Regions within device

2Ch 58h
0004h 0003 = Speed options 54D, 65D, 65A
2Dh 5Ah 0007h

2Eh 5Ch 0000h Erase Block Region 1 Information
2Fh 5Eh 0020h (refer to the CFI specification or CFI publication 100)
30h 60h 0000h
31h 62h 001Dh

32h 64h 0000h Erase Block Region 2 Information
33h 66h 0000h (refer to the CFI specification or CFI publication 100)
34h 68h 0001h
35h 6Ah 0007h
36h 6Ch 0000h Erase Block Region 3 Information
37h 6Eh 0020h (refer to the CFI specification or CFI publication 100)
38h 70h 0000h
39h 72h 0000h

3Ah 74h 0000h Erase Block Region 4 Information
3Bh 76h 0000h (refer to the CFI specification or CFI publication 100)
3Ch 78h 0000h
Table 17. CFI Primary Vendor-Specific Extended Query

Addresses Addresses
40h 80h 0050h
41h 82h 0052h Query-unique ASCII string “PRI”
42h 84h 0049h
43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon)
44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table)
Address Sensitive Unlock (DQ1, DQ0)
00 = Required, 01 = Not Required
Silicon Revision Number (DQ5–DQ2
45h 8Ah 0004h 0000 = CS49
0001 = CS59
0010 = CS99
0011 = CS69
0100 = CS119

D A T A S H E E T
Table 17. CFI Primary Vendor-Specific Extended Query (Continued)

Addresses Addresses
Erase Suspend (1 byte)

00 = Not Supported
46h 8Ch 0002h
01 = To Read Only
02 = To Read and Write
Sector Protect (1 byte)
47h 8Eh 0001h
00 = Not Supported, X = Number of sectors in per group
Temporary Sector Unprotect

48h 90h 0000h
00h = Not Supported, 01h = Supported
Sector Protect/Unprotect scheme (1 byte)
01 =29F040 mode, 02 = 29F016 mode
03 = 29F400 mode, 04 = 29LV800 mode
49h 92h 0006h
05 = 29BDS640 mode (Software Command Locking)
06 = BDD160 mode (New Sector Protect)
07 = 29LV800 + PDL128 (New Sector Protect) mode
Simultaneous Operation (1 byte)

4Ah 94h 001Fh
00h = Not Supported, X = Number of sectors in all banks except Bank 1
Burst Mode Type

4Bh 96h 0001h
00h = Not Supported, 01h = Supported
Page Mode Type

4Ch 98h 0000h
00h = Not Supported, 01h = 4 Word Page, 02h = 8 Word Page
ACC (Acceleration) Supply Minimum
4Dh 9Ah 00B5h
00h = Not Supported (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
ACC (Acceleration) Supply Maximum

4Eh 9Ch 00C5h
00h = Not Supported, (DQ7-DQ4: volt in hex, DQ3-DQ0: 100 mV in BCD)
Top/Bottom Boot Sector Flag (1 byte)

00h = Uniform device, no WP# control,
01h = 8 x 8 Kb sectors at top and bottom with WP# control
02h = Bottom boot device
4Fh 9Eh 0001h
03h = Top boot device
04h = Uniform, Bottom WP# Protect
05h = Uniform, Top WP# Protect
If the number of erase block regions = 1, then ignore this field
Program Suspend
50h A0h 0001h 00 = Not Supported
01 = Supported
Write Buffer Size

51h A2h 0000h
2(N+1) word(s)
Bank Organization (1 byte)
57h AEh 0002h 00 = If data at 4Ah is zero
XX = Number of banks
Bank 1 Region Information (1 byte)

58h B0h 000Fh
XX = Number of Sectors in Bank 1
59h B2h 001Fh

5Ah B4h 0000h

5Bh B6h 0000h

D A T A S H E E T
COMMAND DEFINITIONS
Writing specific address and data commands or se- The RESET# command will not terminate the Burst
quences into the command register initiates device op- mode. System reset (power on reset) will terminate
erations. Tables 18-21 define the valid register the Burst mode.
command sequences. Writing incorrect address and
The device has the regular control pins, i.e. Chip En-
data values or writing them in the improper se-
able (CE#), Write Enable (WE#), and Output Enable
quence resets the device to reading array data.
(OE#) to control normal read and write operations.
All addresses are latched on the falling edge of WE# Moreover, three additional control pins have been
or CE#, whichever happens later. All data is latched on added to allow easy interface with minimal glue logic
the rising edge of WE# or CE#, whichever happens to a wide range of microprocessors / microcontrollers
first. Refer to the AC Characteristics section for timing for high performance Burst read capability. These ad-
diagrams. ditional pins are Address Valid (ADV#) and Clock
(CLK). CE#, OE#, and WE# are asynchronous (rela-
Reading Array Data in Non-burst Mode tive to CLK). The Burst mode read operation is a syn-
The device is automatically set to reading array data chronous operation tied to the edge of the clock. The
after device power-up. No commands are required to microprocessor / microcontroller supplies only the ini-
retrieve data. The device is also ready to read array tial address, all subsequent addresses are automati-
data after completing an Embedded Program or Em- cally generated by the device with a timing defined by
bedded Erase algorithm. the Configuration Register definition. The Burst read
cycle consists of an address phase and a correspond-
After the device accepts an Erase Suspend com- ing data phase.
mand, the device enters the Erase Suspend mode.
The system can read array data using the standard During the address phase, the Address Valid (ADV#)
read timings, except that if it reads at an address pin is asserted (taken Low) for one clock period. To-
within erase-suspended sectors, the device outputs gether with the edge of the CLK, the starting burst ad-
status data. After completing a programming opera- dress is loaded into the internal Burst Address
tion in the Erase Suspend mode, the system may Counter. The internal Burst Address Counter can be
once again read array data with the same exception. configured to either the Linear modes (See “Initial Ac-
See Sector Erase and Program Suspend Command cess Delay Configuration”).
for more information on this mode. During the data phase, the first burst data is available
The system must issue the reset command to re-en- after the initial access time delay defined in the Config-
able the device for reading array data if DQ5 goes high, uration Register. For subsequent burst data, every ris-
or while in the autoselect mode. See the The program- ing (or falling) edge of the CLK will trigger the output
ming of the PPB Lock Bit for a given sector can be ver- data with the burst output delay and sequence defined
ified by writing a PPB Lock Bit status verify command in the Configuration Register.
to the device. section. Tables 17–20 show all the commands executed by the
See also Asynchronous Read Operation (Non-Burst) in device. The device automatically powers up in the
the Key to Switching Waveforms section for more read/reset state. It is not necessary to issue a read/re-
information. See the Sector Erase and Program Resume set command after power-up or hardware reset.
Command sections for more information on this mode.
Read/Reset Command
Reading Array Data in Burst Mode After power-up or hardware reset, the Am29BDD160
The device is capable of very fast Burst mode read op- automatically enter the read state. It is not necessary
erations. The configuration register sets the read con- to issue the reset command after power-up or hard-
figuration, burst order, frequency configuration, and ware reset. Standard microprocessor cycles retrieve
burst length. array data, however, after power-up, only asynchro-
nous accesses are permitted since the Configuration
Upon power on, the device defaults to the asynchro- Register is at its reset state with burst accesses dis-
nous mode. In this mode, CLK, and ADV# are ignored. abled.
The device operates like a conventional Flash device.
Data is available tACC/tCE nanoseconds after address The Reset command is executed when the user needs
becomes stable, CE# become asserted. The device to exit any of the other user command sequences
enters the burst mode by enabling synchronous burst (such as autoselect, program, chip erase, etc.) to re-
reads in the configuration register. The device exits turn to reading array data. There is no latency be-
burst mode by disabling synchronous burst reads in tween executing the Reset command and reading
the configuration register. (See Command Definitions). array data.

D A T A S H E E T
The Reset command does not disable the SecSi sec- Except for Program Suspend, any commands written
tor if it is enabled. This function is only accomplished to the device during the Embedded Program Algorithm
by issuing the SecSi Sector Exit command. are ignored. Note that a hardware reset immediately
terminates the programming operation. The command
Autoselect Command sequence should be reinitiated once that bank has re-
Flash memories are intended for use in applications turned to reading array data, to ensure data integrity.
where the local CPU alters memory contents. As such, Programming is allowed in any sequence and across
manufacturer and device codes must be accessible sector boundaries. A bit cannot be programmed
while the device resides in the target system. PROM from a “0” back to a “1”. Attempting to do so may
programmers typically access the signature codes by halt the operation and set DQ5 to “1,” or cause the
raising A9 to VID. However, multiplexing high voltage Data# Polling algorithm to indicate the operation was
onto the address lines is not generally desired system successful. However, a succeeding read will show that
design practice. the data is still “0”. Only erase operations can convert
The Am29BDD160 contains an Autoselect Command a “0” to a “1”.
operation to supplement traditional PROM program-
ming methodology. The operation is initiated by writing Accelerated Program Command
the Autoselect command sequence into the command The Accelerated Chip Program mode is designed to
register. The bank address (BA) is latched during the improve the Word or Double Word programming
autoselect command sequence write operation to dis- speed. Improving the programming speed is accom-
tinguish which bank the Autoselect command refer- plished by using the ACC pin to supply both the word-
ences. Reading the other bank after the Autoselect line voltage and the bitline current instead of using the
command is written results in reading array data from VPP pump and drain pump, which is limited to 2.5 mA.
the other bank and the specified address. Following Because the external ACC pin is capable of supplying
the command write, a read cycle from address significantly large amounts of current compared to the
(BA)XX00h retrieves the manufacturer code of drain pump, all 32 bits are available for programming
(BA)XX01h. Three sequential read cycles at ad- with a single programming pulse. This is an enormous
dresses (BA) XX01h, (BA) XX0Eh, and (BA) XX0Fh improvement over the standard 5-bit programming. If
read the three-byte device ID (see Tables 19 and 20). the user is able to supply an external power supply
All manufacturer and device codes exhibit odd parity and connect it to the ACC pin, significant time savings
with the MSB of the lower byte (DQ7) defined as the are realized.
parity bit.
In order to enter the Accelerated Program mode, the
(The Autoselect Command requires the user to exe- ACC pin must first be taken to VHH (12 V ± 0.5 V) and
cute the Read/Reset command to return the device followed by the one-cycle command with the program
back to reading the array contents.) address and data to follow. The Accelerated Chip Pro-
gram command is only executed when the device is in
Program Command Sequence Unlock Bypass mode and during normal read/reset
Programming is a four-bus-cycle operation. The pro- operating mode.
gram command sequence is initiated by writing two In this mode, the write protection function is bypassed
unlock write cycles, followed by the program set-up unless the PPB Lock Bit = 1.
command. The program address and data are written
next, which in turn initiate the Embedded Program al- The Accelerated Program command is not permitted if
gorithm. The system is not required to provide further the SecSi sector is enabled.
controls or timings. The device automatically gener-
ates the program pulses and verifies the programmed Unlock Bypass Command Sequence
cell margin. Tables 18 and 20 shows the address and The unlock bypass feature allows the system to pro-
data requirements for the program command se- gram words to the device faster than using the stan-
quence. dard program command sequence. The unlock bypass
command sequence is initiated by first writing two un-
During the Embedded Program algorithm, the system
lock cycles. This is followed by a third write cycle con-
can determine the status of the program operation by
taining the unlock bypass command, 20h. The device
using DQ7, DQ6, or RY/BY#. (See Write Operation
then enters the unlock bypass mode. A two-cycle un-
Status for information on these status bits.) When the
lock bypass program command sequence is all that is
Embedded Program algorithm is complete, the device
required to program in this mode. The first cycle in this
returns to reading array data and addresses are no
sequence contains the unlock bypass program com-
longer latched. Note that an address change is re-
mand, A0h; the second cycle contains the program
quired to begin read valid array data.
address and data. Additional data is programmed in

D A T A S H E E T
the same manner. This mode dispenses with the initial and CFI commands. This feature permits slow PROM
two unlock cycles required in the standard program programmers to significantly improve program-
command sequence, resulting in faster total programming/erase throughput since the command sequence
ming time. Tables 18 and 20 show the requirements for often requires microseconds to execute a single write
the command sequence. operation. Therefore, once the Unlock Bypass com-
mand is issued, only the two-cycle program and erase
During the unlock bypass mode, only the Unlock By-
bypass commands are required. The Unlock Bypass
pass Program and Unlock Bypass Reset commands
Command is ignored if the SecSi sector is enabled. To
are valid. To exit the unlock bypass mode, the system
return back to normal operation, the Unlock Bypass
must issue the two-cycle unlock bypass reset com-
Reset Command must be issued.
mand sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are The following four sections describe the commands
don’t care for both cycles. The device then returns to that may be executed within the unlock bypass mode.
reading array data.
Unlock Bypass Program Command
Figure 5 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in AC The Unlock Bypass Program command is a two-cycle
Characteristics for parameters, and to Figure 22 for command that consists of the actual program com-
timing diagrams. mand (A0h) and the program address/data combina-
tion. This command does not require the two-cycle
“unlock” sequence since the Unlock Bypass command
was previously issued. As with the standard program
START
command, multiple Unlock Bypass Program com-
mands can be issued once the Unlock Bypass com-
mand is issued.
Write Program To return back to standard read operations, the Unlock
Command Sequence Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if
the SecSi sector is enabled.
Data Poll
from System Unlock Bypass Chip Erase Command
Embedded
Program The Unlock Bypass Chip Erase command is a 2-cycle
algorithm command that consists of the erase setup command
in progress
(80h) and the actual chip erase command (10h). This
Verify Data? command does not require the two-cycle “unlock” se-
No
quence since the Unlock Bypass command was previ-
ously issued. Unlike the standard erase command,
Yes there is no Unlock Bypass Erase Suspend or Erase
Resume commands.
No To return back to standard read operations, the Unlock
Increment Address Last Address?
Bypass Reset command must be issued.
The Unlock Bypass Program Command is ignored if
Yes the SecSi sector is enabled.
Programming
Unlock Bypass CFI Command
Completed
The Unlock Bypass CFI command is available for
PROM programmers and target systems to read the
Note: See Tables 18 and 20 for program command se-
CFI codes while in Unlock Bypass mode. See Com-
quence.
mon Flash Memory Interface (CFI) for specific CFI
Figure 4. Program Operation codes.
To return back to standard read operations, the Unlock
Bypass Reset command must be issued.
Unlock Bypass Entry Command The Unlock Bypass Program Command is ignored if
The Unlock Bypass command, once issued, is used to the SecSi sector is enabled.
bypass the “unlock” sequence for program, chip erase,

D A T A S H E E T
Unlock Bypass Reset Command tor address (any address location within the desired
The Unlock Bypass Reset command places the device sector) is latched on the falling edge of WE# or CE#
in standard read/reset operating mode. Once exe- (whichever occurs last) while the command (30h) is
cuted, normal read operations and user command se- latched on the rising edge of WE# or CE# (whichever
quences are available for execution. occurs first).
The Unlock Bypass Program Command is ignored if Specifying multiple sectors for erase is accomplished
the SecSi sector is enabled. by writing the six bus cycle operation, as described
above, and then following it by additional writes of only
Chip Erase Command the last cycle of the Sector Erase command to ad-
dresses or other sectors to be erased. The time be-
The Chip Erase command is used to erase the entire tween Sector Erase command writes must be less
flash memory contents of the chip by issuing a single than 80 µs, otherwise the command is rejected. It is
command. Chip erase is a six-bus cycle operation. recommended that processor interrupts be disabled
There are two “unlock” write cycles, followed by writing during this time to guarantee this critical timing condi-
the erase “set up” command. Two more “unlock” write tion. The interrupts can be re-enabled after the last
cycles are followed by the chip erase command. Chip Sector Erase command is written. A time-out of 80 µs
erase does not erase protected sectors. from the rising edge of the last WE# (or CE#) will ini-
The chip erase operation initiates the Embedded tiate the execution of the Sector Erase command(s). If
Erase algorithm, which automatically preprograms and another falling edge of the WE# (or CE#) occurs within
verifies the entire memory to an all zero pattern prior the 80 µs time-out window, the timer is reset. Once the
to electrical erase. The system is not required to pro- 80 µs window has timed out and erasure has begun,
vide any controls or timings during these operations. only the Erase Suspend command is recognized (see
Note that a hardware reset immediately terminates Sector Erase and Program Suspend Command and
the programming operation. The command sequence Sector Erase and Program Resume Command sec-
should be reinitiated once that bank has returned to tions). If that occurs, the sector erase command se-
reading array data, to ensure data integrity. quence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
The Embedded Erase algorithm erase begins on the Loading the sector erase registers may be done in any
rising edge of the last WE# or CE# pulse (whichever sequence and with any number of sectors.
occurs first) in the command sequence. The status of
the erase operation is determined three ways: Sector erase does not require the user to program the
device prior to erase. The device automatically prepro-
■ Data# polling of the DQ7 pin (see DQ7: Data# Poll- grams all memory locations, within sectors to be
ing) erased, prior to electrical erase. When erasing a sec-
■ Checking the status of the toggle bit DQ6 (see DQ6: tor or sectors, the remaining unselected sectors or the
Toggle Bit I) write protected sectors are unaffected. The system is
■ Checking the status of the RY/BY# pin (see not required to provide any controls or timings during
RY/BY#: Ready/Busy#) sector erase operations. The Erase Suspend and
Erase Resume commands may be written as often as
Once erasure has begun, only the Erase Suspend required during a sector erase operation.
command is valid. All other commands are ignored.
Automatic sector erase operations begin on the rising
When the Embedded Erase algorithm is complete, the edge of the WE# or CE# pulse of the last sector erase
device returns to reading array data, and addresses command issued, and once the 80 µs time-out window
are no longer latched. Note that an address change is has expired. The status of the sector erase operation
required to begin read valid array data. is determined three ways:
Figure 5 illustrates the Embedded Erase Algorithm. ■ Data# polling of the DQ7 pin
See the Erase/Program Operations tables in AC Char-
acteristics for parameters, and to Figure 22 for timing ■ Checking the status of the toggle bit DQ6
diagrams. ■ Checking the status of the RY/BY# pin
Further status of device activity during the sector
Sector Erase Command erase operation is determined using toggle bit DQ2
The Sector Erase command is used to erase individ- (refer to DQ2: Toggle Bit II).
ual sectors or the entire flash memory contents. Sec-
When the Embedded Erase algorithm is complete, the
tor erase is a six-bus cycle operation. There are two
device returns to reading array data, and addresses
“unlock” write cycles, followed by writing the erase “set
are no longer latched. Note that an address change is
up” command. Two more “unlock” write cycles are
required to begin read valid array data.
then followed by the erase command (30h). The sec-

D A T A S H E E T
Figure 5 illustrates the Embedded™ Erase Algorithm, The counter is incremented by one every time an
using a typical command sequence and bus operation. erase pulse is initiated, regardless of whether or not
Refer to the Erase/Program Operations tables in the that erase pulse is successful. An erase pulse is ter-
AC Characteristics section for parameters, and to Fig- minated immediately when the suspend command
ure 22 for timing diagrams. is executed. A new erase pulse is initiated when the
resume command is executed (and the counter is
incremented).
START ■ Given that 300 successful erase pulses are re-
quired, a successful sector erase operation shall
have a maximum of 5680 erase suspends.
Write Erase The Sector Erase and Program Suspend command is
Command Sequence ignored if written during the execution of the Chip
Erase operation or Embedded Program Algorithm (but
will reset the chip if written improperly during the com-
mand sequences). Writing the Sector Erase and Pro-
Data Poll gram command during the Sector Erase time-out
from System results in immediate termination of the time-out period
Embedded
and suspension of the erase operation. Once in Erase
Erase
algorithm
Suspend, the device is available for reading (note that
in progress in the Erase Suspend mode, the Reset command is
No not required for read operations and is ignored) or pro-
Data = FFh?
gram operations in sectors not being erased. Any
other command written during the Erase Suspend
mode is ignored, except for the Sector Erase and Pro-
Yes
gram Resume command. Writing the Erase and Pro-
gram Resume command resumes the sector erase
Erasure Completed operation. The bank address of the erase suspended
bank is required when writing this command
Notes: If the Sector Erase and Program Suspend command
1. See Tables 18 and 20 for erase command sequence. is written during a programming operation, the device
2. See DQ3: Sector Erase Timer for more information. suspends programming operations and allows only
read operations in sectors not selected for program-
Figure 5. Erase Operation ming. Further nesting of either erase or programming
operations is not permitted. Table 18 summarizes per-
missible operations during Erase and Program Sus-
Sector Erase and Program Suspend pend. (A busy sector is one that is selected for
programming or erasure.):
Command
The Sector Erase and Program Suspend command al- Table 18. Allowed Operations During
lows the user to interrupt a Sector Erase or Program Erase/Program Suspend
operation and perform data read or programs in a sec- Sector Program Suspend Erase Suspend
tor that is not being erased or to the sector where a Busy Sector Program Resume Erase Resume
programming operation was initiated. This command Non-busy
Read Only Read or Program
is applicable only during the Sector Erase and Pro- sectors
gramming operation, which includes the time-out pe-
When the Sector Erase and Program Suspend com-
riod for Sector Erase.
mand is written during a Sector Erase operation, the
chip will take between 0.1 µs and 20 µs to actually
Sector Erase and Program Suspend
suspend the operation and go into the erase sus-
Operation Mechanics pended read mode (pseudo-read mode), at which time
■ A successful erase pulse has a duration or 1.2 ms the user can read or program from a sector that is not
± 20%, depending on the number of previous erase erase suspended. Reading data in this mode is the
cycles (among other factors). same as reading from the standard read mode, except
■ A successful sector erase operation requires 300 that the data must be read from sectors that have not
successful erase pulses. been erase suspended.
■ An internal counter monitors the number of erase Polling DQ6 on two immediately consecutive reads
pulses initiated and has a maximum value of 5980. from a given address provides the system with the

D A T A S H E E T
ability to determine if the device is in Erase or Program tents. The contents of the Configuration Register are
Suspend. Before the device enters Erase or Program place on DQ15–DQ0. If WORD# is at VIH (32-bit DQ
Suspend, the DQ6 pin toggles between two immedi- Bus), the contents of DQ31–DQ16 are XXXXh and
ately consecutive reads from the same address. After should be ignored. The user should execute the
the device has entered Erase suspend, DQ6 stops Read/Reset command to place the device back in
toggling between two immediately consecutive reads standard user operation after executing the Configura-
to the same address. During the Sector Erase operation Register Read command.
tion and also in Erase suspend mode, two immediately
The Configuration Register Read Command is fully
consecutive readings from the erase-suspended sec-
operational if the SecSi sector is enabled.
tor causes DQ2 to toggle. DQ2 does not toggle if read-
ing from a non-busy (non-erasing) sector (stored data
Configuration Register Write Command
is read). No bits are toggled during program suspend
mode. Software must keep track of the fact that the The Configuration Register Write command is used to
device is in a suspended mode. modify the contents of the Configuration Register. Ex-
ecution of this command is only allowed while in user
After entering the erase-suspend-read mode, the sys- mode and is not available during Unlock Bypass mode
tem may read or program within any non-suspended or during Security mode. The Configuration Register
sector: Write command is preceded by the standard two-cycle
■ A read operation from the erase-suspended bank “unlock” sequence, followed by the Configuration Reg-
returns polling data during the first 8 µs after the ister Write command (D0h), and finally followed by
erase suspend command is issued; read operations writing the contents of the Configuration Register to
thereafter return array data. Read operations from any address. The contents of the Configuration Regis-
the other bank return array data with no latency. ter are place on DQ15–DQ0. If WORD# is at V IH
(32-bit DQ Bus), the contents of DQ31–DQ16 are
■ A program operation while in the erase suspend
XXXXh and are ignored. Writing the Configuration
mode is the same as programming in the regular
Register while an Embedded Algorithm™ or Erase
program mode, except that the data must be pro-
Suspend modes are executing results in the contents
grammed to a sector that is not erase suspended.
of the Configuration Register not being updated.
Write operation status is obtained in the same man-
ner as a normal program operation. The Configuration Register Read Command is fully
operational if the SecSi sector is enabled.
Sector Erase and Program Resume
Command Common Flash Interface (CFI) Command
The Sector Erase and Program Resume command The Common Flash Interface (CFI) command pro-
(30h) resumes a Sector Erase or Program operation vides device size, geometry, and capability information
that has been suspended. Any further writes of the directly to the users system. Flash devices that sup-
Sector Erase and Program Resume command ig- port CFI, have a “Query Command” that returns infor-
nored. However, another Sector Erase and Program mation about the device to the system. The Query
Suspend command can be written after the device has structure contents are read at the specific address lo-
resumed sector erase operations. Note that until a cations following a single system write cycle where:
suspended program or erase operation has resumed, ■ A 98h query command code is written to 55h ad-
the contents of that sector are unknown. dress location within the device’s address space
The Sector Erase and Program Resume Command is ■ The device is initially in any valid read state, such as
ignored if the SecSi sector is enabled. “Read Array” or “Read ID Data”
Configuration Register Read Command Other device statistics may exist within a long se-
quence of commands or data input; such sequences
The Configuration Register Read command is used to must first be completed or terminated before writing of
verify the contents of the Configuration Register. Exe- the 98H Query command, otherwise invalid Query
cution of this command is only allowed while in user data structure output may result.
mode and is not available during Unlock Bypass mode
or during Security mode. The Configuration Register No t e t ha t f or d a ta bu s bi t s gr e a te r th a n DQ 7
Read command is preceded by the standard two-cycle (DQ31–DQ8), the valid Query access code has all ze-
“unlock” sequence, followed by the Configuration Reg- roes (“0”s) in the upper DQ bus locations. Thus, the
ister Read command (C6h), and finally followed by 16-bit Query command code is 0098h and the 32-bit
performing a read operation to the bank address spec- Query command code is 00000098h.
ified when the C6h command was written. Reading the To terminate the CFI operation, it is necessary to exe-
other bank results in reading the flash memory con- cute the Read/Reset command.

D A T A S H E E T
The CFI command is not permitted if the SecSi sector See Common Flash Memory Interface (CFI) for the
is enabled and Simultaneous Operation is disabled specific CFI command codes.
once the command is entered.

D A T A S H E E T
SecSi Sector Entry Command tions while they are in progress, thus making the
SecSi sector unavailable for reading. If the SecSi sec-
The SecSi Sector Entry command enables the SecSi
tor is enabled while the DYB command is issued, the
(OTP) sector to overlay the 8 KB outermost sector in
DYB for the overlayed sector is NOT updated. Read-
the small (25%) bank. The SecSi sector overlays
ing the DYB status using the PPB Lock Bit/DYBDYB
00000h–0003Fh for the top bootblock configuration
verify command when the SecSi sector is enabled re-
and 7FFC0h–7FFFFh for the bottom bootblock confiu-
turns invalid data.
ration. Address range 00040h–007FFh for the top
bootblock and 7F800h–7FFBFh return invalid data
Password Program Command
when addressed with the SecSi sector enabled. The
following commands are permitted after issuing the The Password Program Command permits program-
SecSi Sector Entry command: ming the password that is used as part of the hard-
ware protection scheme. The actual password is
1. Autoselect 64-bits long. Depending upon the state of the WORD#
2. Password Program (x16 and x32) pin, multiple Password Program Commands are re-
3. Password Verify quired. For a x16 bit data bus, 4 Password Program
commands are required to program the password. For
4. Password Unlock (x16 and x32) a x32 bit data bus, 2 Password Program commands
5. Read/Reset are required. The user must enter the unlock cycle,
6. Program password program command (38h) and the program
address/data for each portion of the password when
7. Chip and Sector Erase programming. There are no provisions for entering the
8. SecSi Sector Protection Bit Program 2-cycle unlock cycle, the password program com-
9. PPB Program mand, and all the password data. There is no special
addressing order required for programming the pass-
10.All PPB Erase word. Also, when the password is undergoing pro-
11. PPB Lock Bit Set gramming, Simultaneous Operation is disabled. Read
12.DYB Write operations to any memory location will return the pro-
gramming status. Once programming is complete, the
13.DYB/PPB/PPB Lock Bit Verify user must issue a Read/Reset command to return the
14.Security Reset device to normal operation. Once the Password is
15.Configuration Register Write written and verified, the Password Mode Locking Bit
must be set in order to prevent verification. The Pass-
16.Configuration Register Read word Program Command is only capable of program-
The following commands are unavailable when the ming “0”s. Programming a “1” after a cell is
SecSi sector is enabled. Issuing the following com- programmed as a “0” results in a time-out by the Em-
mands while the SecSi sector is enabled results in the bedded Program Algorithm™ with the cell remaining
command being ignored. as a “0”. The password is all F’s when shipped from
the factory. All 64-bit password combinations are valid
1. Unlock Bypass as a password.
2. CFI
Password Programming is permitted if the SecSi sec-
3. Accelerated Program tor is enabled.
4. Program and Sector Erase Suspend
Password Verify Command
5. Program and Sector Erase Resume
The Password Verify Command is used to verify the
The SecSi Sector Entry command is allowed when the Password. The Password is verifiable only when the
device is in either program or erase suspend modes. If Password Mode Locking Bit is not programmed. If the
the SecSi sector is enabled, the program or erase sus- Password Mode Locking Bit is programmed and the
pend command is ignored. This prevents resuming ei- user attempts to verify the Password, the device will
ther programming or erasure on the SecSi sector if the always drive all F’s onto the DQ data bus.
overlayed sector was undergoing programming or era-
sure. The host system must ensure that the device The Password Verify command is permitted if the
resume any suspended program or erase opera- SecSi sector is enabled. Also, the device will not oper-
tion after exiting the SecSi sector. ate in Simultaneous Operation when the Password
Verify command is executed. Only the password is re-
Executing any of the PPB program/erase commands, turned regardless of the bank address. The lower two
or Password Unlock command results in the small address bits (A0:A-1) are valid during the Password
bank (25% bank) returning the status of these opera-

D A T A S H E E T
Verify. Writing the Read/Reset command returns the The SecSi Sector Protection Bit Program command is
device back to normal operation. permitted if the SecSi sector is enabled.
Password Protection Mode Locking Bit PPB Lock Bit Set Command
Program Command The PPB Lock Bit Set command is used to set the
The Password Protection Mode Locking Bit Program PPB Lock bit if it is cleared either at reset or if the
Command programs the Password Protection Mode Password Unlock command was successfully exe-
Locking Bit, which prevents further verifies or updates cuted. There is no PPB Lock Bit Clear command.
to the Password. Once programmed, the Password Once the PPB Lock Bit is set, it cannot be cleared un-
Protection Mode Locking Bit cannot be erased! If the less the device is taken through a power-on clear or
Password Protection Mode Locking Bit is verified as the Password Unlock command is executed. Upon
program without margin, the Password Protection setting the PPB Lock Bit, the PPBs are latched into the
Mode Locking Bit Program command can be executed DYBs. If the Password Mode Locking Bit is set, the
to improve the program margin. Once the Password PPB Lock Bit status is reflected as set, even after a
Protection Mode Locking Bit is programmed, the Per- power-on reset cycle. Exiting the PPB Lock Bit Set
sistent Sector Protection Locking Bit program circuitry command is accomplished by writing the Read/Reset
is disabled, thereby forcing the device to remain in the command.
Password Protection mode. Exiting the Mode Locking The PPB Lock Bit Set command is permitted if the
Bit Program command is accomplished by writing the SecSi sector is enabled.
Read/Reset command.
The Password Protection Mode Locking Bit Program DYB Write Command
command is permitted if the SecSi sector is enabled. The DYB Write command is used to set or clear a DYB
for a given sector. The high order address bits
Persistent Sector Protection Mode (A18–A11) are issued at the same time as the code
Locking Bit Program Command 01h or 00h on DQ7-DQ0. All other DQ data bus pins
The Persistent Sector Protection Mode Locking Bit are ignored during the data write cycle. The DYBs are
Program Command programs the Persistent Sector modifiable at any time, regardless of the state of the
Protection Mode Locking Bit, which prevents the Pass- PPB or PPB Lock Bit. The DYBs are cleared at
word Mode Locking Bit from ever being programmed. power-up or hardware reset.Exiting the DYB Write
If the Persistent Sector Protection Mode Locking Bit is command is accomplished by writing the Read/Reset
verified as programmed without margin, the Persistent command.
Sector Protection Mode Locking Bit Program Com- The DYB Write command is permitted if the SecSi
mand should be reissued to improve program margin. sector is enabled.
By disabling the program circuitry of the Password
Mode Locking Bit, the device is forced to remain in the Password Unlock Command
Persistent Sector Protection mode of operation, once
The Password Unlock command is used to clear the
this bit is set. Exiting the Persistent Protection Mode
PPB Lock Bit so that the PPBs can be unlocked for
Locking Bit Program command is accomplished by
modification, thereby allowing the PPBs to become ac-
writing the Read/Reset command.
cessible for modification. The exact password must be
The Persistent Sector Protection Mode Locking Bit entered in order for the unlocking function to occur.
Program command is permitted if the SecSi sector is This command cannot be issued any faster than 2 µs
enabled. at a time to prevent a hacker from running through the
all 64-bit combinations in an attempt to correctly match
SecSi Sector Protection Bit Program a password. If the command is issued before the 2 µs
Command execution window for each portion of the unlock, the
command will be ignored.
The SecSi Sector Protection Bit Program Command
programs the SecSi Sector Protection Bit, which pre- The Password Unlock function is accomplished by
vents the SecSi sector memory from being cleared. If writing Password Unlock command and data to the
the SecSi Sector Protection Bit is verified as pro- device to perform the clearing of the PPB Lock Bit.
grammed without margin, the SecSi Sector Protection The password is 64 bits long, so the user must write
Bit Program Command should be reissued to improve the Password Unlock command 2 times for a x32 bit
program margin. Exiting the V CC-level SecSi Sector data bus and 4 times for a x16 data bus. A0 is used to
Protection Bit Program Command is accomplished by determine whether the 32 bit data quantity is used to
writing the Read/Reset command. match the upper 32 bits or lower 32 bits. A0 and A-1 is
used for matching when the x16 bit data bus is se-

D A T A S H E E T
lected (WORD# = 0). Writing the Password Unlock All PPB Erase Command
command is address order specific. In other words, for
The All PPB Erase command is used to erase all
the x32 data bus configuration, the lower 32 bits of the
PPBs in bulk. There is no means for individually eras-
password are written first and then the upper 32 bits of
ing a specific PPB. Unlike the PPB program, no spe-
the password are written. For the x16 data bus config-
cific sector address is required. However, when the
uration, the lower address A0:A-1= 00, the next Pass-
PPB erase command is written (60h) and A6 = 1, all
word Unlock command is to A0:A -1 = 01, then to
Sector PPBs are erased in parallel. If the PPB Lock Bit
A0:A-1= 10, and finally to A0:A-1= 11. Writing out of se-
is set the ALL PPB Erase command will not execute
quence results in the Password Unlock not returning a
and the command will time-out without erasing the
match with the password and the PPB Lock Bit re-
PPBs. The host system must determine whether all
mains set.
PPB has been fully erased by noting the status of DQ0
Once the Password Unlock command is entered, the in the sixth cycle of the All PPB Erase command. If
RDY/BSY# pin goes LOW indicating that the device is DQ0 = 1, the entire six-cycle All PPB Erase command
busy. Also, reading the small bank (25% bank) results sequence must be reissued until DQ0 = 1.
in the DQ6 pin toggling, indicating that the Password
It is the responsibility of the user to preprogram all
Unlock function is in progress. Reading the large bank
PPBs prior to issuing the All PPB Erase command. If
(75% bank) returns actual array data. Approximately
the user attempts to erase a cleared PPB, over-era-
1uSec is required for each portion of the unlock. Once
sure may occur making it difficult to program the PPB
the first portion of the password unlock completes
at a later time. Also note that the total number of PPB
(RDY/BSY# is not driven and DQ6 does not toggle
program/erase cycles is limited to 100 cycles. Cycling
when read), the Password Unlock command is issued
the PPBs beyond 100 cycles is not guaranteed.
again, only this time with the next part of the pass-
word. If WORD# = 1, the second Password Unlock The All PPB Erase command is permitted if the SecSi
command is the final command before the PPB Lock sector is enabled.
Bit is cleared (assuming a valid password). If WORD#
= 0, this is the fourth Password Unlock command. In DYB Write
x16 mode, four Password Unlock commands are re- The DYB Write command is used for setting the DYB,
quired to successfully clear the PPB Lock Bit. As with which is a volatile bit that is cleared at reset. There is
the first Password Unlock command, the RY/BY# sig- one DYB per sector. If the PPB is set, the sector is
nal goes LOW and reading the device results in the protected regardless of the value of the DYB. If the
DQ6 pin toggling on successive read operations until PPB is cleared, setting the DYB to a 1 protects the
complete. It is the responsibility of the microprocessor sector from programs or erases. Since this is a volatile
to keep track of the number of Password Unlock com- bit, removing power or resetting the device will clear
mands (2 for x32 bus and 4 for x16 bus), the order, the DYBs. The bank address is latched when the com-
and when to read the PPB Lock bit to confirm suc- mand is written.
cessful password unlock
The DYB Write command is permitted if the SecSi
The Password Unlock command is permitted if the sector is enabled.
SecSi sector is enabled.
PPB Lock Bit Set
PPB Program Command
The PPB Lock Bit set command is used for setting the
The PPB Program command is used to program, or DYB, which is a volatile bit that is cleared at reset.
set, a given PPB. Each PPB is individually pro- There is one DYB per sector. If the PPB is set, the
grammed (but is bulk erased with the other PPBs). sector is protected regardless of the value of the DYB.
The specific sector address (A18–A11) are written at If the PPB is cleared, setting the DYB to a 1 protects
the same time as the program command 60h with A6 the sector from programs or erases. Since this is a vol-
= 0. If the PPB Lock Bit is set and the corresponding atile bit, removing power or resetting the device will
PPB is set for the sector, the PPB Program command clear the DYBs. The bank address is latched when the
will not execute and the command will time-out without command is written.
programming the PPB.
The PPB Lock command is permitted if the SecSi sec-
The host system must determine whether a PPB has tor is enabled.
been fully programmed by noting the status of DQ0 in
the sixth cycle of the PPB Program command. If DQ0 DYB Status
= 0, the entire six-cycle PPB Program command se-
quence must be reissued until DQ0 = 1. The programming of the DYB for a given sector can be
verified by writing a DYB status verify command to the
device.

D A T A S H E E T
PPB Status status is read on DQ0. Figure 4 shows a typical flow

for programming the non-volatile bit and Figure 5
The programming of the PPB for a given sector can be
shows a typical flow for erasing the non-volatile bits.
verified by writing a PPB status verify command to the
The SecSi Sector Protection, Password Locking, Per-
device.
sistent Sector Protection Mode Locking bits are not
erasable after they are programmed. However, the
PPB Lock Bit Status
PPBs are both erasable and programmable (depend-
The programming of the PPB Lock Bit for a given sec- ing upon device security).
tor can be verified by writing a PPB Lock Bit status
verify command to the device. Unlike Single High Voltage Sector Protect/Unprotect,
the A6 pin no longer functions as the program/erase
Non-volatile Protection Bit Program And selector nor the program/erase margin enable. In-
stead, this function is accomplished by issuing the
Erase Flow
specific command for either program (68h) or erase
The device uses a standard command sequence for (60h).
programming or erasing the SecSi Sector Protection,
Password Locking, Persistent Sector Protection Mode In asynchronous mode, the DQ6 toggle bit indicates
Locking, or Persistent Protection Bits. Unlike devices whether the program or erase sequence is active. (In
that have the Single High Voltage Sector Unpro- synchronous mode, ADV# indicates the status.) If the
tect/Protect feature, the Am29BDD160 has the stan- DQ6 toggle bit toggles with either OE# or CE#, the
dard two-cycle unlock followed by 60h, which places non-volatile bit program or erase operation is in
the device into non-volatile bit program or erase mode. progress. When DQ6 stops toggling, the value of the
Once the mode is entered, the specific non-volatile bit non-volatile bit is available on DQ0.

D A T A S H E E T
Table 19. Memory Array Command Definitions (x32 Mode)

Bus Cycles (Notes 1–4)
Cycles
Command (Notes) First Second Third Fourth Fifth Sixth
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (5) 1 RA RD
Reset (6) 1 XXX F0
Autoselect Manufacturer ID 4 555 AA 2AA 55 555 90 (BA)X00 01
(7) Device ID (11) 6 555 AA 2AA 55 555 90 (BA)X01 7E (BA)X0E 08 (BA)X0F 00/01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Program/Erase Suspend (12) 1 BA B0
Program/Erase Resume (13) 1 BA 30
CFI Query (14, 15) 1 55 98
Accelerated Program (16) 2 XX A0 PA PD
Configuration Register Verify (15) 3 555 AA 2AA 55 (BA)555 C6 (BA)XX RD
Configuration Register Write (17) 4 555 AA 2AA 55 555 D0 XX WD
Unlock Bypass Entry (18) 3 555 AA 2AA 55 555 20
Unlock Bypass Program (18) 2 XX A0 PA PD
Unlock Bypass Erase (18) 2 XX 80 XX 10
Unlock Bypass CFI (14, 18) 1 XX 98
Unlock Bypass Reset (18) 2 XX 90 XX 00
Legend:
BA = Address of the bank that is being switched to autoselect mode, RA = Read Address (A18:A0).
is in bypass mode, or is being erased. Determined by A18 and A17, RD = Read Data (DQ31:DQ0) from location RA.
see Tables 11 and 12 for more detail. SA = Sector Address (A18:A11) for verifying (in autoselect mode),
PA = Program Address (A18:A0). Addresses latch on the falling edge erasing, or applying security commands.
of the WE# or CE# pulse, whichever happens later. WD = Write Data. See “Configuration Register” definition for specific
PD = Program Data (DQ31:DQ0) written to location PA. Data latches write data. Data latched on rising edge of WE#.
on the rising edge of WE# or CE# pulse, whichever happens first. X = Don’t care
Notes:
1. See Table 1 for description of bus operations. 9. This command is ignored during any embedded program, erase
2. All values are in hexadecimal. or suspended operation.
3. Shaded cells in table denote read cycles. All other cycles are 10. Valid read operations include asynchronous and burst read mode
write operations. operations.
4. During unlock cycles, (lower address bits are 555 or 2AAh as 11. The device ID must be read across the fourth, fifth, and sixth
shown in table) address bits higher than A11 (except where BA is cycles. 00h in the sixth cycle indicates top boot block, 01h
required) and data bits higher than DQ7 are don’t cares. indicates bottom boot block.
5. No unlock or command cycles required when bank is reading 12. The system may read and program in non-erasing sectors, or
array data. enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
6. The Reset command is required to return to the read mode (or to
during a sector erase operation, and requires the bank address.
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while 13. The Program/Erase Resume command is valid only during the
the bank is providing status information). Erase Suspend mode, and requires the bank address.
7. The fourth cycle of the autoselect command sequence is a read 14. Command is valid when device is ready to read array data or
cycle. The system must provide the bank address to obtain the when device is in autoselect mode.
manufacturer ID or device ID information. See the Autoselect 15. Asynchronous read operations.
Command section for more information.
16. ACC must be at VID during the entire operation of this command.
8. This command cannot be executed until The Unlock Bypass
17. Command is ignored during any Embedded Program, Embedded
command must be executed before writing this command
Erase, or Suspend operation.
sequence. The Unlock Bypass Reset command must be
executed to return to normal operation. 18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.

D A T A S H E E T
Table 20. Sector Protection Command Definitions (x32 Mode)

Bus Cycles (Notes 1-4)
Cycles
Reset 1 XXX F0
SecSi Sector Entry 3 555 AA 2AA 55 555 88
SecSi Sector Exit 4 555 AA 2AA 55 555 90 XX 00
SecSi Protection Bit Program (5, 6) 6 555 AA 2AA 55 555 60 OW 68 OW 48 OW RD(0)
SecSi Protection Bit Status 6 555 AA 2AA 55 555 60 OW RD(0)
Password Program (5, 7, 8) 4 555 AA 2AA 55 555 38 PWA[0-1] PWD[0-1]
Password Verify 4 555 AA 2AA 55 555 C8 PWA[0-1] PWD[0-1]
Password Unlock (7, 8) 5 555 AA 2AA 55 555 28 PWA[0-1] PWD[0-1]
PPB Program (5, 6) 6 555 AA 2AA 55 555 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)
All PPB Erase (5, 9, 10) 6 555 AA 2AA 55 555 60 WP 60 (SA)WP 40 (SA)WP RD(0)
PPB Status (11, 12) 4 555 AA 2AA 55 555 90 (SA)X02 00/01
PPB Lock Bit Set 3 555 AA 2AA 55 555 78
PPB Lock Bit Status 4 555 AA 2AA 55 (BA) 555 58 SA RD(1)
DYB Write (7) 4 555 AA 2AA 55 555 48 SA X1
DYB Erase (7) 4 555 AA 2AA 55 555 48 SA X0
DYB Status (12) 4 555 AA 2AA 55 (BA) 555 58 SA RD(0)
PPMLB Program (5,6) 6 555 AA 2AA 55 555 60 PL 68 PL 48 PL RD(0)
PPMLB Status (5) 6 555 AA 2AA 55 555 60 PL RD(0)
SPMLB Program (5, 6) 6 555 AA 2AA 55 555 60 SL 68 SL 48 SL RD(0)
SPMLB Status (5) 6 555 AA 2AA 55 555 60 SL RD(0)
DYB = Dynamic Protection Bit RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
OW = Address (A5–A0) is (011X10). 1, if unprotected, DQ1 = 0.
PPB = Persistent Protection Bit SA = Sector Address where security command applies. Address bits
PWA = Password Address. A0 selects between the low and high A18:A11 uniquely select any sector.
32-bit portions of the 64-bit Password SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
PWD = Password Data. Must be written over two cycles. WP = PPB Address (A5–A0) is (111X10)
PL = Password Protection Mode Lock Address (A5–A0) is (001X10) X = Don’t care
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0= 1, PPMLB = Password Protection Mode Locking Bit
if unprotected, DQ0 = 0. SPMLB = Persistent Protection Mode Locking Bit
1. See Table 1 for description of bus operations. 7. Data is latched on the rising edge of WE#.
2. All values are in hexadecimal. 8. The entire four bus-cycle sequence must be entered for each
3. Shaded cells in table denote read cycles. All other cycles are portion of the password.
write operations. 9. The fourth cycle erases all PPBs. The fifth and sixth cycles are
4. During unlock cycles, (lower address bits are 555 or 2AAh as used to validate whether the bits have been fully erased. If DQ0
shown in table) address bits higher than A11 (except where BA is (in the sixth cycle) reads 1, the erase command must be issued
required) and data bits higher than DQ7 are don’t cares. and verified again.
5. The reset command returns the device to reading the array. 10. Before issuing the erase command, all PPBs should be
programmed in order to prevent over-erasure of PPBs.
6. The fourth cycle programs the addressed locking bit. The fifth and
sixth cycles are used to validate whether the bit has been fully 11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
programmed. If DQ0 (in the sixth cycle) reads 0, the program set.
command must be issued and verified again. 12. The status of additional PPBs and DYBs may be read (following
the fourth cycle) without reissuing the entire command sequence.

D A T A S H E E T
Table 21. Memory Array Command Definitions (x16 Mode)

Bus Cycles (Notes 1–4)
Cycles
Read (5) 1 RA RD
Reset (6) 1 XXX F0
Autoselect Manufacturer ID 4 AAA AA 555 55 AAA 90 (BA)X00 01
(7) Device ID (11) 6 AAA AA 555 55 AAA 90 (BA)X02 7E (BA)X1C 08 (BA)X1E 00/01
Program 4 AAA AA 555 55 AAA A0 PA PD
Chip Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 555 10
Sector Erase 6 AAA AA 555 55 AAA 80 AAA AA 555 55 SA 30
Program/Erase Suspend (12) 1 BA B0
Program/Erase Resume (13) 1 BA 30
CFI Query (14, 15) 1 AA 98
Accelerated Program (16) 2 XX A0 PA PD
Configuration Register Verify (15) 3 AAA AA 555 55 (BA)555 C6 (BA)XX RD
Configuration Register Write (17) 4 AAA AA 555 55 AAA D0 XX WD
Unlock Bypass Entry (18) 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (18) 2 XX A0 PA PD
Unlock Bypass Erase (18) 2 XX 80 XX 10
Unlock Bypass CFI (14, 18) 1 XX 98
Unlock Bypass Reset (18) 2 XX 90 XX 00
Legend:
BA = Address of the bank that is being switched to autoselect mode, RA = Read Address (A18:A-1).
is in bypass mode, or is being erased. Determined by A18 and A17, RD = Read Data (DQ15:DQ0) from location RA.
see Tables 11 and 12 for more detail. SA = Sector Address (A18:A11) for verifying (in autoselect mode),
PA = Program Address (A18:A-1). Addresses latch on the falling edge erasing, or applying security commands.
of the WE# or CE# pulse, whichever happens later. WD = Write Data. See “Configuration Register” definition for specific
PD = Program Data (DQ15:DQ0) written to location PA. Data latches write data. Data latched on rising edge of WE#.
on the rising edge of WE# or CE# pulse, whichever happens first. X = Don’t care
Notes:
1. See Table 1 for description of bus operations. 9. This command is ignored during any embedded program, erase
2. All values are in hexadecimal. or suspended operation.
3. Shaded cells in table denote read cycles. All other cycles are 10. Valid read operations include asynchronous and burst read mode
write operations. operations.
4. During unlock cycles, (lower address bits are AAA or 555h as 11. The device ID must be read across the fourth, fifth, and sixth
shown in table) address bits higher than A11 (except where BA is cycles. 00h in the sixth cycle indicates top boot block, 01h
required) and data bits higher than DQ7 are don’t cares. indicates bottom boot block.
5. No unlock or command cycles required when bank is reading 12. The system may read and program in non-erasing sectors, or
array data. enter the autoselect mode, when in the Program/Erase Suspend
mode. The Program/Erase Suspend command is valid only
6. The Reset command is required to return to the read mode (or to
during a sector erase operation, and requires the bank address.
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while 13. The Program/Erase Resume command is valid only during the
the bank is providing status information). Erase Suspend mode, and requires the bank address.
7. The fourth cycle of the autoselect command sequence is a read 14. Command is valid when device is ready to read array data or
cycle. The system must provide the bank address to obtain the when device is in autoselect mode.
manufacturer ID or device ID information. See the Autoselect 15. Asynchronous read operations.
Command section for more information.
16. ACC must be at VID during the entire operation of this command.
8. This command cannot be executed until The Unlock Bypass
17. Command is ignored during any Embedded Program, Embedded
command must be executed before writing this command
Erase, or Suspend operation.
sequence. The Unlock Bypass Reset command must be
executed to return to normal operation. 18. The Unlock Bypass Entry command is required prior to any
Unlock Bypass operation. The Unlock Bypass Reset command is
required to return to the read mode.

D A T A S H E E T
Table 22. Sector Protection Command Definitions (x16 Mode)

Bus Cycles (Notes 1-4)
Cycles
Reset 1 XXX F0
SecSi Sector Entry 3 AAA AA 555 55 AAA 88
SecSi Sector Exit 4 AAA AA 555 55 AAA 90 XX 00
SecSi Protection Bit Program
6 AAA AA 555 55 AAA 60 OW 68 OW 48 OW RD(0)
(5, 6)
SecSi Protection Bit Status 6 AAA AA 555 55 AAA 60 OW RD(0)
Password Program (5, 7, 8) 5 AAA AA 555 55 AAA 38 PWA[0–3] PWD[0–3]
Password Verify 4 AAA AA 555 55 AAA C8 PWA[0–3] PWD[0–3]
Password Unlock (7, 8) 5 AAA AA 555 55 AAA 28 PWA[0–3] PWD[0–3]
PPB Program (5, 6) 6 AAA AA 555 55 AAA 60 (SA)WP 68 (SA)WP 48 (SA)WP RD(0)
All PPB Erase (5, 9, 10) 6 AAA AA 555 55 AAA 60 WP 60 (SA)WP 40 (SA)WP RD(0)
PPB Status (11, 12) 4 AAA AA 555 55 AAA 90 (SA)X04 00/01
PPB Lock Bit Set 3 AAA AA 555 55 AAA 78
PPB Lock Bit Status 4 AAA AA 555 55 (BA) AAA 58 SA RD(1)
DYB Write (7) 4 AAA AA 555 55 AAA 48 SA X1
DYB Erase (7) 4 AAA AA 555 55 AAA 48 SA X0
DYB Status (12) 4 AAA AA 555 55 (BA) AAA 58 SA RD(0)
PPMLB Program (5, 6) 6 AAA AA 555 55 AAA 60 PL 68 PL 48 PL RD(0)
PPMLB Status (5) 6 AAA AA 555 55 AAA 60 PL RD(0)
SPMLB Program (5, 6) 6 AAA AA 555 55 AAA 60 SL 68 SL 48 SL RD(0)
SPMLB Status (5) 6 AAA AA 555 55 AAA 60 SL RD(0)
Legend:
DYB = Dynamic Protection Bit RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
OW = Address (A5–A0) is (011X10). 1, if unprotected, DQ1 = 0.
PD3:0 = Four 32-bit quantities representing the password. SA = Sector Address where security command applies. Address bits
PPB = Persistent Protection Bit A18:A11 uniquely select any sector.
PWA = Password Address. A0:A-1 selects between the low and high SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
16-bit portions of the 64-bit Password WP = PPB Address (A5–A0) is (111X10)
PWD = Password Data.Must be written over four cycles. X = Don’t care
PL = Password Protection Mode Lock Address (A5-A0) is (001X10) PPMLB = Password Protection Mode Locking Bit
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0 = SPMLB = Persistent Protection Mode Locking Bit
1, if unprotected, DQ0 = 0.
1. See Table 1 for description of bus operations. 8. The entire four bus-cycle sequence must be entered for each
2. All values are in hexadecimal. portion of the password. PWA[0–3] represent the four addresses
over which the password is stored. PWD[0–3] represent the four
3. Shaded cells in table denote read cycles. All other cycles are
word data that comprise the password.
write operations.
9. The fourth cycle erases all PPBs. The fifth and sixth cycles are
4. During unlock cycles, (lower address bits are AAA or 555h as
used to validate whether the bits have been fully erased. If DQ0
shown in table) address bits higher than A11 (except where BA is
(in the sixth cycle) reads 1, the erase command must be issued
required) and data bits higher than DQ7 are don’t cares.
and verified again.
5. The reset command returns the device to reading the array.
10. Before issuing the erase command, all PPBs should be
6. The fourth cycle programs the addressed locking bit. The fifth and programmed in order to prevent over-erasure of PPBs.
sixth cycles are used to validate whether the bit has been fully
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
programmed. If DQ0 (in the sixth cycle) reads 0, the program
set.
command must be issued and verified again.
12. The status of additional PPBs and DYBs may be read (following
7. Data is latched on the rising edge of WE#.
the fourth cycle) without reissuing the entire command sequence.

D A T A S H E E T
WRITE OPERATION STATUS gorithm, Erase Suspend, Erase Suspend-Program

mode, or sector erase time-out.
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, If the user attempts to write to a protected sector,
and RY/BY#. Table 23 and the following subsections Data# polling will be activated for about 1 µs: the de-
describe the functions of these bits. DQ7, RY/BY#, and vice will then return to read mode, with the data from
DQ6 each offer a method for determining whether a the protected sector unchanged. If the user attempts
program or erase operation is complete or in progress. to erase a protected sector, Toggle Bit (DQ6) will be
These three bits are discussed first. activated for about 150 µs; the device will then return
to read mode, without having erased the protected
DQ7: Data# Polling sector.
The Am29BDD160 features a Data# polling flag as a Table 23 shows the outputs for Data# Polling on DQ7.
method to indicate to the host system whether the em- Figure 6 shows the Data# Polling algorithm. Figure 27
bedded algorithms are in progress or are complete. shows the timing diagram for synchronous status DQ7
During the Embedded Program Algorithm an attempt data polling.
to read the bank in which programming was initiated
will produce the complement of the data last written to
DQ7. Upon completion of the Embedded Program Al- RY/BY#: Ready/Busy#
gorithm, an attempt to read the device will produce the
The device provides a RY/BY# open drain output pin as
true last data written to DQ7. Note that DATA# polling
a way to indicate to the host system that the Embedded
returns invalid data for the address being programmed
Algorithms are either in progress or have been com-
or erased.
pleted. If the output is low, the device is busy with either
For example, the data read for an address pro- a program, erase, or reset operation. If the output is
grammed as 0000 0000 1000 0000b will return XXXX floating, the device is ready to accept any read/write or
XXXX 0XXX XXXXb during an Embedded Program erase operation. When the RY/BY# pin is low, the de-
operation. Once the Embedded Program Algorithm is vice will not accept any additional program or erase
complete, the true data is read back on DQ7. Note that commands with the exception of the Erase suspend
at the instant when DQ7 switches to true data, the command. If the device has entered Erase Suspend
other bits may not yet be true. However, they will all be mode, the RY/BY# output will be floating. For program-
true data on the next read from the device. Please ming, the RY/BY# is valid (RY/BY# = 0) after the rising
note that Data# polling may give misleading status edge of the fourth WE# pulse in the four write pulse se-
when an attempt is made to write to a protected sec- quence. For chip erase, the RY/BY# is valid after the
tor. rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the RY/BY# is also valid
For chip erase, the Data# polling flag is valid after the
after the rising edge of the sixth WE# pulse.
rising edge of the sixth WE# pulse in the six write
pulse sequence. For sector erase, the Data# polling is If RESET# is asserted during a program or erase oper-
valid after the last rising edge of the sector erase WE# ation, the RY/BY# pin remains a “0” (busy) until the in-
pulse. Data# polling must be performed at sector ad- ternal reset operation is complete, which requires a
dresses within any of the sectors being erased and not time of tREADY (during Embedded Algorithms). The sys-
a sector that is a protected sector. Otherwise, the sta- tem can thus monitor RY/BY# to determine whether the
tus may not be valid. DQ7 = 0 during an Embedded reset operation is complete. If RESET# is asserted
Erase Algorithm (chip erase or sector erase operation) when a program or erase operation is not executing
but will return a “1” after the operation completes be- (RY/BY# pin is “floating”), the reset operation is com-
cause it will have dropped back into read mode. pleted in a time of tREADY (not during Embedded Algo-
rithms). The system can read data t RH after the
In asynchronous mode, just prior to the completion of
RESET# pin returns to VIH.
the Embedded Algorithm operations, DQ7 may
change asynchronously while OE# is asserted low. (In Since the RY/BY# pin is an open-drain output, several
synchronous mode, ADV# exhibits this behavior.) The RY/BY# pins can be tied together in parallel with a
status information may be invalid during the instance pull-up resistor to VCC. An external pull-up resistor is re-
of transition from status information to array (memory) quired to take RY/BY# to a VIH level since the output is
data. An extra validity check is therefore specified in an open drain.
the data polling algorithm. The valid array data on
Table 23 shows the outputs for RY/BY#. Figures 15, 19,
DQ31–DQ0 (DQ15–DQ0 when WORD# = 0) is avail-
21 and 22 shows RY/BY# for read, reset, program, and
able for reading on the next successive read attempt.
erase operations, respectively.
The Data# polling feature is only active during the Em-
bedded Programming Algorithm, Embedded Erase Al-

D A T A S H E E T
During an Embedded Program or Erase algorithm op-

START
eration, two immediately consecutive read cycles to
any address cause DQ6 to toggle. When the operation
is complete, DQ6 stops toggling. For asynchronous
mode, either OE# or CE# can be used to control the
Read DQ7–DQ0
read cycles. For synchronous mode, the rising edge of
Addr = VA ADV# is used or the rising edge of clock while ADV# is
Low.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for
Yes approximately 100 µs, then returns to reading array
DQ7 = Data? data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected sec-
tors, and ignores the selected sectors that are protected.
No
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is
No DQ5 = 1? erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Sus-
Yes pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
Read DQ7–DQ0 can use DQ7 (see the subsection on DQ7: Data# Poll-
Addr = VA ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
Yes array data.
DQ7 = Data?
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Pro-
No gram algorithm is complete.
PASS Table 23 shows the outputs for Toggle Bit I on DQ6.

FAIL
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2
Notes: explains the algorithm. Figure 25 in the AC Character-
1. VA = Valid address for programming. During a sector istics section shows the toggle bit timing diagrams. Fig-
erase operation, a valid address is an address within any ure 25 shows the differences between DQ2 and DQ6 in
sector selected for erasure. During chip erase, a valid graphical form. See also the subsection on DQ2: Tog-
address is any non-protected sector address. gle Bit II. Figure 27 shows the timing diagram for syn-
2. DQ7 should be rechecked even if DQ5 = “1” because chronous toggle bit status.
DQ7 may change simultaneously with DQ5.
DQ2: Toggle Bit II
Figure 6. Data# Polling Algorithm The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
DQ6: Toggle Bit I II is valid after the rising edge of the final WE# pulse in
Toggle Bit I on DQ6 indicates whether an Embedded the command sequence.
Program or Erase algorithm is in progress or complete, DQ2 toggles when the system performs two immedi-
or whether the device has entered the Erase Suspend ately consecutive reads at addresses within those sec-
mode. Toggle Bit I may be read at any address, and is tors that have been selected for erasure. (For
valid after the rising edge of the final WE# pulse in the asynchronous mode, either OE# or CE# can be used
command sequence (prior to the program or erase op- to control the read cycles. For synchronous mode,
eration), and during the sector erase time-out. ADV# is used.) But DQ2 cannot distinguish whether

D A T A S H E E T
the sector is actively erasing or is erase-suspended.

DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot START
distinguish which sectors are selected for erasure.
Thus, both status bits are required for sector and mode
information. Refer to Table 23 to compare outputs for Read Byte
DQ2 and DQ6. (DQ0-DQ7)
Address = VA
Figure 7 shows the toggle bit algorithm in flowchart
form, and the section Reading Toggle Bits DQ6/DQ2 Read Byte
explains the algorithm. See also the DQ6: Toggle Bit I (DQ0-DQ7) (Note 1)
subsection. Figure 25 shows the toggle bit timing dia- Address = VA
gram. Figure 25 shows the differences between DQ2
and DQ6 in graphical form. Figure 27 shows the timing
diagram for synchronous DQ2 toggle bit status. No
DQ6 = Toggle?
Reading Toggle Bits DQ6/DQ2
Refer to Figure 25 for the following discussion. When- Yes
ever the system initially begins reading toggle bit sta-
tus, it must perform two immediately consecutive
reads of DQ7–DQ0 to determine whether a toggle bit No DQ5 = 1?
is toggling. Typically, the system would note and store
the value of the toggle bit after the first read. After the
second read, the system would compare the new Yes
value of the toggle bit with the first. If the toggle bit is
not toggling, the device has completed the program or Read Byte Twice
erase operation. The system can read array data on (DQ 0-DQ7) (Notes
DQ7–DQ0 on the following read cycle. Adrdess = VA 1, 2)
However, if after the initial two immediately consecutive

read cycles, the system determines that the toggle bit
is still toggling, the system also should note whether No
DQ6 = Toggle?
the value of DQ5 is high (see the section on DQ5). If it
is, the system should then determine again whether the
toggle bit is toggling, since the toggle bit may have Yes
stopped toggling just as DQ5 went high. If the toggle bit
is no longer toggling, the device has successfully com-
pleted the program or erase operation. If it is still tog- FAIL PASS
gling, the device did not complete the operation
successfully, and the system must write the reset com-
mand to return to reading array data. Notes:
1. Read toggle bit with two immediately consecutive reads
The remaining scenario is that the system initially to determine whether or not it is toggling. See text.
determines that the toggle bit is toggling and DQ5 has 2. Recheck toggle bit because it may stop toggling as DQ5
not gone high. The system may continue to monitor the changes to “1”. See text.
toggle bit and DQ5 through successive read cycles,
Figure 7. Toggle Bit Algorithm
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform The DQ5 failure condition may appear if the system
other system tasks. In this case, the system must start tries to program a “1” to a location that is previously
at the beginning of the algorithm when it returns to programmed to “0.” Only an erase operation can
determine the status of the operation (top of Figure 7). change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has
DQ5: Exceeded Timing Limits exceeded the timing limits, DQ5 produces a “1.”
DQ5 indicates whether the program or erase time has Under both these conditions, the system must issue
exceeded a specified internal pulse count limit. Under the reset command to return the device to reading
these conditions DQ5 produces a “1.” This is a failure array data.
condition that indicates the program or erase cycle was
not successfully completed.

D A T A S H E E T
DQ3: Sector Erase Timer After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
After writing a sector erase command sequence, the
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
system may read DQ3 to determine whether or not an
cepted the command sequence, and then read DQ3. If
erase operation has begun. (The sector erase timer
DQ3 is “1”, the internally controlled erase cycle has be-
does not apply to the chip erase command.) If additional
gun; all further commands (other than Erase Suspend)
sectors are selected for erasure, the entire time-out also
are ignored until the erase operation is complete. If
applies after each additional sector erase command.
DQ3 is “0”, the device will accept additional sector
When the time-out is complete, DQ3 switches from “0”
erase commands. To ensure the command has been
to “1.” The system may ignore DQ3 if the system can
accepted, the system software should check the status
guarantee that the time between additional sector
of DQ3 prior to and following each subsequent sector
erase commands will always be less than 50 µs. See
erase command. If DQ3 is high on the second status
also the Sector Erase Command section.
check, the last command might not have been ac-
cepted. Table 23 shows the outputs for DQ3.
Table 23. Write Operation Status

DQ7 DQ5 DQ2
Operation (Note 2) DQ6 (Note 1) DQ3 (Note 2) RY/BY#
Standard Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle 0
Mode Embedded Erase Algorithm 0 Toggle 0 1 Toggle 0
Reading within Erase
1 No toggle 0 N/A Toggle 1
Erase Suspended Sector
Suspend Reading within Non-Erase
Data Data Data Data Data 1
Mode Suspended Sector
Erase-Suspend-Program DQ7# Toggle 0 N/A N/A 0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

D A T A S H E E T
ABSOLUTE MAXIMUM RATINGS

Storage Temperature 20 ns 20 ns
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
+0.8 V
Ambient Temperature
with Power Applied . . . . . . . . . . . . . –65°C to +145°C –0.5 V
VCC, VIO(Note 1) . . . . . . . . . . . . . . . . –0.5 V to + 3.0 V
–2.0 V
ACC, A9, OE#, and RESET# (Note 2) . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.5 V to +13.0 V 20 ns
Address, Data, Control Signals
(with the exception of CLK) (Note 1) –0.5 V to 3.6 V Figure 8. Maximum Negative Overshoot
All other pins (Note 1). . . . . . . . . . .–0.5 V to +5.5 V Waveform
Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During 20 ns
voltage transitions, input at I/O pins may overshoot VSS to VCC
–2.0 V for periods of up to 20 ns. See Figure 9. Maximum +2.0 V
DC voltage on output and I/O pins is 3.6 V. During voltage VCC
transitions output pins may overshoot to VCC + 2.0 V for +0.5 V
periods up to 20 ns. See Figure 9.
2.0 V
2. Minimum DC input voltage on pins ACC, A9, OE#, and
RESET# is -0.5 V. During voltage transitions, A9, OE#, 20 ns 20 ns
and RESET# may overshoot VSS to –2.0 V for periods of
up to 20 ns. See Figure 8. Maximum DC input voltage on
pin A9 and OE# is +13.0 V which may overshoot to 14.0 Figure 9. Maximum Positive Overshoot
V for periods up to 20 ns. Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
4. Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the de-
vice at these or any other conditions above those indi-
cated in the operational sections of this data sheet is not
implied. Exposure of the device to absolute maximum rat-
ing conditions for extended periods may affect device reli-
ability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –40°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range . . . . . . 2.5 V to 2.75 V
VIO Supply Voltages
VIO . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.65 V to 2.75 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.

D A T A S H E E T
DC CHARACTERISTICS
CMOS Compatible
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VIO, VIO = VIO max ±1.0 µA
ILIWP Input Load Current, WP# VIN = VSS to VIO, VIO = VIO max –25 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
VCC Active Burst Read Current CE# = VIL, 56 MHz

ICCB 8 Double-Word 70 90 mA
(Note 1) OE# = VIL 66 MHz
VCC Active Asynchronous Read Current

ICC1 CE# = VIL, OE# = VIL 1 MHz 4 mA
(Note 1)
ICC3 VCC Active Program Current (Notes 2, 4) CE# = VIL, OE# = VIH, ACC = VIH 40 50 mA
ICC4 VCC Active Erase Current (Notes 2, 4) CE# = VIL, OE# = VIH, ACC = VIH 20 50 mA
ICC5 (Note 5) VCC Standby Current (CMOS) VCC= VCC max, CE# = VCC ± 0.3 V 60 µA
ICC6 VCC Active Current (Read While Write) CE# = VIL, OE# = VIL 30 90 mA
ICC7 (Note 5) VCC Reset Current RESET# = VIL 60 µA
ICC8 (Note 5) Automatic Sleep Mode Current VIH = VCC ± 0.3 V, VIL = VSS ± 0.3 V 60 µA
IACC VACC Acceleration Current ACC = VHH 20 mA
VIL Input Low Voltage –0.5 0.3 x VIO V
VIH Input High Voltage 0.7 x VIO 3.6 V
VILCLK CLK Input Low Voltage –0.2 0.3 x VIO V
VIHCLK CLK Input High Voltage 0.7 x VCC 2.75 V
VID Voltage for Autoselect VCC = 2.5 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
IOLRB RY/BY#, Output Low Current VOL = 0.4 V 8 mA
VHH Accelerated (ACC pin) High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 x VCC V
VOH Output High Voltage IOH = –100 µA, VCC = VCC min VIO –0.1 V
VLKO Low VCC Lock-Out Voltage (Note 3) 1.6 2.0 V
Notes:
1. The ICC current listed includes both the DC operating current and the frequency dependent component.
2. ICC active while Embedded Erase or Embedded Program is in progress.
3. Not 100% tested.
4. Maximum ICC specifications are tested with VCC = VCCmax.
5. Current maximum has been increased significantly from datasheet Revision B+4, Dated April 8, 2003.

D A T A S H E E T
DC CHARACTERISTICS (Continued)
Zero Power Flash
5
Supply Current in mA
0
0 500 1000 1500 2000 2500 3000 3500 4000
Time in ns
Note: Addresses are switching at 1 MHz

Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
20
2.7 V
16
Supply Current in mA
12
0
1 2 3 4 5
Frequency in MHz
Note: T = -40 °C
Figure 11. Typical ICC1 vs. Frequency

D A T A S H E E T
TEST CONDITIONS
Table 24. Test Specifications
54D,
Test Condition 64C 65A Unit
Device
Under Output Load 1 TTL gate
Test
Output Load Capacitance, CL
CL 30 100 pF
(including jig capacitance)
Input Rise and Fall Times 5 ns
Input Pulse Levels 0.0 V – VIO V
Input timing measurement
VIO/2 V
reference levels
Note: Diodes are IN3064 or equivalent
Output timing measurement
VIO/2 V
Figure 12. Test Setup reference levels
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted Changing, State Unknown
Does Not Apply Center Line is High Impedance State (High Z)
KS000010-PAL
SWITCHING WAVEFORMS
VIO
Input VIO/2 V Measurement Level VIO/2 V Output
VSS
Figure 13. Input Waveforms and Measurement Levels

D A T A S H E E T
AC CHARACTERISTICS
VCC and VIO Power-up
Parameter Description Test Setup Speed Unit
tVCS VCC Setup Time Min 50 µs
tVIOS VIO Setup Time Min 50 µs
tRSTH RESET# Low Hold Time Min 50 µs
Figure 14. VCC and VIO Power-up Diagram
tVCS
VCC
tVIOS
VIOP
tRSTH
RESET#

D A T A S H E E T
AC CHARACTERISTICS
Asynchronous Read Operations
Parameter Speed Options
JEDEC Std. Description Test Setup 54D 64C 65A Unit
tAVAV tRC Read Cycle Time (Note 1) Max 54 64 67 ns
CE# = VIL
tAVQV tACC Address to Output Delay Max 54 64 67 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 58 69 71 ns
tGLQV tOE Output Enable to Output Delay Max 20 28 ns
Chip Enable to Output High Z
tEHQZ tDF Max 10 ns
(Note 1)
Min 2 ns
tGHQZ tDF Output Enable to Output High Z (Note 1)
Max 10 ns
Read Min 0 ns
Output Enable
tOEH Toggle and
Hold Time (Note 1) Min 10 ns
Data# Polling
Output Hold Time From Addresses, CE# or OE#,

tAXQX tOH Min 2 ns
Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 12 and Table 24 for test specifications

D A T A S H E E T
AC CHARACTERISTICS
Burst Mode Read
Parameter Speed Options
JEDEC Std. Description 54D 64C 65A Unit
Asynchronous Access Time
tIACC Max 54 64 67 ns
ADV# Valid Clock to Output Delay (See Note)
9 FBGA 10 FBGA
tBACC Burst Access Time Valid Clock to Output Delay Max 17 ns
9.5 PQFP 10 PQFP
tADVCS ADV# Setup Time to Rising (Falling) Edge of CLK Min 4 5 7 ns
tADVCH ADV# Hold Time Min 2 ns
tADVP ADV# Pulse Width Min 15 15 18 ns
tBDH Data Hold Time from Next Clock Cycle Max 4 ns
tDVCH Valid Data Hold from CLK Min 2 3 3 ns
9 FBGA 10 FBGA
tDIND CLK to Valid IND/WAIT# Max 17 ns
9.5 PQFP 10 PQFP
tINDH IND/WAIT# Hold from CLK Min 2 3 3 ns
tIACC CLK to Valid Data Out, Initial Burst Access Max 54 60 68 ns
Min 15 18 25
tCLK CLK Period ns
Max 60
tCR CLK Rise Time Max 3 ns
tCF CLK Fall Time Max 3 ns
tCH CLK High Time Min 2.5 2.5 3 ns
tCL CLK Low Time Min 2.5 2.5 3 ns
tDS Data Setup to WE# Rising Edge Min 15 15 16 ns
tDH Data Hold from WE# Rising Edge Min 2 ns
tAS Address Setup to Falling Edge of WE# Min 0 ns
tAH Address Hold from Falling Edge of WE# Min 25 30 33 ns
tCS CE# Setup Time Min 3 ns
tCH CE# Hold Time Min 3 ns
Address Setup Time to CLK
tACS Min 5 6 7 ns
(See Note)
Address Hold Time from ADV# Rising Edge
tACH Min 1 2 2 ns
(See Note)
tOE Output Enable to Output Valid Max 20 ns
Min 2 3 3
tDF tOEZ Output Enable to Output High Z ns
Max 10 15 17
tEHQZ tCEZ Chip Enable to Output High Z Max 10 15 17 ns
tCES CE# Setup Time to Clock Min 4 5 6 ns
Note: See Product Selector Guide for minimum initial clock delay prior to initial valid data. tIACC may also be calculated using the
following formula: tIACC = (clock delays) x (clock period) + tBACC.

D A T A S H E E T
AC CHARACTERISTICS
tRC
Addresses Addresses Stable

tACC
CE#
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
RY/BY#
0V
Figure 15. Conventional Read Operations Timings
tCES tCEZ
CE#
CLK
tADVCS
ADV#
tADVCH
tACS
A0: A18 Aa
tBDH tBACC
tACH
DQ0: DQ31
tIACC Da Da + 1 Da + 2 Da + 3 Da + 31
tOE tOEZ
OE#*
IND#
Figure 16. Burst Mode Read (x32 Mode)

D A T A S H E E T
AC CHARACTERISTICS
CLK
ADV#
CE#
tCS tCH
A18-A0 Stable Address

tWC
DQ31-DQ0 Valid Data
tAS tAH
tDS tDH
WE# tOEH
OE#
tWPH
IND/WAIT#
Figure 17. Asynchronous Command Write Timing

Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.
CE#
tCES
CLK
tADVCS
tADVP
ADV#
ttACS
AS tACH tACS tACH
A18-A0, Valid Address Valid Address
WORD# tWC tEHQZ
tADVCH
DQ31-DQ0 Data In Data Out
tDF
tWADVH tWCKS
tOE
OE# tDH
tDS
tWP
WE#
10 ns
IND/WAIT#
Figure 18. Synchronous Command Write/Read Timing

Note: All commands have the same number of cycles in both asynchronous and synchronous modes, including the
READ/RESET command. Only a single array access occurs after the F0h command is entered. All subsequent accesses are
burst mode when the burst mode option is enabled in the Configuration Register.

D A T A S H E E T
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC Std. Description Test Setup All Speed Options Unit
RESET# Pin Low (During Embedded
tREADY Max 11 µs
Algorithms) to Read or Write (See Note)
RESET# Pin Low (NOT During Embedded

tREADY Max 500 ns
Algorithms) to Read or Write (See Note)
tRP RESET# Pulse Width Min 500 ns
RESET# High Time Before Read (See

tRH Min 50 ns
Note)
tRPD RESET# Low to Standby Mode Min 20 µs
tRB RY/BY# Recovery Time Min 0 ns
RESET# Active for Bank NOT Executing

tREADY Max 500 ns
Embedded Algorithm
tRH RESET# High Time before Read Max 50 ns

RESET# Active for Bank Executing
tREADY Max 11 µs
Embedded Algorithm
RESET# Delay to Read Mode During
tDRNE Max 7 µs
Normal Erase
RESET# Delay to Read Mode if RESET# is
tRMX held active for maximum delay (see Max 50 ns
previous two parameters)
Note: Not 100% tested.

D A T A S H E E T
AC CHARACTERISTICS
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timing to Bank NOT Executing Embedded Algorithm
Reset Timing to Bank Executing Embedded Algorithm
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 19. RESET# Timings
DQ31-DQ0 Program/Erase Command
tDS tDH
WE# tWP
tWPWS
WP# Valid WP#
tCH tWPRH
RY/BY#
Figure 20. WP# Timing

D A T A S H E E T
AC CHARACTERISTICS
Erase/Program Operations
Parameter
JEDEC Std. Description All Speed Options Unit
tAVAV tWC Write Cycle Time (Note 1) Min 60 ns

tAVWL tAS Address Setup Time Min 0 ns
tWLAX tAH Address Hold Time Min 25 ns
tDVWH tDS Data Setup to WE# Rising Edge Min 15 ns
tWHDX tDH Data Hold from WE# Rising Edge Min 2 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)
tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns
CE# Setup to CLK Min 7
tWLWH tWP WE# Width Min 25 ns

tWHWL tWPH Write Pulse Width High Min 30 ns
tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec.
tVCS VCC Setup Time (Note 1) Min 50 µs
tRB Recovery Time from RY/BY# Min 0 ns
tBUSY RY/BY# Delay After WE# Rising Edge Max 90 ns
WP# Setup to WE# Rising Edge with

tWPWS Min 20 ns
Command
tWPRH WP# Hold after RY/BY# Rising Edge Max 2 ns
Notes:
1. Not 100% tested.
2. See the section for more information.

D A T A S H E E T
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
Data A0h PD Status DOUT
tBUSY tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 21. Program Operation Timings

D A T A S H E E T
AC CHARACTERISTICS
Erase Command Sequence (last two cycles) Read Status Data
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
10 for Chip Erase
tBUSY tRB
RY/BY#
tVCS
VCC
Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status).
Figure 22. Chip/Sector Erase Operation Timings
tWC tRC tWC tWC
Addresses Valid PA Valid RA Valid PA Valid PA

tAH
tACC tCPH
tCE
CE#
tCP
tOE
OE#
tOEH tGHWL
tWP tWPH
WE#
tDF
tWPH tDS
tDH tOH
Valid Valid Valid Valid
Data
In Out In In
tSR/W
WE# Controlled Write Cycle Read Cycle CE# Controlled Write Cycles
Figure 23. Back-to-back Cycle Timings

D A T A S H E E T
AC CHARACTERISTICS
tWC
tRC
Addresses VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 24. Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
tBUSY
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 25. Toggle Bit Timings (During Embedded Algorithms)

D A T A S H E E T
AC CHARACTERISTICS
Enter
Embedded Erase Enter Erase Erase
Erasing Suspend Suspend Program Resume
WE# Erase Erase Suspend Erase Erase Suspend Erase Erase
Read Suspend Read Complete
Program
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 26. DQ2 vs. DQ6 for Erase and Erase Suspend Operations
CE#
CLK
AVD#
Addresses VA VA
OE#
tOE tOE
Data Status Data Status Data
RDY
1. The timings are similar to synchronous read timings and asynchronous data polling Timings/Toggle bit Timing.
2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete,
the toggle bits will stop toggling.
3. RDY is active with data (A18 = 0 in the Configuration Register). When A18 = 1 in the Configuration Register, RDY is active one
clock cycle before data.
4. Data polling requires burst access time delay.
Figure 27. Synchronous Data Polling Timing/Toggle Bit Timings

D A T A S H E E T
VIH
RESET#
SA, A6,
Valid* Valid* Valid*
A1, A0
Sector Protect/Unprotect Verify
Data 60h 60h/68h** 40h/48h*** Status
Sector Protect: 150 µs

1 µs Sector Unprotect: 15 ms
CE#
WE#
OE#
* Valid address for sector protect: A6 = 0, A1 = 1, A0 = 0. Valid address for sector unprotect:A6 = 1, A1 = 1, A0 = 0.
** Command for sector protect is 68h. Command for sector unprotect is 60h.
*** Command for sector protect verify is 48h. Command for sector unprotect verify is 40h.
Figure 28. Sector Protect/Unprotect Timing Diagram

D A T A S H E E T
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
JEDEC Std. Description All Speed Options Unit
tAVAV tWC Write Cycle Time (Note 1) Min 65 ns
tAVEL tAS Address Setup Time Min 0 ns
tELAX tAH Address Hold Time Min 45 ns
tDVEH tDS Data Setup Time Min 35 ns
tEHDX tDH Data Hold Time Min 2 ns
tOES Output Enable Setup Time Min 0 ns
Read Recovery Time Before Write

tGHEL tGHEL Min 0 ns
(OE# High to WE# Low)
tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns
tWADVS WE# Rising Edge Setup to ADV# Falling Edge Min 5 ns
tWP WE# Width Min 15 ns
tWADVH WE# Falling Edge After ADV# Falling Edge Min 0 ns
tWCKS WE# Rising Edge Setup to CLK Rising Edge Min 5 ns
tELEH tCP CE# Pulse Width Min 35 ns
tEHEL tCPH CE# Pulse Width High Min 30 ns
tWHWsH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec.
Notes:
1. Not 100% tested.
2. See the section for more information.

D A T A S H E E T
AC CHARACTERISTICS
555 for program PA for program

2AA for erase SA for sector erase
555 for chip erase
Data# Polling
Addresses PA
tWC tAS
tAH
tWH tWPH
tWP
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tBUSY
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 29. Alternate CE# Controlled Write Operation Timings

D A T A S H E E T
ERASE AND PROGRAMMING PERFORMANCE

Parameter Typ (Note 1) Max (Note 2) Unit Comments
Sector Erase Time 1.0 5 s Excludes 00h programming
Chip Erase Time 23 230 s prior to erasure (Note 4)
Double Word Program Time 18 250 µs
Word (x16) Program Time 15 210 µs

Accelerated Double Word Program Time 8 130 µs Excludes system level
Accelerated Chip Program Time 5 50 s overhead (Note 5)
Chip Program Time x16 10 100

s
(Note 3) x32 12 120
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 2.5 V VCC, 1M cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 145°C, VCC = 2.5 V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See
Tables 19 and 20 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1M cycles.
7. PPBs have a minimum program/erase cycle endurance of 100 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, ACC, and WP#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
VCC Current –100 mA +100 mA
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PQFP AND FORTIFIED BGA PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Setup Typ Max Unit
CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF
CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years

D A T A S H E E T
PHYSICAL DIMENSIONS
PQR080–80-Lead Plastic Quad Flat Package

D A T A S H E E T
PHYSICAL DIMENSIONS
LAA 080–80-ball Fortified Ball Grid Array (13 x 11 mm)

D A T A S H E E T
REVISION SUMMARY
Revision B (September 30, 2002) number of delay cycles callouts. Moved start of Valid
Address cycle.
Initial public release.
Falling CLK Edge Output and Two-CLK Data Hold
Revision B+1 (October 7, 2002)
Deleted figure.
Distinctive Characteristics
See Table 9 , Configuration Register Definitions
Changed maximum power consumption on burst
mode read, program/erase operations, and standby Modified descriptions for CR3–CR10.
mode.
See Table 16 , CFI Device Geometry Definition
Burst Mode Read table Modified description of data at address 2Ch (x32
Changed tCES specification from 7, 8, and 9 ns to 4, 5, mode); added data 0003h.
and 6 ns, respectively.
DC Characteristics
DC Characteristics table Added maximum ICC6 specification.
Deleted I CC2 specification. Changed I CCB OE# test
AC Characteristics
condition from VIH to VIL. Added 1 MHz test condition
to ICC1 ; changed OE# test condition from VIH to V IL . Asynchronous Read Operations: Changed tCE specifi-
Changed ICC3 and I CC4 maximum values and added cations for 54D, 65D, 64C, and 65A speed options.
typical values. Changed maximum values for I CC5 , Changed tDF specifications for 65A and 90A speed op-
ICC7, and ICC8. Added Note 4 to table. tions.
AC Characteristics Revision B+4 (April 8, 2003)

Erase and Program Operations table: Replaced TBDs
for tAH and tWP with values.
Corrected typo in Single power supply operation.
Erase and Programming Performance table
Corrected typo in Performance characteristics.
Replaced TBDs and existing typical and maximum val-
ues with new values. Product Selector Guide
Revision B+2 (October 14, 2002) Updated Max Burst Access Delay for the 54D, 65D,
64C, and 80C speed options.
Distinctive Characteristics, DC Characteristics
Global
Changed VCC CMOS standby current to 30 mA max.
Removed references to interleaving operations
Absolute Maximum Ratings throughout datasheet.
Changed maximum rating for VCC to 3.0 V. Table 6. 16-Bit and 32-Bit Linear and Interleaved
Burst Data Order
Revision B+3 (November 22, 2002)
Removed 2nd row for “Four Interleaved Data Trans-
Product Selector Guide fers” and “Eight Interleaved Data Transfers”.
Added availability note. Changed minimum initial clock Continuous Burst Read Operations, Figure 3. and
delay and maximum CE# access time on 54D, 65D, Figure 4. Wait Function During Continuous Burst
64C, and 65A speeds. Changed maximum OE# ac- Reads at Wordline Boundary, Figure 5. and Figure
cess time on 65A and 90A speeds. 6. Odd/Even Starting address Continuous Burst
Ordering Information Mode Alignment
Added availability note. Removed from datasheet.
See Table 8 , Burst Initial Access Delay Table 9. Configuration Register Definitions
Deleted definitions and settings columns and added Added “Reserved” references to table.
initial burst access columns. Sector Protection
Figure 3, Initial Burst Delay Control Added Sector and Sector Group section.
Modified drawing: Deleted arrows connecting ad-
dress/data cycles. Deleted setting callouts. Changed

D A T A S H E E T
Sector Erase and Program Suspend Operation DQ7: Data# Polling, DQ6: Toggle Bit I and DQ2:
Mechanics Toggle Bit II
Added bulleted section. Added reference to Figure 27.
Absolute Maximum Ratings and Operating Ranges Absolute Maximum Ratings
Added VIO Added ACC reference.
Changed 1.65 V to –0.5 V CMOS Compatible
Changed 2.3 V to 2.5 V Corrected Max values for the ICC5, 7, and 8
CMOS Compatible Added Note #5.
Removed “VIO” from Max column of output high volt- Figure 27. Synchronous Data Polling
age row. Timings/Toggle Bit Timing
Figure 16. Burst Mode Read (x32 mode) Added Figure.
Corrected typos to subscripts. Simultaneous Read/Write Operations Overview
Corrected values for the tBACC and tDIND for the 54D, and Restrictions
65D, 64C, and 80C speed options. Added Sections and table.
Figure 17. Asynchronous Command Write Timing Table 7. Burst Initial Access Delay, Table 8.
Added tWC and tWPH. Configuration Register Definitions, Table 23. Test
Specifications, Asynchronous Read Operations,
Figure 18. Synchronous Command Write/ Read and Burst Mode Read
Timing Removed the 65D, 80C, and 90A speed options from
Added tWC and tWPH. tables.
Hardware Reset (RESET#) Revision C (May 19, 2003)

Corrected tREADY max. No revisions made, repost on web.
Figure 20. WP# Write Timing
Revision C+1 (May 29, 2003)
Added tWP.
Figure 23. Back-to-back Cycle Timings
Changed the standby mode to 60 µA.
Added tWPH.
Product Selector Guide
Figure 24. Data# Polling Timings (During
Embedded Algorithms) Changed the standard voltage range to 2.5-2.75 V
Added tWC. Output Disable Mode
Figure 29. Alternate CE# Controlled Write Replace paragraph.

Operation Timings Synchronous (Burst) Read Operation
Added tWP and tWPH Removed reference to “continuous sequential” from
Erase and Programming Performance section.
Changed the sector erase time typical to 1.0. Figure 3. Initial Burst Delay Control
Renumbered waveform to read two, three, four.
Revision B+5 (May 6, 2003)
Toggle Bit I
Global
Added sentence to second paragraph of section.
Converted data sheet from Advanced Information to
Preliminary. CMOS Compatible
Ordering Information Removed reference to continuous burst from table.
Removed some OPNs and markings. Burst Mode Read
Automatic Sleep Mode (ASM) and Standby Mode Changed the tIACC Max for the 65A speed option to 67
ns.
Reworded first paragraph.

D A T A S H E E T
Figure 15. Typical ICC1 vs. Frequency Changed 2.5 to 2.7 and made T= 40°C
Renumbered Supply Current axis, removed 2.3 V Burst Mode Read
graph, and changed other graph to 2. 5V.
Changed tBACC for 54D to 9 FBGA and 9.5 PQFP.
Figure 27. Synchronous Data Polling
Changed tDIND for 54D to 9 FBGA and 9.5 PQFP and
Timing/Toggle Bit Timings
for the 64C to 10 FBGA and 10 PQFP.
Deleted line under the pulse in OE#.
Figure 27. Synchronous Data Polling Timing/Tog-
Revision C+2 (June 26, 2003) gle Bit Timing
Added note 4.
Product Selector Guide
Added Note. Revision D (June 30, 2003)
Synchronous (Burst) Read Operation, ADV# Global
Control In Linear Mode, and IND/WAIT# Operation
Converted to a Preliminary Datasheet.
in Linear Mode
Removed feature. Revision D+1 (June 30, 2003)
Table. 7 Valid Configuration Register Bit Definition Global
for IND/WAIT#
Converted to a Datasheet.
Removed features.
Table 20. Sector Protection Command Definitions Distinctive Characteristics
(x32 mode) Added temperature range to simultaneous read/write
operations section.
Changed the address for OW A5-A0 to 011X10.
Table 22. Sector Protection Command Definitions CMOS Compatible
(x16 mode) Inserted IACC field to table.
Changed the PWA sector to A0:A-1
Figure 11. Typical ICC1 vs. Frequency
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

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Am29BDD160G

Continuity of Ordering Part Numbers

For More Information

■ Flexible sector architecture SOFTWARE FEATURES

■ Programmable Burst interface ■ Supports Common Flash Interface (CFI)

2 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 3

All PPB Erase Command ....................................................... 43 Key to Switching Waveforms . . . . . . . . . . . . . . . 56

4 Am29BDD160G October 21, 2003

PRODUCT SELECTOR GUIDE

Max Initial/Asynchronous Access Time, ns (tACC) 54 64 67

Max Clock Rate (MHz) 66 56 40

Erase Voltage VIO Input/Output

X-Decoder Cell Matrix

October 21, 2003 Am29BDD160G 5

Latches and Control Logic

6 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 7

Special Package Handling Instructions

8 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 9

BOOT CODE SECTOR ARCHITECTURE

Valid Combinations for Fortified BGA Packages

10 Am29BDD160G October 21, 2003

DEVICE BUS OPERATIONS

October 21, 2003 Am29BDD160G 11

Table 1. Device Bus Operation

Top Boot Block

Read L L H H X X AIN DOUT

Write L H L H X X AIN DIN

Burst Read Operations

Terminate Current Burst Read

Terminate Current Burst Read

12 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 13

14 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 15

Table 5. Am29BDD160 Autoselect Codes (High Voltage Method)

Read Cycle 1 L L H X X VID X L L X L L L H 007Eh

PPB Protection 0000h (unprotected)

A0-A18 Address 0 Address 1 Address 2 Address 3

16 Am29BDD160G October 21, 2003

Two Linear Data Transfers, 0-1 (A0 = 0)

0-1-2-3 (A0:A-1/A1-A0 = 00)

October 21, 2003 Am29BDD160G 17

0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F (A2:A-1/ A3-A0 = 0000)

0-1-2-3-4-5-6-7-8-9-A-B-C-D-E-F-G-H-I-J-K-L-M-N-O-P-Q-R-S-T-U-V (A3:A-1 = 00000)

CE# Control in Linear Mode RESET# Control in Linear Mode

18 Am29BDD160G October 21, 2003

October 21, 2003 Am29BDD160G 19

Table 7. Valid Configuration Register Bit Definition for IND/WAIT#

A0-A18 Address 1 Address 2

20 Am29BDD160G October 21, 2003

ADV# Address 1 Latched

A18-A0 Valid Address

Three CLK Delay

Five CLK Delay

Figure 3. Initial Burst Delay Control

October 21, 2003 Am29BDD160G 21