R13 SET - 1

Code No: RT32042

III B. Tech II Semester Regular Examinations, April - 2016

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Maximum Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answering the question in Part-Ais compulsory
3. Answer any THREE Questions from Part-B
*****

PART –A
1 a) Find the power of the given signal below? [4M]
3(—1)n, n≥0
x[n] = { 0 n<0

b) Compare overlap-add method and overlap-save method [4M]

c) Compare direct form I and direct form II realization of IIR systems. [4M]
d) What conditions are to be satisfied by the impulse response of an FIR system in
order to have a linear phase? [3M]
e) What is the need for multirate signal processing? [3M]
f) What are the differences between fixed type processors and floating type
processors? [4M]
PART –B
2 a) Find the solution to the following linear constant coefficient difference equation [10M]
3 1 1 n
y(n) — y ( n — 1) + y(n — 2) = ( for n ≥ 0
) 2 2
2
With initial conditions y(-1) = 4 and y(-2) = 10.
b) Derive the relationship between impulse response and frequency response of a [6M]
discrete time system.
3 a) Compute the DFT of the sequence x(n) = sin[nπ/4], where N=8 using DIT FFT [8M]
algorithm
b) Determine the IDFT of the sequence [8M]
X(K) = (6, —√2 — j4.8284, —2 + j2, √2 — j0.8284, —2, √2 + j0.8284, —2
— j2, —√2 — j4.8284
4 Obtain the cascade and parallel realisation structures for the following signals. [16M]

H(z) = 2(1 — z–1)(1 + √2z–1 + z–2)

(1 + 0.5z–1(1 — 0.9z–1 + 0.81z–2))

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 R13 SET - 1
Code No: RT32042

5 a) The desired frequency response of a low pass

—3π filter is 3π
jw e–j3w ≤w≤
Hd(e ) = { [10M]
4
4
0 elsewhere
Determine H(ejw) for M =7 using a rectangular window.

b) What are the effects of windowing? [6M]

6 a) Derive an expression for the spectrum of output signal of an decimator. [8M]

b) What are the applications of multirate system? [8M]

7 a) What is MAC? Explain its operation in detail. [10M]

b) What are the various addressing modes used in the TMS320C5X processor? [6M]

*****
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 R13 SET - 2
Code No: RT32042

III B. Tech II Semester Regular Examinations, April - 2016

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Maximum Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answering the question in Part-A is compulsory
3. Answer any THREE Questions from Part-B
*****
PART –A
1 a) Show that the following systems are nonlinear and time invariant.
[4M]
y(n) – x(n)y(n-1) = x(n)

b) Write computation efficiency of FFT over DFT. [3M]

c) What are the basic building blocks of realization structures? [4M]
d) Obtain the mapping formula for the impulse invariant transformation. [4M]
e) Write some examples of multirate digital systems. [3M]
f) What are the advantages of DSP processors in relation to general purpose
processors? [4M]
PART –B
2 a) Determine the frequency response, magnitude and phase responses and time [10M]
delay of the systems given by 1
( ) ( )
y n — y n — = x(n)
1 2
b) Explain causality and stability of a linear time invariant system. [6M]
3 a) Find the DFT of the following sequence using FFT DIF?
X(n) = {1,2,3,5,5,3,2,1} [8M]

b) Compute the DFTs of the sequence x(n) = 2-n, where N = 8 using DIT
algorithm [8M]
4 Develop the cascade and parallel forms of the following causal IIR transfer
functions. [16M]

H(z) (3 + 5z–1)(0.6 + 3z–1)

=
(1 — 2z–1 + 2z–2)(1 — z–1)
5 a) Convert the analog filter to a digital filter whose system function is [10M]
1
H(s) =
(s + 2)2 + (s + 1)
Use bilinear transformation.
b) What is a Kaiser window? In what way is it superior to other window functions? [6M]

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 R13 SET - 2
Code No: RT32042

6 a) Draw the block diagram of a multistage interpolator and explain it [8M]

b) A one stage decimator is characterized by the following Decimator factor = 3.
Anti-aliasing filter coefficients h(0) = -0.06 = h(4), h(1)=0.3 =h(3), h(2) =0.62. [8M]
Given the data, s(n) with successive values [6,-2,-3,8,6,4,-2], calculate and list
the filtered output and the output of the decimator
7 a) Draw and explain the memory architecture of the TMS320C3X processor. [10M]
b) What are the major advantages of having on-chip memory? [6M]

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 R13 SET - 3
Code No: RT32042

III B. Tech II Semester Regular Examinations, April - 2016

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Maximum Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answering the question in Part-Ais compulsory
3. Answer any THREE Questions from Part-B
*****

PART –A
1 a) Show that the following system is nonlinear and time invariant. [4M]
y(n+2) +2y(n) = x(n+1) +2
b) State all properties of DFT [4M]

c) Distinguish the canonic and non-canonic structures. [4M]

d) Discuss the stability of the impulse invariant mapping technique. [3M]

e) What is meant by aliasing? How to avoid it? [4M]

f) List the basic characteristics of digital signal processor. [3M]

PART –B
2 a) Determine the frequency response, magnitude and phase responses and time delay
[10M]
of the systems given by
y(n) = x(n) – x(n-1) + x(n - 2)
b) State and explain the transfer function of an LTI system. [6M]

3 a) Find the N-point DFT for x(n) = an for 0 < a < 1? [8M]

b) Given x(n) = {1,2,3,4,4,3,2,1}, find X(k) using DIF FFT algorithm. [8M]

4 Realize the following IIR system functions in the direct form I and II and also [16M]
parallel form.
1
H(z) =
(1 + az–1)(1 — bz–1)

5 a) Design a digital Butterworth filter that satisfies the following constraint using
bilinear transformation. Assume T=1sec. [10M]
π
0.9 ≤ |H(ejw)| ≤ 1 0≤w≤
2
3π
jw
|H(e )| ≤ 2 ≤w≤π
4

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 SET - 3
Code No: RT32042
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b) What is a Hamming window function? Obtain its frequency domain [6M]

characteristics.
6 a) Draw the block diagram of a multistage decimator and explain it [8M]

b) Discuss the computationally efficient implementation of decimator in an FIR

[8M]
filter.

7 a) Draw and explain the major block diagram of the TMS320C3X. [10M]

b) Explain the function of Barrel Shifter in the digital signal processor. [6M]

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 R13 SET - 4
Code No: RT32042

III B. Tech II Semester Regular Examinations, April - 2016

DIGITAL SIGNAL PROCESSING
(Electronics and Communication Engineering)
Time: 3 hours Maximum Marks: 70
Note: 1. Question Paper consists of two parts (Part-A and Part-B)
2. Answering the question in Part-Ais compulsory
3. Answer any THREE Questions from Part-B
*****

PART –A
1 a) What is BIBO stability? What are the conditions for BIBO system? [4M]
b) How FFT is more efficient to determine DFT of sequence? [3M]
c) Distinguish between the methods of realization namely, block diagram
representation and signal flow graph for implementing the digital filter transfer [4M]
function.
d) What is the impulse invariant technique? [4M]
e) What are the drawbacks in multistage implementation? [3M]
f) Mention various generations of digital signal processors. [4M]
PART –B
2 a) Determine frequency, magnitude and phase responses and time delay for the
[10M]
system.
1
y(n) + y(n — 1) = x(n) — x(n —
1) 4

b) Define the terms : linearity, time invariance and causality for a discrete time [6M]
system.

3 a) Compute the FFT for the sequence x(n) = n+1 where N =8 using DIT algorithm [8M]
b) State and prove the periodicity property in DFT. [8M]

4 Realize the following IIR system functions in the direct form I and II and also [16M]
parallel form.
1
H(z) = 1
(1 — az–1)2 + (1 — bz )
–1 2

5 a) What are the requirements for converting a stable analog filter into a stable digital
filter? [6M]

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 R13 SET - 4
Code No: RT32042

b) The desired frequency response of a low pass filter

—π is π [10M]
1; 2 ≤w≤2
Hd(ejw) = {
π
0; ≤w≤
π2
Determine hd(n) for M =7 using a rectangular window.

6 a) How can sampling rate be converted by a rational factor M/L? [8M]

b) Draw and explain the polyphase structure of a interpolator. [8M]
7 a) Explain the purpose of six registers used in the TMS320C2X processor. [10M]
b) What are the limitations of pipelining in Digital Signal Processor? [6M]
****

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