research-article

Cross-layer resilience challenges: metrics and optimization

Authors:

Subhasish Mitra,

Kevin Brelsford,

Pia N. SandaAuthors Info & Claims

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Pages 1029 - 1034

Published: 08 March 2010 Publication History

Abstract

With increasing sources of disturbances in the underlying hardware, a key challenge in design of robust systems is to meet user expectations at required cost. Cross-layer resilience techniques, implemented across multiple layers of the system stack and designed to work together, can help system designers build effective robust systems at the desired cost point. This paper brings to the forefront two major cross-layer resilience challenges:

1. Quantification and validation of the effectiveness of a cross-layer resilience approach to robust system design in overcoming hardware reliability challenges.

2. Global optimization of a robust system design using cross-layer resilience techniques.

References

[1]

{Agarwal 07} Agarwal, M., et al., "Circuit Failure Prediction and Its Application to Transistor Aging," Proc. IEEE VLSI Test Symp., pp. 277--286, 2007.

Digital Library

[2]

{Ando 03} Ando, H., et al., "A 1.3-GHz Fifth-Generation SPARC64 Microprocessor", IEEE Journal Solid-State Circuits, Vol. 38, Issue 11, pp. 1896--1905, Nov. 2003.

[3]

{Bowman 09} Bowman, K., et al., "Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance," IEEE Journal Solid-State Circuits, Vol. 44, Issue 1, pp. 49--63, Jan. 2009.

[4]

{Bernick 05} Bernick, D., et al., "Non-Stop Advanced Architecture," Proc. IEEE Intl. Conf. Dependable Systems and Networks, pp. 12--21, 2005.

Digital Library

[5]

{Borkar 05} Borkar, S. Y., "Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation," IEEE Micro, pp. 10--16, Nov.-Dec. 2005.

Digital Library

[6]

{Calin 96} Calin, T., M. Nicolaidis, and R. Velaco, "Upset Hardened Memory Design for Submicron CMOS Technology," IEEE Trans. Nucl. Sci., Vol. 43, No. 12, pp. 2874--2878, Dec. 1996.

[7]

{Carter 10} Carter, N. P., et al., "Design Techniques for Cross-Layer Resilience," Proc. Design Automation and Test in Europe, 2010.

Digital Library

[8]

{DeHon 10} DeHon, A., et al., " Vision for Cross-Layer Optimization to Address the Dual Challenges of Energy and Reliability," Proc. Design Automation and Test in Europe, 2010.

Digital Library

[9]

{Ernst 03} Ernst, D., et al., "Razor: A Low-Power Pipeline based on Circuit-level Timing Speculation," Proc. IEEE Intl. Symp. Microarchitecture, pp. 7--18, 2003.

Digital Library

[10]

{Franco 94} Franco, P., and E. J. McCluskey, "On-line Delay Testing of Digital Circuits," Proc. IEEE VLSI Test Symp., pp. 167--173, 1994.

[11]

{Goswami 97} Goswami, K. K., R. K. Iyer L. Young, "DEPEND: A Simulation-Based Environment for System Level Dependability Analysis," IEEE Trans. Computers, Vol. 46, pp. 60--74, Jan. 1997.

Digital Library

[12]

{Huang 84} Huang, K. H., and J. A. Abraham, "Algorithm Based Fault Tolerance for Matrix Operations," IEEE Trans. Computers, Vol. C-33, No. 6, pp. 518--528, June 1984.

Digital Library

[13]

{Inoue 08} Inoue, H., Y. Li and S. Mitra, "VAST: Virtualization-Assisted Concurrent Autonomous Self-Test," Proc. IEEE Intl. Test Conf., 2008.

[14]

{Kogge 08} Kogge, P., et al., "Exascale Computing Study: Technology Challenges in Achieving Exascale Systems," 2008.

[15]

{Lee 10} Lee, H., et al., "LEAP: Layout Design through Error-Aware Placement for Soft-Error Resilient Sequential Cell Design," Proc. IEEE Intl. Reliability Physics Symp., 2010.

[16]

{Leem 10} Leem, L., et al., "ERSA: Error Resilient System Architecture for Probabilistic Applications," Proc. Design Automation and Test in Europe, 2010.

Digital Library

[17]

{Li 08} Li, Y., S. Makar and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test using Stored Test Patterns," Proc. Design Automation and Test in Europe, pp. 885--890, 2008.

Digital Library

[18]

{Li 09a} Li, Y., et al., "Overcoming Early-Life Failure and Aging for Robust Systems," IEEE Design and Test of Computers, Nov.-Dec. 2009.

Digital Library

[19]

{Li 09b} Li, Y., O. Mutlu and S. Mitra, "Operating System Scheduling for Efficient Online Self-Test in Robust Systems," Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, 2009.

Digital Library

[20]

{Li 10} Li, Y., D. S. Gardner and S. Mitra, "Concurrent Autonomous Self-Test for Uncore Components in SoCs," Proc. IEEE VLSI Test Symp., 2010.

[21]

{McCluskey 90} McCluskey, E. J., "Design Techniques for Testable Embedded Error Checkers," IEEE Computer, Vol. 23, No. 7, pp. 84--88, July 1990.

Digital Library

[22]

{Meaney 05} Meaney, P., et al., "IBM Z990 Soft Error Detection and Recovery," IEEE Trans. Device and Materials Reliability, Vol. 5, Issue 3, pp. 419--427, Sept. 2005.

[23]

{Mintarno 10} Mintarno, E., "Optimized Self-Tuning for Circuit Aging," Proc. Design Automation and Test in Europe, 2010.

Digital Library

[24]

{Mitra 00} Mitra, S., and E. J. McCluskey, "Which Concurrent Error Detection Schemes to Choose?" Proc. IEEE Intl. Test Conf., pp. 985--994, 2000.

Digital Library

[25]

{Mitra 05} Mitra, S., et al., "Robust System Design with Built-In Soft Error Resilience," IEEE Computer, Vol. 38, pp. 43--52, Feb. 2005.

Digital Library

[26]

{Mitra 08} Mitra, S., "Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges," Proc. Design Automation and Test in Europe, 2008.

Digital Library

[27]

{Muller 10} Muller, K. P., and P. N. Sanda, "Soft Error Assessments for Servers," Proc. Intl. Reliability Physics Symp., 2010.

[28]

{Nassif 10} Nassif, S. R., et al., "A Resilience Roadmap," Proc. Design Automation and Test in Europe, 2010.

Digital Library

[29]

{Nepal 08} Nepal, K., et al., "Using Implications for Online Error Detection," Proc. IEEE Intl. Test Conf., 2008.

[30]

{Oh 02a} Oh, N., P. P. Shirvani and E. J. McCluskey, "Error Detection by Duplicated Instructions in Super-Scalar Processors," IEEE Trans. Reliability, Vol. 51, Issue 1, pp. 63--75, March 2002.

[31]

{Oh 02b} Oh, N., S. Mitra and E. J. McCluskey, "ED⁴I: Error Detection by Diverse Data and Duplicated Instructions" IEEE Trans. Computers, Vol. 51, No. 2, pp. 180--199, Feb. 2002.

Digital Library

[32]

{Pattabiraman 07} Pattabiraman, K., et. al., "Automated Derivation of Application-Aware Error Detectors using Static Analysis," Proc. IEEE Intl. Symp. On-line Testing, pp. 211--16, 2007.

Digital Library

[33]

{Sanda 08} Sanda, P. N., et al., "Soft Error Resilience of the IBM POWER6 Processor," IBM Journal Research and Development, Vol 52, Number 3, 2008.

Digital Library

[34]

{Spainhower 99} Spainhower, L., and T. A. Gregg, "S/390 Parallel Enterprise Server G5 Fault Tolerance," IBM Journal Res. and Dev., Vol. 43, pp. 863--873, Sept./Nov., 1999.

Digital Library

[35]

{Seshia 07} Seshia, S., W. Li and S. Mitra, "Verification Guided Soft Error Resilience," Proc. Design Automation and Test in Europe, pp. 1442--1447, 2007.

Digital Library

[36]

{Siewiorek 98} Siewiorek, D. P., and R. S Swarz, Reliable Computer Systems: Design and Evaluation, 1998.

Digital Library

[37]

{Singhee 07} Singhee, A., and R. A. Rutenbar, "Statistical Blockade: A Novel Method for Very Fast Monte Carlo Simulation of Rare Circuit Events, and its Application," Proc. Design Automation and Test in Europe, pp. 1379--1384, 2007.

Digital Library

[38]

{Zhang 06} Zhang, M., et al., "Sequential Element Design with Built-In Soft Error Resilience," IEEE Trans. VLSI, Vol. 14, Issue 12, pp. 1368--1378, Dec. 2006.

Digital Library

Cited By

Guo XStan M(2017)Implications of accelerated self-healing as a key design knob for cross-layer resilienceIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.00856:C(167-180)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.008
Dutt NJantsch ASarma S(2016)Toward Smart Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/287293615:2(1-27)Online publication date: 17-Feb-2016
https://dl.acm.org/doi/10.1145/2872936
Cho HCher CShepherd TMitra S(2015)Understanding soft errors in uncore componentsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744923(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744923
Show More Cited By

Recommendations

Cross-Layer Resilience: Challenges, Insights, and the Road Ahead
DAC '19: Proceedings of the 56th Annual Design Automation Conference 2019

Resilience to errors in the underlying hardware is a key design objective for a large class of computing systems, from embedded systems all the way to the cloud. Sources of hardware errors include radiation, circuit aging, variability induced by ...
Design techniques for cross-layer resilience
DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

Current electronic systems implement reliability using only a few layers of the system stack, which simplifies the design of other layers but is becoming increasingly expensive over time. In contrast, cross-layer resilient systems, which distribute the ...
Resilience Challenges for Exascale Systems
DFT '09: Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

The combination of decreasing device reliability due to deep submicron scaling, increasing integration, and the size of future exascale high-performance computers and cloud datacenters pose significant challenges for system resilience. Furthermore, with ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

DATE '10: Proceedings of the Conference on Design, Automation and Test in Europe

March 2010

1868 pages

ISBN:9783981080162

General Chairs:
Giovanni De Micheli
EPF Lausanne, CH
,
Bashir Al-Hashimi
University of Southampton, UK
,
Program Chairs:
Wolfgang Mueller
University of Paderborn, SE
,
Enrico Macii
Politecnico di Torino, IT

Sponsors

EDAA: European Design Automation Association
ECSI
EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
The IEEE Computer Society TTTC
The IEEE Computer Society DATC
The Russian Academy of Sciences: The Russian Academy of Sciences

Publisher

European Design and Automation Association

Leuven, Belgium

Publication History

Published: 08 March 2010

Check for updates

Qualifiers

Research-article

Conference

DATE '10

Sponsor:

EDAA
EDAC
SIGDA
The Russian Academy of Sciences

DATE '10: Design, Automation and Test in Europe

March 8 - 12, 2010

Germany, Dresden

Acceptance Rates

Overall Acceptance Rate 518 of 1,794 submissions, 29%

Upcoming Conference

DATE '25

Sponsor:
sigda

Design, Automation and Test in Europe

March 31 - April 2, 2025

Lyon , France

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

8
Total Citations
View Citations
125
Total Downloads

Downloads (Last 12 months)2
Downloads (Last 6 weeks)1

Reflects downloads up to 22 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Guo XStan M(2017)Implications of accelerated self-healing as a key design knob for cross-layer resilienceIntegration, the VLSI Journal10.1016/j.vlsi.2016.10.00856:C(167-180)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.10.008
Dutt NJantsch ASarma S(2016)Toward Smart Embedded SystemsACM Transactions on Embedded Computing Systems10.1145/287293615:2(1-27)Online publication date: 17-Feb-2016
https://dl.acm.org/doi/10.1145/2872936
Cho HCher CShepherd TMitra S(2015)Understanding soft errors in uncore componentsProceedings of the 52nd Annual Design Automation Conference10.1145/2744769.2744923(1-6)Online publication date: 7-Jun-2015
https://dl.acm.org/doi/10.1145/2744769.2744923
Schlichtmann UKleeberger VAbraham JEvans AGimmler-Dumont CGlaß MHerkersdorf ANassif SWehn NFettweis GNebel W(2014)Connecting different worldsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2616982(1-8)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2616982
Schmoll FHeinig AMarwedel PEngel M(2013)Improving the fault resilience of an H.264 decoder using static analysis methodsACM Transactions on Embedded Computing Systems10.1145/2536747.253675313:1s(1-27)Online publication date: 6-Dec-2013
https://dl.acm.org/doi/10.1145/2536747.2536753
Cho HMirkhani SCher CAbraham JMitra S(2013)Quantitative evaluation of soft error injection techniques for robust system designProceedings of the 50th Annual Design Automation Conference10.1145/2463209.2488859(1-10)Online publication date: 29-May-2013
https://dl.acm.org/doi/10.1145/2463209.2488859
Henkel JBauer LBecker JBringmann OBrinkschulte UChakraborty SEngel MErnst RHärtig HHedrich LHerkersdorf AKapitza RLohmann DMarwedel PPlatzner MRosenstiel WSchlichtmann USpinczyk OTahoori MTeich JWehn NWunderlich HDick RMadsen J(2011)Design and architectures for dependable embedded systemsProceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis10.1145/2039370.2039384(69-78)Online publication date: 9-Oct-2011
https://dl.acm.org/doi/10.1145/2039370.2039384
Leem LCho HLee HKim YLi YMitra SScheffer LPhillips JHu A(2010)Cross-layer error resilience for robust systemsProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133465(177-180)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133465

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents