Just Accepted
Dynamic Per-Flow Queues in Shared Buffer TSN Switches
Authors: 
Wenxue Wu, Tong Zhang, Zhen Li, Xiaoqin Feng, Liwei Zhang, Fengyuan RenAuthors Info & Claims
Wenxue Wu, Tong Zhang, Zhen Li, Xiaoqin Feng, Liwei Zhang, Fengyuan RenAuthors Info & ClaimsAccepted on 11 February 2025
Abstract
Time-Sensitive Networking (TSN), as an enhancement based on Ethernet, can ensure deterministic traffic transmission with low delays and minimal jitters. However, TSN switches have only eight priority queues inherited from Ethernet at each egress port, which limits the flexibility and efficiency of traffic scheduling, as well as the support for developing traffic management mechanisms. Although per-flow queues boost scheduling and Quality of Service (QoS), static per-flow hardware queues in switches are considered unpratical due to resource limits. In this paper, we leverage the limitation of buffer size on the number of concurrent flows in shared buffer TSN switches to design Dynamic Per-Flow Queues (DFQ). DFQ only maintains a fixed number of virtual queues determined by the buffer size and dynamically manages the mapping between virtual queues and active flows to provide the capability of per-flow queueing. By constructing Flow Mapping Table (FMT) with content-addressable memory (or hash bucket), DFQ can quickly match, create, and recycle queues to multiplex limited switch resource. We prototype DFQ on an FPGA switch and evaluate its performance in different scenarios. Experimental results show that DFQ can decrease the overhead of per-flow isolation with minimal impact on delay and throughput, indicating that DFQ is an effective per-flow queues solution.
References
[1]
2020. IEEE Standard for Local and Metropolitan Area Networks–Bridges and Bridged Networks - Amendment 34: Asynchronous Traffic Shaping. IEEE Std 802.1Qcr-2020 (Amendment to IEEE Std 802.1Q-2018 as amended by IEEE Std 802.1Qcp-2018, IEEE Std 802.1Qcc-2018, IEEE Std 802.1Qcy-2019, and IEEE Std 802.1Qcx-2020) (2020), 1–151.
[2]
Rudy Belliardi, J Dorr, T Enzinger, F Essler, J Farkas, M Hantel, M Riegel, MP Stanica, G Steindl, R Wamßer, et al. 2018. Use Cases IEC/IEEE 60802 v1.3.
[3]
Broadcom. [n. d.]. Broadcom 53154 TSN Chip. Retrieved August 29, 2024 from https://www.broadcom.com/products/ethernet-connectivity/switching/roboswitch/bcm53154
[4]
Broadcom. [n. d.]. Trident3-X5/BCM56770 Series. Retrieved August 29, 2024 from https://www.broadcom.com/products/ethernet-connectivity/switching/strataxgs/bcm56770-series
[5]
H. Cheng, Y. Jin, Y. Gao, Y. Yu, W. Hu, and N. Ansari. 2008. Per-Flow Re-Sequencing in Load-Balanced Switches by Using Dynamic Mailbox Sharing. In 2008 IEEE International Conference on Communications. 5680–5684.
[6]
Abhijit K Choudhury and Ellen L Hahne. 1998. Dynamic queue length thresholds for shared-memory packet switches. IEEE/ACM Transactions On Networking 6, 2 (1998), 130–140.
[7]
Shang-Tse Chuang, A. Goel, N. McKeown, and B. Prabhakar. 1999. Matching output queueing with a combined input output queued switch. In Proc. IEEE Conference on Computer Communications (INFOCOM’99). 1169–1178.
[8]
Silviu S. Craciunas, Ramon Serna Oliver, Martin Chmelík, and Wilfried Steiner. 2016. Scheduling Real-Time Communication in IEEE 802.1Qbv Time Sensitive Networks. In Proceedings of the 24th International Conference on Real-Time Networks and Systems (Brest, France) (RTNS ’16). Association for Computing Machinery, New York, NY, USA, 183–192.
[9]
Zefu Dai and Jianwen Zhu. 2012. Saturating the transceiver bandwidth: Switch fabric design on FPGAs. In Proc. ACM/SIGDA international symposium on Field Programmable Gate Arrays (FPGA’12). 67–76.
[10]
Krystian Erwinski, Marcin Paprocki, Lech M. Grzesiak, Kazimierz Karwowski, and Andrzej Wawrzak. 2013. Application of Ethernet Powerlink for Communication in a Linux RTAI Open CNC system. IEEE Transactions on Industrial Electronics 60, 2 (2013), 628–636.
[11]
Ronald Fagin, Jurg Nievergelt, Nicholas Pippenger, and H. Raymond Strong. 1979. Extendible hashing—a fast access method for dynamic files. ACM Trans. Database Syst. 4, 3 (Sept. 1979), 315–344.
[12]
David Gerónimo Gómez, Antonio M. López, Angel Domingo Sappa, and Thorsten Graf. 2010. Survey of Pedestrian Detection for Advanced Driver Assistance Systems. IEEE Transactions on Pattern Analysis and Machine Intelligence 32 (2010), 1239–1258.
[13]
J. Gomez-Cornejo, A. Zuloaga, I. Villalta, J. Del Ser, U. Kretzschmar, and J. Lazaro. 2017. A novel BRAM content accessing and processing method based on FPGA configuration bitstream. Microprocessors and Microsystems 49 (2017), 64–76.
[14]
Florian Heilmann and Gerhard Fohler. 2019. Size-based queuing: an approach to improve bandwidth utilization in TSN networks. ACM SIGBED Rev. 16(2019), 9–14.
[15]
C. Hu, Y. Tang, X. Chen, and B. Liu. 2007. Per-Flow Queueing by Dynamic Queue Sharing. In IEEE INFOCOM 2007 - 26th IEEE International Conference on Computer Communications. 1613–1621.
[16]
Intel. [n. d.]. Intel® Ethernet Server Adapter I210-T1. Retrieved December 9, 2024 from https://www.intel.com/content/www/us/en/products/sku/68668/intel-ethernet-server-adapter-i210t1/specifications.html
[17]
Haokai Jing and Tong Zhang. 2023. Improving Traffic Scheduling Based on Per-flow Virtual Queues in Time-Sensitive Networking. In Proc. IEEE Symposium on Computers and Communications (ISCC’23). 1185–1188.
[18]
Farouk Kamoun and Leonard Kleinrock. 1980. Analysis of shared finite storage in a computer network node environment under general traffic conditions. IEEE Transactions on communications 28, 7 (1980), 992–1003.
[19]
Daehyeok Kim, Yibo Zhu, Changhoon Kim, Jeongkeun Lee, and Srinivasan Seshan. 2018. Generic External Memory for Switch Data Planes. In Proc. ACM Workshop on Hot Topics in Networks (HotNets’18). Association for Computing Machinery, 1–7.
[20]
Abdesselem Kortebi, Luca Muscariello, Sara Oueslati, and James Roberts. 2005. Evaluating the number of active flows in a scheduler realizing fair statistical bandwidth sharing. ACM SIGMETRICS Performance Evaluation Review 33, 1 (2005), 217–228.
[21]
Kyland. [n. d.]. SICOM3000TSN. Retrieved August 29, 2024 from https://www.kyland.com.cn/products/SICOM3000TSN.html
[22]
Jesse Levinson, Jake Askeland, Jan Becker, Jennifer Dolson, David Held, Soeren Kammel, J. Zico Kolter, Dirk Langer, Oliver Pink, Vaughan Pratt, Michael Sokolsky, Ganymed Stanek, David Stavens, Alex Teichman, Moritz Werling, and Sebastian Thrun. 2011. Towards fully autonomous driving: systems and algorithms. In Proc. IEEE Intelligent Vehicles Symposium (IV). 163–168.
[23]
Zonghui Li, Hai Wan, Yangdong Deng, Xibin Zhao, Yue Gao, Xiaoyu Song, and Ming Gu. 2020. Time-Triggered Switch-Memory-Switch Architecture for Time-Sensitive Networking Switches. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, 1(2020), 185–198.
[24]
Lucia Lo Bello, Mohammad Ashjaei, Gaetano Patti, and Moris Behnam. 2020. Schedulability analysis of Time-Sensitive Networks with scheduled traffic and preemption support. J. Parallel and Distrib. Comput. 144 (2020), 153–171.
[25]
Lucia Lo Bello, Enrico Bini, and Gaetano Patti. 2015. Priority-Driven Swapping-Based Scheduling of Aperiodic Real-Time Messages Over EtherCAT Networks. IEEE Transactions on Industrial Informatics 11, 3 (2015), 741–751.
[26]
Ahmed Nasrallah, Akhilesh S. Thyagaturu, Ziyad Alharbi, Cuixiang Wang, Xing Shao, Martin Reisslein, and Hesham ElBakoury. 2019. Ultra-Low Latency (ULL) Networks: The IEEE TSN and IETF DetNet Standards and Related 5G ULL Research. IEEE Communications Surveys & Tutorials 21, 1 (2019), 88–145.
[27]
Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, and Cong-Kha Pham. 2019. An Efficient I/O Architecture for RAM-Based Content-Addressable Memory on FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs 66, 3(2019), 472–476.
[28]
Aggelos Nikologiannis and Manolis Katevenis. 2001. Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques. In Proc. IEEE International Conference on Communications (ICC’01), Vol. 7. 2048–2052.
[29]
Aristides Nikologiannis, Ioannis Papaefstathiou, Georgios Kornaros, and Christoforos Kachris. 2004. An FPGA-based queue management system for high speed networking devices. Microprocess and Microsystems 28 (2004), 223–236.
[30]
Planet. [n. d.]. TSN-5225-4T. Retrieved August 29, 2024 from https://planet.com.br/produtos/tsn-5225-4t
[31]
B. Prabhakar and N. McKeown. 1998. On the speedup required for combined input and output queued switching. In Proc. IEEE International Symposium on Information Theory (ISIT’98.). 1909–1920.
[32]
Anastasios Psarras, Michalis Paschou, Chrysostomos Nicopoulos, and Giorgos Dimitrakopoulos. 2017. A dual-clock multiple-queue shared buffer. IEEE Trans. Comput. 66, 10 (2017), 1809–1815.
[33]
Delphine Reinhardt, Parag S. Mogre, and Matthias Hollick. 2010. Survey on Wireless Sensor Network Technologies for Industrial Automation: The Security and Quality of Service Perspectives. Future Internet 2(2010), 96–125.
[34]
Renesas. [n. d.]. Dual-Port SRAM. Retrieved August 29, 2024 from https://www.renesas.com/us/en/document/apn/254-most-commonly-asked-questions-about-sync-dual-ports
[35]
Rich Seifert and J.H. Edwards. 2008. The All-New Switch Book: The Complete Guide to LAN Switching Technology. Wiley.
[36]
Guilherme Serpa Sestito, Afonso Celso Turcato, Andre Luis Dias, Murilo Silveira Rocha, Maira Martins da Silva, Paolo Ferrari, and Dennis Brandao. 2018. A Method for Anomalies Detection in Real-Time Ethernet Data Traffic Applied to PROFINET. IEEE Transactions on Industrial Informatics 14, 5 (2018), 2171–2180.
[37]
Danfeng Shan, Wanchun Jiang, and Fengyuan Ren. 2017. Analyzing and Enhancing Dynamic Threshold Policy of Data Center Switches. IEEE Transactions on Parallel and Distributed Systems 28, 9 (2017), 2454–2470.
[38]
B. Suter, T.V. Lakshman, D. Stiliadis, and A.K. Choudhury. 1999. Buffer management schemes for supporting TCP in gigabit routers with per-flow queueing. IEEE Journal on Selected Areas in Communications 17, 6(1999), 1159–1169.
[39]
Curtis Villamizar and Cheng Song. 1994. High performance TCP in ANSNET. ACM SIGCOMM Computer Communication Review(Oct 1994), 45–60.
[40]
Alfredo Viola. 2010. Distributional analysis of the parking problem and Robin Hood linear probing hashing with buckets. Discrete Mathematics & Theoretical Computer Science 12 (2010).
[41]
Jean Walrand. 2023. A Concise Tutorial on Traffic Shaping and Scheduling in Time-Sensitive Networks. IEEE Communications Surveys & Tutorials 25, 3 (2023), 1941–1953.
[42]
Hao Wang and Bill Lin. 2011. Per-flow Queue Scheduling with Pipelined Counting Priority Index. In Proc. IEEE Symposium on High Performance Interconnects (HOTI’11). 19–26.
[43]
Jianhua Wei, Lei Zhu, Weichuan Zhang, Zhi Feng, and Peng Guo. 2014. Dynamic Per-flow Queuing to Reduce Competitions Among Large Number of Flows. Chinese Journal of Electronics 23, 4 (2014), 783–789.
[44]
Xilinx. [n. d.]. SoCs with Hardware and Software Programmability. Retrieved August 29, 2024 from https://www.amd.com/en/products/adaptive-socs-and-fpgas/soc/zynq-7000.html
[45]
Junli Xue, Guochu Shou, Yaqiong Liu, Yihong Hu, and Zhigang Guo. 2021. Time-aware traffic scheduling with virtual queues in time-sensitive networking. In 2021 IFIP/IEEE International Symposium on Integrated Network Management (IM). IEEE, 604–607.
[46]
Jinli Yan, Wei Quan, Xiangrui Yang, Wenwen Fu, Yue Jiang, Hui Yang, and Zhigang Sun. 2020. TSN-Builder: enabling Rapid Customization of Resource-Efficient Switches for Time-Sensitive Networking. In Proc. ACM/IEEE Design Automation Conference (DAC’20). 1–6.
[47]
Qiwen Yun, Qimin Xu, Yanzhou Zhang, Yingxiu Chen, Yafei Sun, and Cailian Chen. 2021. Flexible Switching Architecture with Virtual-Queue for Time-Sensitive Networking Switches. In Proc. Annual Conference of the IEEE Industrial Electronics Society (IECON 2021). 1–6.
[48]
Zifan Zhou, Ying Yan, Michael Berger, and Sarah Ruepp. 2018. Analysis and modeling of asynchronous traffic shaping in time sensitive networks. In Proc. IEEE International Workshop on Factory Communication Systems (WFCS’18). 1–4.
Index Terms
- Dynamic Per-Flow Queues in Shared Buffer TSN Switches
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EISSN:1557-7309
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Publication History
Online AM: 19 February 2025
Accepted: 11 February 2025
Revised: 22 December 2024
Received: 08 September 2024
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