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A multiple bit upset tolerant SRAM memory

Authors:

Gustavo Neuberger,

Fernanda de Lima,

Luigi Carro,

Ricardo ReisAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 8, Issue 4

Pages 577 - 590

https://doi.org/10.1145/944027.944038

Published: 01 October 2003 Publication History

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Abstract

SRAMs are used nowadays in almost every electronic product. However, as technology shrinks transistor sizes, single and multiple bit upsets only observable in space applications previously are now reported at ground level. This article presents a high level technique to protect SRAM memories against multiple upsets based on correcting codes. The proposed technique combines Reed Solomon code and Hamming code to assure reliability in presence of multiple bit flips with reduced area and performance penalties. Multiple upsets were randomly injected in various combinations of memory cells to evaluate the robustness of the method. The experiment was emulated in a Virtex FPGA platform. Results show that 100% of the injected double faults and a large amount of multiple faults were corrected by the method.

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Aziz AGolap MPorosh MTousif MSadi M(2025)Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parityIntegration10.1016/j.vlsi.2024.102297100(102297)Online publication date: Jan-2025
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Sajjad WShafique AMahmood R(2024)Designing of Reliable, Low-Power, and Performance-Efficient Onboard Computer Architecture for CubeSatsIEEE Journal on Miniaturization for Air and Space Systems10.1109/JMASS.2023.33422085:2(59-72)Online publication date: Jun-2024
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Thunig RBorchert CKober USchirmeier H(2024)Hybrid Hardware/Software Detection of Multi-Bit Upsets in Memory2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)10.1109/DSN-W60302.2024.00029(94-97)Online publication date: 24-Jun-2024
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Index Terms

A multiple bit upset tolerant SRAM memory
1. Hardware
  1. Hardware test
    1. Memory test and repair
  2. Robustness
    1. Hardware reliability
2. Software and its engineering
  1. Software creation and management
    1. Software development techniques
      1. Error handling and recovery

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 8, Issue 4

October 2003

194 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/944027

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

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Published: 01 October 2003

Published in TODAES Volume 8, Issue 4

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Aziz AGolap MPorosh MTousif MSadi M(2025)Multi-bit error detection and correction technique using HVDK (Horizontal-Vertical-Diagonal-Knight) parityIntegration10.1016/j.vlsi.2024.102297100(102297)Online publication date: Jan-2025
https://doi.org/10.1016/j.vlsi.2024.102297
Sajjad WShafique AMahmood R(2024)Designing of Reliable, Low-Power, and Performance-Efficient Onboard Computer Architecture for CubeSatsIEEE Journal on Miniaturization for Air and Space Systems10.1109/JMASS.2023.33422085:2(59-72)Online publication date: Jun-2024
https://doi.org/10.1109/JMASS.2023.3342208
Thunig RBorchert CKober USchirmeier H(2024)Hybrid Hardware/Software Detection of Multi-Bit Upsets in Memory2024 54th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)10.1109/DSN-W60302.2024.00029(94-97)Online publication date: 24-Jun-2024
https://doi.org/10.1109/DSN-W60302.2024.00029
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Efficient error detection codes for multiple-bit upset correction in SRAMs with BICS

Fault Injection and Dependability Evaluation of Fault-Tolerant Systems

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