article

Optimal simultaneous module and multivoltage assignment for low power

Authors:

Junjuan XuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 2

Pages 362 - 386

https://doi.org/10.1145/1142155.1142161

Published: 01 April 2006 Publication History

Abstract

Reducing power consumption through high-level synthesis has attracted a growing interest from researchers due to its large potential for power reduction. In this work we study functional unit binding (or module assignment) given a scheduled data flow graph under a multi-Vdd framework. We assume that each functional unit can be driven by different Vdd levels dynamically during run time to save dynamic power. We develop a polynomial-time optimal algorithm for assigning low Vdds to as many operations as possible under the resource and latency constraints, and in the same time minimizing total switching activity through functional unit binding. Our algorithm shows consistent improvement over a design flow that separates voltage assignment from functional unit binding. We also change the initial scheduling to examine power/energy-latency tradeoff scenarios under different voltage level combinations. Experimental results show that we can achieve 28.1% and 33.4% power reductions when the latency bound is the tightest with two and three-Vdd levels respectively compared with the single-Vdd case. When latency is relaxed, multi-Vdd offers larger power reductions (up to 46.7%). We also show comparison data of energy consumption under the same experimental settings.

References

[1]

Anderson J. and Najm, F. 2004. Low-power programmable routing circuitry for FPGAs. In Proceedings of the IEEE International Conference on Computer-Aided Design (San Jose, CA). IEEE Computer Society Press, Los Alamitos, CA, 602--609.

Digital Library

[2]

Bogliolo, A., Benini, L., Riccó, B., and De Micheli, G. 1999. Efficient switching activity computation during high-level synthesis of control-dominated designs. In Proceedings of the International Symposium on Low Power Electronics and Design (San Diego, CA). 127--132.

Digital Library

[3]

Chang, J. and Pedram, M. 1995. Register allocation and binding for low power. In Proceedings of the Design Automation Conference (San Francisco, CA). 29--35.

Digital Library

[4]

Chang, J. and Pedram, M. 1996. Module assignment for low power. In Proceedings of the EURO-Design Automation Conference (Geneva, Switzerland). 376--381.

Digital Library

[5]

Chang, J. and Pedram, M. 1997. Energy minimization using multiple supply voltages, IEEE Trans. VLSI Syst. 5, 4, 436--443.

Digital Library

[6]

Chen, D. and Cong, J. 2004a. Register binding and port assignment for multiplexer optimization. In Proceedings of the Asian Pacific Design Automation Conference (Yokohama, Japan). 68--73.

Digital Library

[7]

Chen, D. and Cong, J. 2004b. Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. In Proceedings of the International Symposium on Low Power Electronics and Design (Newport Beach, CA). 70--73.

Digital Library

[8]

Chen, D., Cong, J., and Fan, Y. 2003. Low-power high-level synthesis for FPGA architectures. In Proceedings of the International Symposium on Low Power Electronics and Design (Seoul, Korea). 134--139.

Digital Library

[9]

Chen, D., Cong, J., Li, F., and He, L. 2004. Low-power technology mapping for FPGA architectures with dual supply voltages. In Proceedings of the International Symposium on Field Programmable Gate Arrays (Monterey, CA). 109--117.

Digital Library

[10]

Cong J. and Liu, C. 1991. On the k-layer planar subset and topological via minimization problems. Trans. CAD 10, 459--463.

[11]

De Micheli, G. 1994. Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York.

Digital Library

[12]

Dilworth, R. 1950. A decomposition theorem for partially ordered set. Ann. Math 51, 161--166.

[13]

Duarte, D., Tsai, Y., Vijaykrishnan, N., and Irwin, M. 2002. Evaluating run-time techniques for leakage power reduction. In Proceedings of International Conference on VLSI Design. 31--38.

Digital Library

[14]

Gelsinger, P. 2004. Giga-scale integration for tera-ops performance: Opportunities and new frontiers. 41st DAC Tuesday Keynote.

[15]

Gonzalez, R., Gordon, B., and Horowitz, M. 1997. Supply and threshold voltage scaling for low power CMOS. IEEE J. Solid-State Circ. 32, 8, 1210--1216.

[16]

Hamada, M., Takahashi, M., Arakida, H., Chiba, A., Terazawa, T., Ishikawa, T., Kanazawa, M., Igarashi, M., Usami, K., and Kuroda, T. 1998. A top-down low power design technique using clustered voltage scaling with variable supply-voltage scheme. In Proceedings of the Custom Integrated Circuits Conference. 495--498.

[17]

ITRS, International Technology Roadmap for Semiconductors. 2003. Semiconductor Industry Association.

[18]

Johnson, M. and Roy, K. 1997. Datapath scheduling with multiple supply voltages and level converters. Trans. Des. Automat. Elect Syst. 2, 3, 227--248.

Digital Library

[19]

Kao, J., Narendra, S., and Chandrakasan, A. 2002. Subthreshold leakage modeling and reduction techniques. In Proceedings of the International Conference on Computer-Aided Design (San Jose, CA). 141--148.

Digital Library

[20]

Li, F., Chen, D., He, L., and Cong, J. 2003. Architecture evaluation for power-efficient FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays (Monterey, CA). 175--184.

Digital Library

[21]

Li, F., Lin, Y., and He, L. 2004. FPGA power reduction using configurable dual-Vdd. In Proceedings of the Design Automation Conference (San Diego, CA). 735--740.

Digital Library

[22]

Li, F. and He, L. 2001. Maximum current estimation with consideration of power gating. In Proceedings of the International Symposium on Physical Design (Sonoma, CA). 106--111.

Digital Library

[23]

Lin, Y. R., Hwang, C. T., and Wu, A. 1997. Scheduling techniques for variable voltage low power design. Trans. Des. Automat. Electron. Syst. 2, 2, 81--97.

Digital Library

[24]

Lyuh, C. G. and Kim, T. 2003. High-level synthesis for low-power based on network flow method. Trans. VLSI Syst. 11, 3, 364--375.

Digital Library

[25]

Manzak, A. and Chakrabarti, C. 2002. A low power scheduling scheme with resources operating at multiple voltages. Trans. VLSI Syst. 10, 1, 6--14.

Digital Library

[26]

Mutoh, S., Douseki, T., Matsuya, Y., Aoki, T., Shigematsu, A., and Yamada, J. 1995. 1-V power supply high-speed digital circuit technology with multithresholdvoltage CMOS. J. Solid-State Circ. 30, 8, 847--854.

[27]

Raje, S. and Sarrafzadeh, M. 1995. Variable voltage scheduling. In Proceedings of the International Symposium on Low Power Design (Dana Point, CA). 9--14.

Digital Library

[28]

Sarrafzadeh, M. and Lou, R. D. 1993. Maximum k-covering of weighted transitive graphs with applications. Algorithmica 9, 1, 84--100.

[29]

Srivastava, M. B. and Potkonjak, M. 1995. Optimum and heuristic transformation techniques for simultaneous optimization of latency and throughput. Trans. VLSI Syst. 3, 1, 2--19.

Digital Library

[30]

Takahashi, M. Hamada, M., Nishikawa, T., Arakida, H., Fujita, T., Hatori, F., Mita, S., Suzuki, K., Chiba, A., Terazawa, T., Sano, F., Watanbe, Y., Usami, K., Igarashi, M., Ishikawa, T., Kanazawa, M., Kuroda, T., and Furuyama, T. 1998. A 60mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme. J. Solid-State Circ. 33, 11, 1772--1780.

[31]

Usami, K. and Horowitz, M. 1995. Clustered voltage scaling for low-power design. In Proceedings of the International Symposium on Low Power Design (Dana Point, CA). 3--8.

Digital Library

[32]

Usami, K., Igarashi, M., Minami, F., Ishikawa, T., Kanazawa, M., Ichida, M., and Nogami, K. 1998. Automated low-power technique exploiting multiple supply voltages applied to a media processor. J. Solid-State Circ. 33, 3, 463--472.

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Optimal simultaneous module and multivoltage assignment for low power

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 2

April 2006

283 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1142155

Issue’s Table of Contents

Copyright © 2006 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 April 2006

Published in TODAES Volume 11, Issue 2

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Cited By

Ren WKozlowski WKoteshwara SYe MFranke HChen D(2023)AccShield: a New Trusted Execution Environment with Machine-Learning Accelerators2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247768(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247768
Zhang XChen YHao CHuang SLi YChen D(2023)Compilation and Optimizations for Efficient Machine Learning on Embedded SystemsEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_3(37-74)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_3
Zheng JLiu YLiu XLiang LChen DCheng K(2022)ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor with Compiler-Architecture Co-DesignIEEE Transactions on Computers10.1109/TC.2022.3213177(1-14)Online publication date: 2022
https://doi.org/10.1109/TC.2022.3213177
ABE SSHI YUSAMI KYANAGISAWA MTOGAWA N(2013)Floorplan Driven Architecture and High-Level Synthesis Algorithm for Dynamic Multiple Supply VoltagesIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E96.A.2597E96.A:12(2597-2611)Online publication date: 2013
https://doi.org/10.1587/transfun.E96.A.2597
Abe SYouhua Shi Usami KYanagisawa MTogawa N(2013)An energy-efficient high-level synthesis algorithm incorporating interconnection delays and dynamic multiple supply voltages2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)10.1109/VLDI-DAT.2013.6533808(1-4)Online publication date: Apr-2013
https://doi.org/10.1109/VLDI-DAT.2013.6533808
Rocha JDias OGomes L(2013)Exploiting dataflows and Petri nets mappings2013 11th IEEE International Conference on Industrial Informatics (INDIN)10.1109/INDIN.2013.6622950(590-595)Online publication date: Jul-2013
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Mukherjee RGhosh PDasgupta PPal A(2013)Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS ArchitectureAdvances in Computing and Information Technology10.1007/978-3-642-31600-5_62(633-648)Online publication date: 2013
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Mukherjee RGhosh PKumar NDasgupta PPal A(2012)Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework2012 International Symposium on Electronic System Design (ISED)10.1109/ISED.2012.51(267-271)Online publication date: Dec-2012
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Hara-Azumi YMatsuba TTomiyama HHonda STakada H(2012)Selective Resource Sharing with RT-Level Retiming for Clock Enhancement in High-Level SynthesisProceedings of the 2012 IEEE 14th International Conference on High Performance Computing and Communication & 2012 IEEE 9th International Conference on Embedded Software and Systems10.1109/HPCC.2012.224(1534-1540)Online publication date: 25-Jun-2012
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