article

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks

Authors:

Sanjukta Bhanja,

Karthikeyan Lingasubramanian,

N. RanganathanAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11, Issue 3

Pages 773 - 796

https://doi.org/10.1145/1142980.1142990

Published: 07 June 2004 Publication History

Abstract

We propose a novel, nonsimulative probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a dynamic Bayesian network. Dynamic Bayesian networks are extremely powerful in modeling high order temporal, as well as spatial, correlations; TDM is an exact model for the underlying conditional independencies. The attractive feature of this graphical representation of the joint probability function is not only that it makes the dependency relationships amongst nodes explicit, but it also serves as a computational mechanism for probabilistic inference. We report average errors in switching probability of 0.006, with errors tightly distributed around mean error values, on ISCAS'89 benchmark circuits involving up to 10000 signals.

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Cited By

Zhang HJiang YHung WSong XGu MSun J(2014)Symbolic Analysis of Programmable Logic ControllersIEEE Transactions on Computers10.1109/TC.2013.12463:10(2563-2575)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1109/TC.2013.124
Rejimon TLingasubramanian KBhanja S(2009)Probabilistic error modeling for nano-domain logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200316717:1(55-65)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003167
Lingasubramanian KBhanja S(2007)Probabilistic error modeling for sequential logic2007 7th IEEE Conference on Nanotechnology (IEEE NANO)10.1109/NANO.2007.4601266(616-620)Online publication date: Aug-2007
https://doi.org/10.1109/NANO.2007.4601266
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Index Terms

A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks
1. Hardware
  1. Hardware validation

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 11, Issue 3

July 2006

262 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1142980

Issue’s Table of Contents

Copyright © 2004 ACM.

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Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 June 2004

Published in TODAES Volume 11, Issue 3

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Cited By

Zhang HJiang YHung WSong XGu MSun J(2014)Symbolic Analysis of Programmable Logic ControllersIEEE Transactions on Computers10.1109/TC.2013.12463:10(2563-2575)Online publication date: 1-Oct-2014
https://dl.acm.org/doi/10.1109/TC.2013.124
Rejimon TLingasubramanian KBhanja S(2009)Probabilistic error modeling for nano-domain logic circuitsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200316717:1(55-65)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003167
Lingasubramanian KBhanja S(2007)Probabilistic error modeling for sequential logic2007 7th IEEE Conference on Nanotechnology (IEEE NANO)10.1109/NANO.2007.4601266(616-620)Online publication date: Aug-2007
https://doi.org/10.1109/NANO.2007.4601266
Rejimon TBhanja S(2006)A timing-aware probabilistic model for single-event-upset analysisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88416514:10(1130-1139)Online publication date: 1-Oct-2006
https://dl.acm.org/doi/10.1109/TVLSI.2006.884165

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