research-article

System-level PVT variation-aware power exploration of on-chip communication architectures

Authors:

Sudeep Pasricha,

Young-Hwan Park,

Fadi J. KurdahiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 2

Article No.: 20, Pages 1 - 25

https://doi.org/10.1145/1497561.1497563

Published: 07 April 2009 Publication History

Abstract

With the shift towards deep submicron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage, and temperature (PVT) corners. In this article, we first investigate the impact of PVT corners on power consumption at the system-on-chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to “scale up” and abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate level, as well as at the higher system level. Our preliminary results are very interesting, and indicate that (i) there are significant variations in power consumption across PVT corners; and (ii) the PVT-aware power estimation problem may be amenable to a reasonably simple abstraction at the system level.

References

[1]

Adya, S. N. and Markov, I. L. 2003. Fixed-outline floorplanning: Enabling hierarchical design. IEEE Trans. VLSI Syst. 11, 6, 1120--1135.

Digital Library

[2]

Amba Ahb Interconnection Matrix. 2008. http://www.synopsys.com/products/designware/amba_solutions.html.

[3]

Banerjee, K. and Mehrotra, A. 2001. Coupled analysis of electromigration reliability and performance in ULSI signal nets. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. 158--164.

Digital Library

[4]

Benini, L., Macii, A., Poncino, M., and Scarsi, R. 2000. Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 19, 9, 969--980.

Digital Library

[5]

Bona, A., Zaccaria, V., and Zafalon, R. 2004. System level power modeling and simulation of high-end industrial network-on-chip. In Proceedings of the Conference on Design, Automation and Test in Europe.

Digital Library

[6]

Borkar, S., Karnik, T., and De, V. 2004. Design and reliability challenges in nanometer technologies. In Proceedings of the 41^st Design Automation Conference. 75.

Digital Library

[7]

Cadence PKS. 2008. www.cadence.com/datasheets/pks_ds.pdf.

[8]

Caldari, M., Conti, M., Coppola, M., Crippa, P., Orcioni, S., Pieralisi, L., and Turchetti, C. 2003. System-level power analysis methodology applied to the AMBA AHB bus. In Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum.

Digital Library

[9]

Dhanwada, N., Lin, I., and Narayanan, V. 2005. A power estimation methodology for system C transaction level models. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Digital Library

[10]

Faraway, J. J. 2004. Linear Models with R. CRC Press.

[11]

GNU R. 2008. http://www.gnu.org/software/r/R.html.

[12]

Ho, R., Mai, K. W., and Horowitz, M. A. 2001. The future of wires. Proc. IEEE 89, 4, 490--504.

[13]

JVT ISO/IEC MPEG, ITU-T VCEG. 2003. Final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14496-10 AVC). JVT-G050.

[14]

Khandelwal, V. and Srivastava, A. 2005. A general framework for accurate statistical timing analysis considering correlations. In Proceedings of the 42nd Design Automation Conference. 89--94.

Digital Library

[15]

Kretzschmar, C., Nieuwland, A. K., and Müller, D. 2004. Why transition coding for power minimization of on-chip buses does not work. In Proceedings of the Conference on Design, Automation and Test in Europe.

Digital Library

[16]

Lahiri, K. and Raghunathan, A. 2004. Power analysis of system-level on-chip communication architectures. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS). 236--241.

Digital Library

[17]

Lahiri, K., Raghunathan, A., Dey, S., and Panigrahi, D. 2002. Battery-driven system design: A new frontier in low power design. In Proceedings of ASP-DAC 7th Asia and South Pacific Design Automation Conference and Proceedings of the 15^th International Conference on VLSI Design. 261--267.

Digital Library

[18]

Lajolo, M., Raghunathan, A., Dey, S., and Lavagno, L. 2002. Cosimulation-based power estimation for system-on-chip design. IEEE Trans. VLSI Syst. 10, 3, 253--266.

Digital Library

[19]

Le, J., Li, X., and Pileggi, L. T. 2004. STAC: statistical timing analysis with correlation. In Proceedings of the 41^st Design Automation Conference. 343--348.

Digital Library

[20]

Lee, I., Kim, H., Yang, P., Yoo, S., Chung, E., Choi, K., Kong, J., and Eo, S. 2006. PowerViP: SoC power estimation framework at transaction level. In Proceedings of the Asia and South Pacific Conference on Design Automation. 24--27.

Digital Library

[21]

Metro IP. http://www.arm.com/products/physicalip/metro.html.

[22]

Pasricha, S. 2002. Transaction level modeling of SoC with System C 2.0. In Proceedings of the SNUG Conference.

[23]

Pasricha, S. and Dutt, N. 2008. On-Chip Communication Architectures. Morgan Kaufmann/Elsevier.

Digital Library

[24]

Pasricha, S., Dutt, N., and Ben-Romdhane, M. 2004. Extending the transaction level modeling approach for fast communication architecture exploration. In Proceedings of the 41st Annual Conference on Design Automation. 113--118.

Digital Library

[25]

Pasricha, S., Park, Y., Kurdahi, F. J., and Dutt, N. 2006. System-level power-performance trade-offs in bus matrix communication architecture synthesis. In Proceedings of the 4^th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). ACM, 300--305.

Digital Library

[26]

Rabaey, J., Chandrakasan, A., and Nikolic, B. 2003. Digital Integrated Circuits: A Design Perspective 2nd Ed. Prentice-Hall, Englewood Cliffs, NJ.

Digital Library

[27]

Raghunandan, C., Sainarayanan, K. S., and Srinivas, M. B. 2008. Process variation aware bus-coding scheme for delay minimization in VLSI interconnects. In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED). 43--46.

Digital Library

[28]

Sotiriadis, P. P. and Chandrakasan, A. P. 2002. A bus energy model for deep submicron technology. IEEE Trans. Very VLSI Systems 10, 3, 341--350.

Digital Library

[29]

Synopsys CoreTools, PrimeTime PX. 2008. http://www.synopsys.com.

[30]

Systemc Initiative. 2008. http://www.systemc.org.

[31]

Tuuna, S., Isoaho, J., and Tenhunen, H. 2008. Analysis of delay variation in encoded on-chip bus signaling under process variation. In Proceedings of the 21st International Conference on VLSI Design. 228--234.

Digital Library

[32]

Wang, H., Miranda, M., Lobmaier, F., Catthoor, F., and Papanikolaou, A. 2005. A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications. In Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 117--122.

Digital Library

Cited By

Kozhikkottu VDey SRaghunathan AGroeneveld PSciuto DHassoun S(2012)Recovery-based design for variation-tolerant SoCsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228510(826-833)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228510

Index Terms

System-level PVT variation-aware power exploration of on-chip communication architectures
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Interconnection architectures
2. Hardware
  1. Very large scale integration design

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 14, Issue 2

March 2009

384 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1497561

Issue’s Table of Contents

Copyright © 2009 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 April 2009

Accepted: 01 September 2008

Revised: 01 August 2008

Received: 01 July 2008

Published in TODAES Volume 14, Issue 2

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Cited By

Kozhikkottu VDey SRaghunathan AGroeneveld PSciuto DHassoun S(2012)Recovery-based design for variation-tolerant SoCsProceedings of the 49th Annual Design Automation Conference10.1145/2228360.2228510(826-833)Online publication date: 3-Jun-2012
https://dl.acm.org/doi/10.1145/2228360.2228510

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