research-article

Race analysis for systemc using model checking

Authors:

Daniel KroeningAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 3

Article No.: 21, Pages 1 - 32

https://doi.org/10.1145/1754405.1754406

Published: 10 June 2010 Publication History

Abstract

SystemC is a system-level modeling language that offers a wide range of features to describe concurrent systems at different levels of abstraction. The SystemC standard permits simulators to implement a deterministic scheduling policy, which often hides concurrency-related design flaws. We present a novel compiler for SystemC that integrates a very precise formal race analysis by means of model checking. Our compiler produces a simulator that uses the outcome of the analysis to perform partial order reduction. The key insight to make the model checking engine scale is to apply it only to tiny fractions of the SystemC model. We show that the outcome of the analysis is not only valuable to eliminate redundant context switches at runtime, but can also be used to diagnose race conditions statically. In particular, our analysis is able to reveal races that can remain undetected during simulation and is able to formally prove the absence of races.

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Cited By

Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Formale Verifikation von SystemC-basierten Entwürfen durch symbolische SimulationVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_4(63-125)Online publication date: 1-Jan-2023
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Race analysis for systemc using model checking

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 15, Issue 3

May 2010

192 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1754405

Issue’s Table of Contents

Copyright © 2010 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 10 June 2010

Accepted: 01 February 2010

Revised: 01 October 2009

Received: 01 May 2009

Published in TODAES Volume 15, Issue 3

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Cited By

Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2023)Formale Verifikation von SystemC-basierten Entwürfen durch symbolische SimulationVerbessertes virtuelles Prototyping10.1007/978-3-031-18174-0_4(63-125)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-18174-0_4
Shen YPeng YChen JShi LDeng F(2022)Interruption-driven resource competition defect model and testing methodology2022 IEEE 6th Advanced Information Technology, Electronic and Automation Control Conference (IAEAC )10.1109/IAEAC54830.2022.9930087(602-616)Online publication date: 3-Oct-2022
https://doi.org/10.1109/IAEAC54830.2022.9930087
Xiang DZhao FLiu Y(2021)DICER 2.0: A New Model Checker for Data-Flow Errors of Concurrent Software SystemsMathematics10.3390/math90909669:9(966)Online publication date: 25-Apr-2021
https://doi.org/10.3390/math9090966
Xiang DLiu GYan CJiang C(2021)A Guard-Driven Analysis Approach of Workflow Net with DataIEEE Transactions on Services Computing10.1109/TSC.2019.289908614:6(1650-1661)Online publication date: 1-Nov-2021
https://doi.org/10.1109/TSC.2019.2899086
Herdt VDrechsler R(2021)Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challengesScience China Information Sciences10.1007/s11432-020-3308-465:1Online publication date: 23-Dec-2021
https://doi.org/10.1007/s11432-020-3308-4
Lin BXie F(2020)A Systematic Investigation of State-of-the-Art SystemC VerificationJournal of Circuits, Systems and Computers10.1142/S021812662030013529:15(2030013)Online publication date: 18-Jul-2020
https://doi.org/10.1142/S0218126620300135
Herdt VGroße DDrechsler RHerdt VGroße DDrechsler R(2020)Formal Verification of SystemC-Based Designs using Symbolic SimulationEnhanced Virtual Prototyping10.1007/978-3-030-54828-5_4(59-117)Online publication date: 15-Oct-2020
https://doi.org/10.1007/978-3-030-54828-5_4
Herdt VLe HGrobe DDrechsler R(2019)Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic SimulationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663838:7(1359-1372)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846638
Anantharaman PBrady JFlathers PKothari VMillian MReeves JReitinger NNisen WSmith SCarvalho MBishop MSomayaji APieters WMannan M(2018)Going DarkProceedings of the New Security Paradigms Workshop10.1145/3285002.3285011(52-63)Online publication date: 28-Aug-2018
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Biere AKröning D(2018)SAT-Based Model CheckingHandbook of Model Checking10.1007/978-3-319-10575-8_10(277-303)Online publication date: 19-May-2018
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