research-article

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs

Authors:

Kyu-Myung Choi,

Takayasu SakuraiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 4

Article No.: 28, Pages 1 - 37

https://doi.org/10.1145/1835420.1835421

Published: 07 October 2010 Publication History

Abstract

Power Gating has become one of the most widely used circuit design techniques for reducing leakage current. Its concept is very simple, but its application to standard-cell VLSI designs involves many careful considerations. The great complexity of designing a power-gated circuit originates from the side effects of inserting current switches, which have to be resolved by a combination of extra circuitry and customized tools and methodologies. In this tutorial we survey these design considerations and look at the best practice within industry and academia. Topics include output isolation and data retention, current switch design and sizing, and physical design issues such as power networks, increases in area and wirelength, and power grid analysis. Designers can benefit from this tutorial by obtaining a better understanding of implications of power gating during an early stage of VLSI designs. We also review the ways in which power gating has been improved. These include reducing the sizes of switches, cutting transition delays, applying power gating to smaller blocks of circuitry, and reducing the energy dissipated in mode transitions. Power Gating has also been combined with other circuit techniques, and these hybrids are also reviewed. Important open problems are identified as a stimulus to research.

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Index Terms

Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Very large scale integration design

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 15, Issue 4

September 2010

164 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1835420

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Copyright © 2010 ACM.

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Publication History

Published: 07 October 2010

Accepted: 01 April 2010

Revised: 01 March 2010

Received: 01 September 2009

Published in TODAES Volume 15, Issue 4

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Jeba Johannah JKorah RMaria Kalavathy G(2021)Low-Power Deep-Submicron CMOS Adder Using Optimized Delay Universal GatesAdvances in Automation, Signal Processing, Instrumentation, and Control10.1007/978-981-15-8221-9_47(531-549)Online publication date: 5-Mar-2021
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Park J(2020)Hybrid Non-Volatile Flip-Flops Using Spin-Orbit-Torque (SOT) Magnetic Tunnel Junction Devices for High Integration and Low Energy Power-Gating ApplicationsElectronics10.3390/electronics90914069:9(1406)Online publication date: 1-Sep-2020
https://doi.org/10.3390/electronics9091406
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