research-article

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme

Authors:

Wai-Chung Tang,

Yu-Liang WuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 17, Issue 4

Article No.: 50, Pages 1 - 21

https://doi.org/10.1145/2348839.2348854

Published: 01 October 2012 Publication History

Abstract

Rewiring is known to be a class of logic restructuring technique that is at least equally powerful in flexibility compared to other logic transformation techniques. Especially it is wiring sensitive and is particularly useful for interconnect-based circuit synthesis processes. One of the most well-studied rewiring techniques is the ATPG-based Redundancy Addition and Removal (RAR) technique which adds a redundant alternative wire to make an originally irredundant target wire become redundant and thus removable. In this article, we propose a new Error-Cancellation-based Rewiring scheme (ECR) which can also identify non-RAR-based rewiring operations with high efficiency. In ECR scheme, it is not necessary for alternative wires to be redundant. Based on the notion of error cancellation, we analyze and reformulate the rewiring problem, and a more generalized rewiring scheme is developed to detect more rewiring cases which are not obtainable by existing schemes while it still maintains a low runtime complexity. Comparing with the most recent non-RAR rewiring tool IRRA, the total number of alternative wires found by our approach is about doubled (202%) while the CPU time used is just slightly more (8%) upon benchmarks preoptimized by ABC’s rewriting. Our experimental results also suggest that the ECR engine is more powerful than IRRA in FPGA technology mapping.

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Cited By

Lam TTang WWei XDiao YYu‐LiangWu D(2016)Delete‐First Rewiring TechniquesBoolean Circuit Rewiring10.1002/9781118750124.ch4(67-132)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch4
Lam TTang WWei XDiao YYu‐LiangWu D(2016)Concept of Logic RewiringBoolean Circuit Rewiring10.1002/9781118750124.ch2(11-36)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch2
Wei XLam TYang XTang WDiao YWu Y(2014)Delete and Correct (DaC)Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.71(375-380)Online publication date: 5-Jan-2014
https://dl.acm.org/doi/10.1109/VLSID.2014.71

Index Terms

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 17, Issue 4

October 2012

347 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2348839

Issue’s Table of Contents

Copyright © 2012 ACM.

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 2012

Accepted: 01 May 2012

Revised: 01 March 2012

Received: 01 August 2011

Published in TODAES Volume 17, Issue 4

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Cited By

Lam TTang WWei XDiao YYu‐LiangWu D(2016)Delete‐First Rewiring TechniquesBoolean Circuit Rewiring10.1002/9781118750124.ch4(67-132)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch4
Lam TTang WWei XDiao YYu‐LiangWu D(2016)Concept of Logic RewiringBoolean Circuit Rewiring10.1002/9781118750124.ch2(11-36)Online publication date: 8-Jan-2016
https://doi.org/10.1002/9781118750124.ch2
Wei XLam TYang XTang WDiao YWu Y(2014)Delete and Correct (DaC)Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems10.1109/VLSID.2014.71(375-380)Online publication date: 5-Jan-2014
https://dl.acm.org/doi/10.1109/VLSID.2014.71

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