research-article

Mathematical formalisms for performance evaluation of networks-on-chip

Authors:

Abbas Eslami Kiasari,

Zhonghai LuAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 45, Issue 3

Article No.: 38, Pages 1 - 41

https://doi.org/10.1145/2480741.2480755

Published: 03 July 2013 Publication History

Abstract

This article reviews four popular mathematical formalisms—queueing theory, network calculus, schedulability analysis, and dataflow analysis—and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.

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Cited By

Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-180:16(24483-24519)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1007/s11227-024-06340-1
Balti MJEMAI A(2021)Performance survey of classic and Optic network‐on‐chipIET Circuits, Devices & Systems10.1049/cds2.1202515:4(393-402)Online publication date: 2-Mar-2021
https://doi.org/10.1049/cds2.12025
Boyer MGraillat ADupont de Dinechin BMigge J(2020)Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarksPerformance Evaluation10.1016/j.peva.2020.102124(102124)Online publication date: Jul-2020
https://doi.org/10.1016/j.peva.2020.102124
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Index Terms

Mathematical formalisms for performance evaluation of networks-on-chip
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis
      1. Modeling methodologies

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 45, Issue 3

June 2013

575 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/2480741

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Copyright © 2013 ACM.

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Publication History

Published: 03 July 2013

Accepted: 01 April 2012

Revised: 01 August 2011

Received: 01 April 2011

Published in CSUR Volume 45, Issue 3

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Cited By

Patra RMaji PSrivastava DMondal H(2024)Machine learning-driven performance assessment of network-on-chip architecturesThe Journal of Supercomputing10.1007/s11227-024-06340-180:16(24483-24519)Online publication date: 1-Nov-2024
https://dl.acm.org/doi/10.1007/s11227-024-06340-1
Balti MJEMAI A(2021)Performance survey of classic and Optic network‐on‐chipIET Circuits, Devices & Systems10.1049/cds2.1202515:4(393-402)Online publication date: 2-Mar-2021
https://doi.org/10.1049/cds2.12025
Boyer MGraillat ADupont de Dinechin BMigge J(2020)Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarksPerformance Evaluation10.1016/j.peva.2020.102124(102124)Online publication date: Jul-2020
https://doi.org/10.1016/j.peva.2020.102124
Graillat AMaiza CMoy MRaymond Pde Dinechin BErmont JSong YGill C(2019)Response time analysis of dataflow applications on a many-core processor with shared-memory and network-on-chipProceedings of the 27th International Conference on Real-Time Networks and Systems10.1145/3356401.3356416(61-69)Online publication date: 6-Nov-2019
https://dl.acm.org/doi/10.1145/3356401.3356416
Penny WPalomino DPorto MZatt BIndrusiak LMartino JLubaszewski MReorda M(2019)Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platformsProceedings of the 32nd Symposium on Integrated Circuits and Systems Design10.1145/3338852.3339868(1-6)Online publication date: 26-Aug-2019
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Maiza CRihani HRivas JGoossens JAltmeyer SDavis R(2019)A Survey of Timing Verification Techniques for Multi-Core Real-Time SystemsACM Computing Surveys10.1145/332321252:3(1-38)Online publication date: 18-Jun-2019
https://dl.acm.org/doi/10.1145/3323212
Penny WPalomino DPorto MZatt BIndrusiak L(2019)Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms2019 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)10.1109/ReCoSoC48741.2019.9034970(1-8)Online publication date: Jul-2019
https://doi.org/10.1109/ReCoSoC48741.2019.9034970
Dziurzanski PSwan JIndrusiak LRamos J(2019)Implementing Digital Twins of Smart Factories with Interval Algebra2019 IEEE International Conference on Industrial Technology (ICIT)10.1109/ICIT.2019.8755026(941-948)Online publication date: Feb-2019
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Joseph JBamberg LErmel DPerjikolaei BDrewes AGarcia-Ortiz APionteck T(2019)NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and MicroarchitecturesIEEE Access10.1109/ACCESS.2019.29421297(135145-135163)Online publication date: 2019
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Indrusiak LHarbin JReinbrecht CSepúlveda J(2019)Side-channel protected MPSoC through secure real-time networks-on-chipMicroprocessors & Microsystems10.1016/j.micpro.2019.04.00468:C(34-46)Online publication date: 1-Jul-2019
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