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Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors

Published: 29 August 2014 Publication History
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  • Abstract

    Thermal issues have become critical roadblocks for achieving highly reliable three-dimensional (3D) integrated circuits (ICs). The presence of process variations further exacerbates these problems. In this article, we propose techniques for the efficient evaluation and mitigation of the impact of leakage power variations on the temperature profile of 3D Chip Multiprocessors (CMPs). Experimental results demonstrate that, due to the impact of process variations, a 4-tier 3D implementation can be more than 40ˆC hotter and 23% leakier than its 2D counterpart. To determine the maximum temperature of each fabricated 3D IC, we propose an accurate learning-based model for peak temperature prediction. Based on the learning model, we then propose two post-fabrication techniques to increase the thermal yield of 3D CMPs: (1) tier restacking and (2) thermally-aware die matching. Experimental results show that: (1) the proposed prediction model achieves more than 98% accuracy, and (2) the proposed thermally-aware, post-fabrication optimization techniques significantly improve the thermal yield from only 51% to 99% for 3D CMPs.

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    Cited By

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    • (2023)3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238664(1-6)Online publication date: 20-Jun-2023
    • (2022)Yield-aware joint die packing, die matching and static thread mapping for hard real-time 3D embedded CMPsMicroprocessors & Microsystems10.1016/j.micpro.2022.10454392:COnline publication date: 1-Jul-2022
    • (2020)Leakage-Aware Dynamic Thermal Management of 3D MemoriesACM Transactions on Design Automation of Electronic Systems10.1145/341946826:2(1-31)Online publication date: 23-Oct-2020
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    1. Statistical Peak Temperature Prediction and Thermal Yield Improvement for 3D Chip Multiprocessors

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 19, Issue 4
      August 2014
      246 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/2663459
      • Editor:
      • Naehyuck Chang
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Publication History

      Published: 29 August 2014
      Accepted: 01 April 2014
      Revised: 01 April 2014
      Received: 01 December 2012
      Published in TODAES Volume 19, Issue 4

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      Author Tags

      1. 3D IC
      2. chip multiprocessor
      3. leakage power
      4. prediction
      5. process variation
      6. statistical model
      7. temperature
      8. thermal hotspot

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      • (2023)3D-TTP: Efficient Transient Temperature-Aware Power Budgeting for 3D-Stacked Processor-Memory Systems2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI59464.2023.10238664(1-6)Online publication date: 20-Jun-2023
      • (2022)Yield-aware joint die packing, die matching and static thread mapping for hard real-time 3D embedded CMPsMicroprocessors & Microsystems10.1016/j.micpro.2022.10454392:COnline publication date: 1-Jul-2022
      • (2020)Leakage-Aware Dynamic Thermal Management of 3D MemoriesACM Transactions on Design Automation of Electronic Systems10.1145/341946826:2(1-31)Online publication date: 23-Oct-2020
      • (2020)Augmented Cross-Entropy-Based Joint Temperature Optimization of Real-Time 3-D MPSoC SystemsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293932839:10(1987-1999)Online publication date: Oct-2020
      • (2019)PredictNcoolACM Transactions on Embedded Computing Systems10.1145/335820818:5s(1-22)Online publication date: 8-Oct-2019
      • (2019)A Survey of Chip-level Thermal SimulatorsACM Computing Surveys10.1145/330954452:2(1-35)Online publication date: 30-Apr-2019
      • (2019)A Survey of Prediction and Classification Techniques in Multicore Processor SystemsIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.287869930:5(1184-1200)Online publication date: 1-May-2019
      • (2019)Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architectureIntegration, the VLSI Journal10.1016/j.vlsi.2017.12.00265:C(282-292)Online publication date: 1-Mar-2019
      • (2018)Performance and Thermal Tradeoffs for Energy-Efficient Monolithic 3D Network-on-ChipACM Transactions on Design Automation of Electronic Systems10.1145/322304623:5(1-25)Online publication date: 22-Aug-2018
      • (2017)Performance-thermal trade-offs for a VFI-enabled 3D NoC architecture2017 18th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED.2017.7918327(271-276)Online publication date: Mar-2017
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