research-article

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs

Authors:

Chien-Chih Huang,

Pei-Wen LuoAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 1

Article No.: 15, Pages 1 - 17

https://doi.org/10.1145/2770872

Published: 02 December 2015 Publication History

Abstract

The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch. Paralleling unit capacitance (UC) with a common-centroid structure can alleviate the random mismatch errors. The complexity of generating an optimal solution to the UC placement problem is extremely high, let alone if both placement and routing problems are to be optimized simultaneously. This article evaluates the performance of the UC placement generated in an existing work and proposes an alternative UC placement to achieve optimal ratio mismatch M and better linearity performance of SAR ADC design. Results show that the proposed UC placement achieves a ratio mismatch of M = 0.695, the effective number of bits ENOB = 8.314 bits, and the integral nonlinearity INL = 0.816 LSB (least significant bits) for a 9-bit SAR ADC design.

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Cited By

Yenuchenko MPilipko M(2022)A Metric of Elements Placement Properties for Nonlinearity Reduction Prediction in Binary DACs2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus54750.2022.9755486(215-219)Online publication date: 25-Jan-2022
https://doi.org/10.1109/ElConRus54750.2022.9755486
Yenuchenko MPilipko M(2022)Comparative Analysis of Switching Schemes for 8-bit Arrays in Binary DACs2022 International Conference on Electrical Engineering and Photonics (EExPolytech)10.1109/EExPolytech56308.2022.9950860(40-43)Online publication date: 20-Oct-2022
https://doi.org/10.1109/EExPolytech56308.2022.9950860
Karmokar NMadhusudan MSharma AHarjani RLin MSapatnekar S(2022)Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712576(114-121)Online publication date: 17-Jan-2022
https://doi.org/10.1109/ASP-DAC52403.2022.9712576
Show More Cited By

Index Terms

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)
      1. Placement
      2. Wire routing

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 1

November 2015

464 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2852253

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2015 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 02 December 2015

Accepted: 01 May 2015

Revised: 01 April 2015

Received: 01 December 2014

Published in TODAES Volume 21, Issue 1

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Cited By

Yenuchenko MPilipko M(2022)A Metric of Elements Placement Properties for Nonlinearity Reduction Prediction in Binary DACs2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus)10.1109/ElConRus54750.2022.9755486(215-219)Online publication date: 25-Jan-2022
https://doi.org/10.1109/ElConRus54750.2022.9755486
Yenuchenko MPilipko M(2022)Comparative Analysis of Switching Schemes for 8-bit Arrays in Binary DACs2022 International Conference on Electrical Engineering and Photonics (EExPolytech)10.1109/EExPolytech56308.2022.9950860(40-43)Online publication date: 20-Oct-2022
https://doi.org/10.1109/EExPolytech56308.2022.9950860
Karmokar NMadhusudan MSharma AHarjani RLin MSapatnekar S(2022)Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC52403.2022.9712576(114-121)Online publication date: 17-Jan-2022
https://doi.org/10.1109/ASP-DAC52403.2022.9712576
Yenuchenko MPilipko M(2020)Comparative Analysis of Switching Schemes for 6-bit Arrays in Binary DACs2020 IEEE International Conference on Electrical Engineering and Photonics (EExPolytech)10.1109/EExPolytech50912.2020.9243952(71-75)Online publication date: 15-Oct-2020
https://doi.org/10.1109/EExPolytech50912.2020.9243952
Huang CChen JWey C(2017)PACESIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2016.256140336:1(134-145)Online publication date: 1-Jan-2017
https://dl.acm.org/doi/10.1109/TCAD.2016.2561403

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