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Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs

Authors:

Subodha Charles,

Prabhat MishraAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 24, Issue 6

Article No.: 60, Pages 1 - 23

https://doi.org/10.1145/3350422

Published: 09 September 2019 Publication History

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Abstract

Dynamic cache reconfiguration (DCR) is an effective technique to optimize energy consumption in many-core architectures. While early work on DCR has shown promising energy saving opportunities, prior techniques are not suitable for many-core architectures since they do not consider the interactions and tight coupling between memory, caches, and network-on-chip (NoC) traffic. In this article, we propose an efficient cache reconfiguration framework in NoC-based many-core architectures. The proposed work makes three major contributions. First, we model a distributed directory based many-core architecture similar to Intel Xeon Phi architecture. Next, we propose an efficient cache reconfiguration framework that considers all significant components, including NoC, caches, and main memory. Finally, we propose a machine learning--based framework that can reduce the exploration time by an order of magnitude with negligible loss in accuracy. Our experimental results demonstrate 18.5% energy savings on average compared to base cache configuration.

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Cited By

Zhu WZeng X(2021)Decision Tree-Based Adaptive Reconfigurable Cache SchemeAlgorithms10.3390/a1406017614:6(176)Online publication date: 1-Jun-2021
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Charles SMishra P(2021)A Survey of Network-on-Chip Security Attacks and CountermeasuresACM Computing Surveys10.1145/345096454:5(1-36)Online publication date: 25-May-2021
https://dl.acm.org/doi/10.1145/3450964
Shen TGao DZhang LZhao JZhuo C(2021)A Physical-Aware Framework for Memory Network Design Space ExplorationProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431636(865-871)Online publication date: 18-Jan-2021
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 24, Issue 6

November 2019

275 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3357467

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 09 September 2019

Accepted: 01 July 2019

Revised: 01 July 2019

Received: 01 January 2019

Published in TODAES Volume 24, Issue 6

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Cited By

Zhu WZeng X(2021)Decision Tree-Based Adaptive Reconfigurable Cache SchemeAlgorithms10.3390/a1406017614:6(176)Online publication date: 1-Jun-2021
https://doi.org/10.3390/a14060176
Charles SMishra P(2021)A Survey of Network-on-Chip Security Attacks and CountermeasuresACM Computing Surveys10.1145/345096454:5(1-36)Online publication date: 25-May-2021
https://dl.acm.org/doi/10.1145/3450964
Shen TGao DZhang LZhao JZhuo C(2021)A Physical-Aware Framework for Memory Network Design Space ExplorationProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431636(865-871)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431636
Pan ZMishra P(2021)Accelerating Spectral Normalization for Enhancing Robustness of Deep Neural Networks2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI51109.2021.00055(260-265)Online publication date: Jul-2021
https://doi.org/10.1109/ISVLSI51109.2021.00055
Nour SHabashy SSalem S(2021)Energy Optimization by Using Last Level Cache Partitioning for Multicore Platforms2021 16th International Conference on Computer Engineering and Systems (ICCES)10.1109/ICCES54031.2021.9686175(1-6)Online publication date: 15-Dec-2021
https://doi.org/10.1109/ICCES54031.2021.9686175
Charles SMishra P(2021)Securing on-Chip Communication Using Digital WatermarkingNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_9(219-252)Online publication date: 22-Jan-2021
https://doi.org/10.1007/978-3-030-69131-8_9
Charles SMishra P(2021)Real-Time Detection and Localization of DoS AttacksNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_8(183-217)Online publication date: 22-Jan-2021
https://doi.org/10.1007/978-3-030-69131-8_8
Charles SMishra P(2021)Lightweight Anonymous Routing for On-chip InterconnectsNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_6(123-151)Online publication date: 22-Jan-2021
https://doi.org/10.1007/978-3-030-69131-8_6
Charles SMishra P(2021)Trust-Aware Routing in NoC-Based SoCsNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_5(101-121)Online publication date: 22-Jan-2021
https://doi.org/10.1007/978-3-030-69131-8_5
Charles SMishra P(2021)Lightweight Encryption Using Incremental CryptographyNetwork-on-Chip Security and Privacy10.1007/978-3-030-69131-8_4(79-99)Online publication date: 22-Jan-2021
https://doi.org/10.1007/978-3-030-69131-8_4
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