research-article

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC

Authors:

John JoseAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems, Volume 28, Issue 6

Article No.: 97, Pages 1 - 24

https://doi.org/10.1145/3616871

Published: 16 October 2023 Publication History

Abstract

Due to the technological advancements in the last few decades, several applications have emerged that demand more computing power and on-chip and off-chip memories. However, the scaling of memory technologies is not at par with computing throughput of modern day multi-core processors. Conventional memory technologies such as SRAM and DRAM have technological limitations to meet large on-chip memory requirements owing to their low packaging density and high leakage power. In order to meet the ever-increasing demand for memory, researchers came up with alternative solutions, such as emerging non-volatile memory technologies such as STT-RAM, PCM, and ReRAM. However, these memory technologies have limited write endurance and high write energy. This emphasizes the need for a policy that will reduce the writes or distribute the writes uniformly across the memory thereby enhancing its lifetime by delaying the early wear out of memory cells due to frequent writes. We propose two techniques, Enhanced-Virtually Split Cache (E-ViSC) and Protean-Virtually Split Cache (P-ViSC), which dynamically adjust the cache configuration to distribute the writes uniformly across the memory to enhance the lifetime. Experimental studies show that E-ViSC and P-ViSC improve lifetime of NVM L2 caches by upto 2.31× and 1.97× respectively.

References

[1]

Sukarn Agarwal and Hemangee K. Kapoor. 2017. Towards a better lifetime for non-volatile caches in chip multiprocessors. In Proceedings of the 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems. 29–34. DOI:

[2]

Sukarn Agarwal and Hemangee K. Kapoor. 2019. Improving the lifetime of non-volatile cache by write restriction. IEEE Trans. Comput. 68, 9 (2019), 1297–1312. DOI:

Digital Library

[3]

Sukarn Agarwal and Hemangee K. Kapoor. 2020. LiNoVo: Longevity enhancement of non-volatile last level caches in chip multiprocessors. In Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI. 194–199. DOI:

[4]

Hiroyuki Akinaga and Hisashi Shima. 2010. Resistive random access memory (ReRAM) based on metal oxides. Proc. IEEE 98, 12 (2010), 2237–2251. DOI:

[5]

Nathan Binkert, Bradford Beckmann, Gabriel Black, Steven K. Reinhardt, Ali Saidi, Arkaprava Basu, Joel Hestness, Derek R. Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib, Nilay Vaish, Mark D. Hill, and David A. Wood. 2011. The Gem5 simulator. ACM SIGARCH Computer Architecture News 39, 2 (2011), 1–7. DOI:

Digital Library

[6]

Xunchao Chen, Navid Khoshavi, Ronald F. DeMara, Jun Wang, Dan Huang, Wujie Wen, and Yiran Chen. 2017. Energy-aware adaptive restore schemes for MLC STT-RAM cache. IEEE Transactions on Computers 66, 5 (2017), 786–798. DOI:

Digital Library

[7]

Ping Chi, Shuangchen Li, Yuanqing Cheng, Yu Lu, Seung H. Kang, and Yuan Xie. 2016. Architecture design with STT-RAM: Opportunities and challenges. In Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference. 109–114. DOI:

Digital Library

[8]

Xiangyu Dong, Cong Xu, Yuan Xie, and Norman P. Jouppi. 2012. NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, 7 (2012), 994–1007. DOI:

Digital Library

[9]

Carlos Escuin, Pablo Ibañez, Teresa Monreal, Jose M. Llaberia, and Victor Viñals. 2022. Forecasting Lifetime and Performance of a Novel NVM Last-level Cache with Compression. arXiv:2204.03512. Retrieved from https://arxiv.org/abs/2204.03512

[10]

Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Ensieh Aliagha, and Elham Cheshmikhani. 2019. A-CACHE: Alternating cache allocation to conduct higher endurance in NVM-based caches. IEEE Transactions on Circuits and Systems II: Express Briefs 66, 7 (2019), 1237–1241. DOI:

[11]

John L. Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34, 4 (2006), 1–17. DOI:

Digital Library

[12]

Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, and Chita R. Das. 2012. Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs. In Proceedings of the DAC Design Automation Conference 2012. 243–252. DOI:

Digital Library

[13]

Mohammad Reza Jokar, Mohammad Arjomand, and Hamid Sarbazi-Azad. 2016. Sequoia: A high-endurance NVM-based cache architecture. IEEE Transactions on Very Large Scale Integration Systems 24, 3 (2016), 954–967. DOI:

Digital Library

[14]

Sparsh Mittal and Jeffrey S. Vetter. 2014. EqualChance: Addressing intra-set write variation to increase lifetime of non-volatile caches. In Proceedings of the 2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads. USENIX Association.

[15]

Sparsh Mittal and Jeffrey S. Vetter. 2015. AYUSH: A technique for extending lifetime of SRAM-NVM hybrid caches. IEEE Computer Architecture Letters 14, 2 (2015), 115–118. DOI:

Digital Library

[16]

Sparsh Mittal and Jeffrey S. Vetter. 2016. EqualWrites: Reducing intra-set write variations for enhancing lifetime of non-volatile caches. IEEE Transactions on Very Large Scale IntegrationSystems 24, 1 (2016), 103–114. DOI:

Digital Library

[17]

Sparsh Mittal and Jeffrey S. Vetter. 2016. A survey of software techniques for using non-volatile memories for storage and main memory systems. IEEE Transactions on Parallel and Distributed Systems 27, 5 (2016), 1537–1550. DOI:

Digital Library

[18]

Sparsh Mittal, Jeffrey S. Vetter, and Dong Li. 2014. LastingNVCache: A technique for improving the lifetime of non-volatile caches. In Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI. 534–540. DOI:

Digital Library

[19]

Sparsh Mittal, Jeffrey S. Vetter, and Dong Li. 2014. WriteSmoothing: Improving lifetime of non-volatile caches using intra-set wear-leveling. In Proceedings of the 24th Edition of the Great Lakes Symposium on VLSI. Association for Computing Machinery, New York, NY, 139–144. DOI:

Digital Library

[20]

Moinuddin K. Qureshi, Andre Seznec, Luis A. Lastras, and Michele M. Franceschini. 2011. Practical and secure PCM systems by online detection of malicious write streams. In Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture. 478–489. DOI:

[21]

Arindam Sarkar, Newton Singh, Varun Venkitaraman, and Virendra Singh. 2021. DAM: Deadblock aware migration techniques for STT-RAM-based hybrid caches. IEEE Computer Architecture Letters 20, 1 (2021), 62–64. DOI:

[22]

Andre Seznec. 2010. A phase change memory as a secure main memory. IEEE Computer Architecture Letters 9, 1 (2010), 5–8. DOI:

Digital Library

[23]

S. Sivakumar, T. M. Abdul Khader, and John Jose. 2021. Improving lifetime of non-volatile memory caches by logical partitioning. In Proceedings of the 2021 on Great Lakes Symposium on VLSI.Association for Computing Machinery, New York, NY, 123–128. DOI:

Digital Library

[24]

S. Sivakumar, Mani Mannampalli, and John Jose. 2023. Enhancing lifetime of non-volatile memory caches by write-aware techniques. In Proceedings of the Emerging Electronic Devices, Circuits and Systems.Chandan Giri, Takahiro Iizuka, Hafizur Rahaman, and Bhargab B. Bhattacharya (Eds.), Springer Nature Singapore, Singapore, 109–123.

[25]

Jue Wang, Xiangyu Dong, Yuan Xie, and Norman P. Jouppi. 2013. i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations. In Proceedings of the 2013 IEEE 19th International Symposium on High Performance Computer Architecture. 234–245. DOI:

Digital Library

[26]

H.-S. Philip Wong, Simone Raoux, SangBum Kim, Jiale Liang, John P. Reifenberg, Bipin Rajendran, Mehdi Asheghi, and Kenneth E. Goodson. 2010. Phase change memory. Proc. IEEE 98, 12 (2010), 2201–2227. DOI:

[27]

Wangyuan Zhang and Tao Li. 2009. Characterizing and mitigating the impact of process variations on phase change based memory systems. In Proceedings of the 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture. 2–13.

Digital Library

Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452

Index Terms

Self Adaptive Logical Split Cache Techniques for Delayed Aging of NVM LLC
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
      1. Embedded hardware

Recommendations

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers
Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable ...
Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime

Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging design ...
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policy
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

In recent years, NVM (non-volatile memory) technologies, such as STT-RAM (spin transfer torque RAM) and PRAM (phase change RAM), have drawn a lot of attention due to their low leakage and high density. However, both NVMs suffer from high write latency ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 28, Issue 6

November 2023

404 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3627977

Editor:
Hu X. Sharon
University of Notre Dame, USA

Issue’s Table of Contents

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 16 October 2023

Online AM: 24 August 2023

Accepted: 05 August 2023

Revised: 08 June 2023

Received: 09 March 2023

Published in TODAES Volume 28, Issue 6

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
209
Total Downloads

Downloads (Last 12 months)153
Downloads (Last 6 weeks)10

Reflects downloads up to 23 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Full Text

View this article in Full Text.

Media

Figures

Other

Tables

View full text|Download PDF

View Issue’s Table of Contents