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BIST and production testing of ADCs using imprecise stimulus

Published: 01 October 2003 Publication History

Abstract

A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n-bit ADC by using a ramp signal of much less than n-bit linearity and a shifted version of the same nonlinear ramp as excitation. The performance of the algorithm is comparable to that of the traditional method which uses (n + 3)-bits or a decade more linear input signals. Complete algorithm description, extensive simulation results and experimental results obtained from using a production tester on commercially available ICs are presented to validate the potential of this algorithm.

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      cover image ACM Transactions on Design Automation of Electronic Systems
      ACM Transactions on Design Automation of Electronic Systems  Volume 8, Issue 4
      October 2003
      194 pages
      ISSN:1084-4309
      EISSN:1557-7309
      DOI:10.1145/944027
      Issue’s Table of Contents
      Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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      Published: 01 October 2003
      Published in TODAES Volume 8, Issue 4

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      Author Tags

      1. ADC linearity
      2. Analog and mixed-signal testing
      3. built-in self-test
      4. imprecision measurement
      5. imprecision stimulus
      6. production test

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      Cited By

      View all
      • (2018)Knowledge- and Simulation-Based Synthesis of Area-Efficient Passive Loop Filter Incremental Zoom-ADC for Built-In Self-Test ApplicationsACM Transactions on Design Automation of Electronic Systems10.1145/326622724:1(1-27)Online publication date: 21-Dec-2018
      • (2015)A Structured Methodology for Measurement DevelopmentIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2015.239902364:9(2367-2379)Online publication date: Sep-2015
      • (2009)An on-chip solution for static ADC test and measurementProceedings of the 19th ACM Great Lakes symposium on VLSI10.1145/1531542.1531564(81-86)Online publication date: 10-May-2009
      • (2007)Testing High-Resolution ADCs With Low-Resolution/Accuracy Deterministic Dynamic Element Matched DACsIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2007.90362156:5(1753-1762)Online publication date: Oct-2007
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      • (2006)A SNDR BIST for \Sigma\Delta Analogue-to-Digital ConvertersProceedings of the 24th IEEE VLSI Test Symposium10.1109/VTS.2006.12(314-319)Online publication date: 30-Apr-2006
      • (2006)A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy ExcitationsIEEE Transactions on Instrumentation and Measurement10.1109/TIM.2006.87382155:3(902-915)Online publication date: Jun-2006
      • (2006)A Robust, Self-Tuning CMOS Circuit for Built-in Go/No-Go Testing of Synthesizer Phase Noise2006 IEEE International Test Conference10.1109/TEST.2006.297696(1-10)Online publication date: Oct-2006
      • (2006)A Statistical Digital Equalizer for Loopback-based Linearity Test of Data Converters2006 15th Asian Test Symposium10.1109/ATS.2006.261027(245-250)Online publication date: Dec-2006
      • (2006)A BIST Scheme for SNDR Testing of ΣΔ ADCs Using Sine-Wave FittingJournal of Electronic Testing: Theory and Applications10.1007/s10836-006-9500-z22:4-6(325-335)Online publication date: 1-Dec-2006
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