article

Free access

A survey of Boolean matching techniques for library binding

Editor: C. L. Liu Authors:

Giovanni De MicheliAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2, Issue 3

Pages 193 - 226

https://doi.org/10.1145/264995.264996

Published: 01 July 1997 Publication History

Abstract

When binding a logic network to a set of cells, a fundamental problem is recognizing whether a cell can implement a portion of the network. Boolean matching means solving this task using a formalism based on Boolean algebra. In its simplest form, Boolean matching can be posed as a tautology check. We review several approaches to Boolean matching as well as to its generalization to cases involving don't care conditions and its restriction to specific libraries such as those typical of anti-fuse based FPGAs. We then present a general formulation of Boolean matching supporting multiple-output logic cells.

References

[1]

BENINI, L., FAVALLI, M., AND DE MICHELI, G. 1995. Generalized matching, a new approach to concurrent logic optimization and library binding. In Logic synthesis.

[2]

BRACE, K. S., RUDELL, R. L., AND BRYANT, R.E. 1990. Efficient implementation of a BDD package. In 27th ACM/IEEE design automation conference (Orlando, FL, June 24-28, 1990). ACM Press, New York, NY, 40-45.

[3]

BRAYTON, R., HACHTEL, G., MCMULLEN, C., AND SANGIOVANNI-VINCENTELLI, A. 1984. Logic minimization algorithms for VLSI synthesis. Kluwer Academic Publishers, Hingham, MA.

[4]

BROWN, F. 1990. Boolean reasoning. Kluwer Academic Publishers, Hingham, MA.

[5]

BRYANT, R. E. 1986. Graph-based algorithms for Boolean function manipulation. IEEE Trans. Comput. C-35, 8 (Aug.), 677-691.

[6]

BURCH, J. R. AND LONG, D.E. 1992. Efficient Boolean function matching. In Computeraided design (Santa Clara, CA, Nov. 8-12, 1992). IEEE Computer Society Press, Los Alamitos, CA, 408-411.

[7]

CHEN, K.-C. 1993. Boolean matching based on Boolean unification. In Computer-aided design, 346-351.

[8]

CHENG, D. I. AND MAREK-SADOWSKA, M. 1993. Verifying equivalence of functions with unknown input correspondence. In Design Automation, 81-85.

[9]

CLARKE, E. M., MCMILLAN, K. L., ZHAO, X, FUJITA, M., AND YANG, J. 1993. Spectral transforms for large boolean functions with applications to technology mapping. In Design automation conference (Dallas, TX, June 14-18, 1993). ACM Press, New York, NY, 54-60.

[10]

CONG, J. AND DING, Y. 1992. An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. In Computer Aided Design, 48-53.

[11]

CONG, J. AND DING, Y. 1996. Combinational logic synthesis for LUT based field programmable gate arrays. ACM Trans. Des. Autom. Electron. Syst. 1, 2 (Apr.), 145-204.

[12]

DARRINGER, J., JOYNER, W., BERMAN, L., AND TREVILLYAN, L. 1981. LSS: Logic synthesis through local transformations". IBM J. Res. Dev. 25, 4 (July), 272-280.

[13]

DE MICHELI, a. 1994. Synthesis and optimization of digital circuits. McGraw-Hill, Inc., New York, NY.

[14]

DETJENS, E. AND GANNOT, G., ET AL. 1987. Technology mapping in MIS. In Computer-Aided Design, 116-119.

[15]

EDWARDS, C. 1975. Applications of Rademacher-Walsh transform to Boolean function classification and threshold logic synthesis. IEEE Trans. Comput. (Jan.), 48-62.

[16]

ERCOLANI, S. AND DE MICHELI, G. 1991. Technology mapping for electrically programmable gate arrays. In ACM/IEEE design automation conference (San Francisco, CA, June 17-21, 1991). ACM Press, New York, NY, 234-239.

[17]

FORTAS, A., BOUZOUZOU, H., CRASTES, M., ROANE, R., AND SAUCIER, G. 1995. Mapping techniques for Quicklogic FPGA. In SASIMI.

[18]

GAREY, M. AND JOHNSON, D. 1979. Computers and intractability. W. H. Freeman & Co., New York, NY.

[19]

GREEN, J., HAMDY, E., AND BEAL, S. 1993. Antifuse field programmable gate arrays. Proc. IEEE 81, 7 (July), 1041-1056.

[20]

GREGORY, D., BARTLETT, K., DE GEUS, A., AND HACHTEL, G. 1986. Socrates: A System for Automatically synthesizing and optimizing combinational logic. In Design automation, 79-85.

[21]

HURST, S., MILLER, D., AND MUZIO, J. 1985. Spectral techniques in digital logic. Academic Press Ltd., London, UK.

[22]

KARPLUS, K. 1991. Amap: a technology mapper for selector-based field-programmable gate arrays. In Design Automation, 244-247.

[23]

KEUTZER, K. 1987. DAGON: technology binding and local optimization by DAG matching. In Design automation conference (Miami Beach, FL, June 28-July 1, 1987) A. O'Neill and D. Thomas, Eds. ACM Press, New York, NY, 341-347.

[24]

MOHNKE, J. AND MALIK, S. 1993. Permutation and phase independent Boolean comparison. Integr. VLSI J. 16, 2 (Dec.), 109-129.

[25]

MORRISON, C. R., JACOBY, R. M., AND HACHTEL, G.D. 1989. Techmap: technology mapping with delay and area optimization. In Logic and Architecture Synthesis for Silicon Compilers. North-Holland Publishing Co., Amsterdam, The Netherlands, 53-64.

[26]

MURGAI, R., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. L. 1992. An improved synthesis algorithm for multiplexor-based PGA's. In Design automation conference (Anaheim, CA, June 8-12, 1992). IEEE Computer Society Press, Los Alamitos, CA, 380-386.

[27]

SAVOJ, g., SILVA, M. J., BRAYTON, R. K., AND SANGIOVANNI-VINCENTELLI, A. 1992. Boolean matching in logic synthesis. In European Design Automation (Congress Centrum Hamburg, Hamburg, Germany, Sept. 7-10, 1992). IEEE Computer Society Press, Los Alamitos, CA, 168-174.

[28]

SCHLICHTMANN, U., BRGLEZ, F., AND HERMANN, M. 1992. Characterization of Boolean functions for rapid matching in FPGA technology mapping. In Design automation conference (Anaheim, CA, June 8-12, 1992). IEEE Computer Society Press, Los Alamitos, CA, 374- 379.

[29]

SCHLICHTMANN, U., BRGLEZ, F., AND SCHNEIDER, P. 1993. Efficient Boolean matching based on unique variable ordering. In Logic Synthesis.

[30]

SOMENZI, F. AND BRAYTON, R.K. 1989. Minimization of Boolean relations. In Circuits and systems, 738-743.

[31]

TRIMBERGER, S. 1993. A reprogrammable gate array and application. Proc. IEEE 81, 7 (July), 1030-1041.

[32]

TSAI, C.-C. AND MAREK-SADOWSKA, M. 1994. Boolean matching using generalized Reed- Muller forms. In Design automation (San Diego, CA, June 6-10, 1994). ACM Press, New York, NY, 339-344.

[33]

WANG, K.-H. AND HWANG, T.-T. 1995. Boolean matching for incompletely specified functions. In Design automation conference (San Francisco, CA, June 12-16, 1995). ACM Press, New York, NY, 48-53.

[34]

WANG, K. H., HWANG, T.-T., AND CHEN, C. 1996. Exploiting communication complexity in Boolean matching. IEEE Transactions on CAD/ICAS 15, 10 (Oct.), 1249-1256.

[35]

WATANABE, Y., GUERRA, L. M., AND BRAYTON, R.K. 1996. Permissible functions for multioutput components in combinational logic optimization. IEEE Transactions on CAD/ICAS 15, 7 (July), 734-744.

[36]

WONG, S., So, H., Ov, J., AND COSTELLO, J. 1989. A 5000-gate CMOS EPLD with multiple logic and interconnect array. In Custom Integrated Circuit, 581-584.

[37]

YANG, J. AND DE MICHELI, G. 1991. Spectral techniques for technology mapping: A CSL report.

[38]

YANG, C.-H., CHEN, S.-J., HO, J.-M., AND TSAI, C.-C. 1997. Hmap: a fast mapper for EPGAs using extended GBDD hash tables. ACM Trans. Des. Autom. Electron. Syst. 2, 2 (Apr.).

Cited By

Calvino ADe Micheli G(2024)Scalable Logic Rewriting Using Don't Cares2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546807(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546807
Chen TJiang JDe V(2024)Boolean Matching Reversible Circuits: Algorithm and ComplexityProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657312(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657312
Pan HXia YWang LChu Z(2024)Semi-Tensor Product-Based Exact Synthesis for Logic RewritingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333727943:4(1093-1106)Online publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3337279
Show More Cited By

Index Terms

A survey of Boolean matching techniques for library binding
1. Hardware
  1. Integrated circuits
    1. Logic circuits

Recommendations

Simulation and SAT-based Boolean matching for large Boolean networks
DAC '09: Proceedings of the 46th Annual Design Automation Conference

Boolean matching is to check the equivalence of two target functions under input permutation and input/output phase assignment. This paper addresses the permutation independent (P-equivalent) Boolean matching problem. We will propose a matching ...
Boolean quantification techniques with applications in formal verification: algorithms and analysis
A satisfiability procedure for quantified boolean formulae
The renesse issue on satisfiability

We present a satisfiability tester QSAT for quantified Boolean formulae and a restriction QSAT_CNF of QSAT to unquantified conjunctive normal form formulae. QSAT makes use of procedures which replace subformulae of a formula by equivalent formulae. By a ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 2, Issue 3

July 1997

113 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/264995

Editor:
C. L. Liu
Univ. of Illinois at Urbana-Champaign, Urbana

Issue’s Table of Contents

Copyright © 1997 ACM.

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 July 1997

Published in TODAES Volume 2, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

93
Total Citations
View Citations
1,125
Total Downloads

Downloads (Last 12 months)150
Downloads (Last 6 weeks)19

Reflects downloads up to 12 Nov 2024

Other Metrics

View Author Metrics

Citations

Cited By

Calvino ADe Micheli G(2024)Scalable Logic Rewriting Using Don't Cares2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE58400.2024.10546807(1-6)Online publication date: 25-Mar-2024
https://doi.org/10.23919/DATE58400.2024.10546807
Chen TJiang JDe V(2024)Boolean Matching Reversible Circuits: Algorithm and ComplexityProceedings of the 61st ACM/IEEE Design Automation Conference10.1145/3649329.3657312(1-6)Online publication date: 23-Jun-2024
https://dl.acm.org/doi/10.1145/3649329.3657312
Pan HXia YWang LChu Z(2024)Semi-Tensor Product-Based Exact Synthesis for Logic RewritingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.333727943:4(1093-1106)Online publication date: 1-Apr-2024
https://dl.acm.org/doi/10.1109/TCAD.2023.3337279
Radi GCalvino ADe Micheli G(2024)In Medio Stat Virtus*: Combining Boolean and Pattern Matching2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC)10.1109/ASP-DAC58780.2024.10473889(404-410)Online publication date: 22-Jan-2024
https://doi.org/10.1109/ASP-DAC58780.2024.10473889
GE XKIMURA S(2023)Theory and Application of Topology-Based Exact Synthesis for Majority-Inverter GraphsIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.2022EAP1103E106.A:9(1241-1250)Online publication date: 1-Sep-2023
https://doi.org/10.1587/transfun.2022EAP1103
Bairamkulov RCalvino ADe Micheli G(2023)Synthesis of SFQ Circuits with Compound Gates2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)10.1109/VLSI-SoC57769.2023.10321853(1-6)Online publication date: 16-Oct-2023
https://doi.org/10.1109/VLSI-SoC57769.2023.10321853
Calvino ADe Micheli G(2023)Technology Mapping Using Multi-Output Library Cells2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323999(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323999
Chou CHsu CWu CTu KKhoo K(2023)Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323797(1-4)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323797
Calvino AMishchenko ASchmit HMahintorabi EMicheli GXu X(2023)Improving Standard-Cell Design Flow using Factored Form Optimization2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247905(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247905
Calvino ARiener HRai SKumar ADe Micheli GWang T(2022)A Versatile Mapping Approach for Technology Mapping and Graph OptimizationProceedings of the 27th Asia and South Pacific Design Automation Conference10.1109/ASP-DAC52403.2022.9712552(410-416)Online publication date: 17-Jan-2022
https://dl.acm.org/doi/10.1109/ASP-DAC52403.2022.9712552
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

Media

Figures

Other

Tables

View Issue’s Table of Contents