Dimitri Galayko

This paper presents a functional design and modeling of smart conditioning circuit of a vibrational energy harvester based on electrostatic transducer. Two original features are added to the basic configuration previously published (whose model we presented on BMAS2007 conference). Firstly, we developed an auto-calibration block which allows the new harvester to adapt dynamically to the varying environment parameters (e.g., amplitude of external vibrations). Secondly, we propose an original schematic configuration based on dual output DC-DC converter, which implements a smart power interface with the load, allowing the harvester to manage a possibly variable load and adapt to different situations (e.g. unsufficient generated power level, load too large, etc.). The scheme of the power interface re-uses the coil existing in the basic harvester configuration. The new harvester architecture contains ldquosoftwarerdquo blocks which can be programmed to implement different power-management and auto-calibration strategies. We describe one possible algorithm of the whole architecture operation, and present the corresponding modeling results. The system is implemented as a mixed VHDL-AMS/ELDO model.

The search for compact autonomous devices has been increasing in the microelectronics industry. These devices have the capacity to generate their own energy in order to be charged. One of the ways of harvesting environmental energy for charging such devices is by using mechanical vibrations through the use of variable capacitor. Taking this principle a basis, this work presents a behavioral analysis of a system model of harvesting vibratory energy for low power, made up of a circuit which includes a variable capacitor and a piezoelectric transducer. An architecture of a circuit which improves the ratio “amount of harvested energy - circuit area” comparing with conventional architectures is presented. The conventional circuit harvested a maximum power of 4.5μW whereas the circuit with the new architecture harvested a 6.25 μW power. The paper shows a use of a piezoelectric generator providing initial power and compensating the leakage losses in the capacitors.

This paper presents a novel silicon-based and batch-processed MEMS electrostatic transducer for harvesting and converting the energy of vibrations into electrical energy without using an electret layer. Effective conversion from the mechanical-to-electric domains of 61 nW on a 60 MΩ resistive load, under a vibration level of 0.25 g at 250 Hz, has been demonstrated. Rigorous analysis of the efficiency of the harvester is presented, covering issues related with mechanical and electrical operation. Various schemes for the conditioning electronics are discussed and the harvested power measurements using a dc/dc converter are explained in detail. The paper concludes with a comparison with previous electrostatic transducers based on a new simple factor of merit.

This paper presents the results of modeling of a mixed non-linear, strongly coupled and multidomain electromechanical system designed to scavenge the energy of ambient vibrations and to generate an electrical supply for an embedded microsystem. The system is operating in three domains: purely mechanical (the resonator), coupled electromechanical (electrostatic transducer associated with the moving mass) and electrical circuit, including switches, diodes and linear electrical components. Although only linear networks can be properly modeled in SystemC-AMS, we propose a technique allowing modeling of electrical networks including non-linear components (diodes) as well as time-varying capacitors. The whole system was modeled using two solvers of SystemC-AMS simultaneously: the one allowing TDF (Timed Data Flow) modeling and the one allowing LIN ELEC (linear electrical) circuit analysis. The modeling results are compared with VHDL-AMS and Matlab Simulink models.

In this paper, we describe an architecture of a distributed ADPLL (All Digital Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uni- and bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the robustness to possible network failures in comparison to simple unidirectional mode.

ABSTRACT This paper presents a new architecture of bang- bang phase frequency detector based on standard cells. The pro- posed architecture presents advantages in terms of compatibility with fully-automated design flow of digital circuitry compared with other architectures. The metastability failure is also studied. The reliability of this architecture is approved by simulation results in CMOS65 nm.

ABSTRACT This paper presents a CMOS 1.1-2.8 GHz 10 bits digitally controlled oscillator (DCO) for high speed clocking of SoCs. The DCO includes only 269 tuning cells, which is possible thanks to an original algorithm based on weighted combined thermometer code, used for the DCO frequency control. The control circuit of the DCO includes only binary-to-thermometer decoders: that was possible with the proposed technique of virtual extension of number of the DCO ring. It was implemented in 65-nm CMOS technology, with semi-custom layout design allowed to optimize the area on silicon. The design was validated by transistor-level ELDO extracted schematic simulation. Oscillator shows a good linearity in the frequency tunning range, with average power consumption 6 mW/GHz with 1.1 V supply voltage. Typical phase noise with 1 MHz offset and 2 GHz carrying frequency is -86.12 dBc/Hz.

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done.

ABSTRACT Clock distribution networks of synchronized oscillators are an alternative approach to classical tree-like clock distribution methods. Each node of the network may consist of a phase-locked loop (PLL) trying to match the phase of its neighbors. Then a network of independent oscillators takes the place of the centralized clock source, providing separate clock signals to the physically distant parts of the system. In the discrete case, the digital filter is necessarily operated asynchronously: each operation is triggered by a rising edge of the locally-generated clock, the frequency and phase of which vary as the whole system tries to synchronize. The locking behavior, the synchronous state and the stability conditions of such a system are analyzed. Similarly, the synchronization of an autonomous network of two self-sampled PLLs is studied. Surprisingly, its analysis is much simpler than that of the single PLL.

This paper presents an FPGA platform for the design and study of network of coupled All-Digital Phase Locked Loops (ADPLLs), destined for clock generation in large synchronous System on Chip (SoC). An implementation of a programmable and reconfigurable 4×4 ADPLL network is described. The paper emphasizes the difference between the FPGA and ASIC-based implementation of such a system, in particular, implementation of digitally controlled oscillators and phase-frequency detector. The FPGA-implemented network allows studying complex phenomena related to coupled ADPLL operation and exploiting stability issues and nonlinear behavior. A dynamic setup mechanism has been proposed for the network, allowing selecting the desirable synchronized state. Experimental results demonstrate the global synchronization of network and performance of the network for different configurations.

Tri-state inverter based DCO are emerging as an attractive circuit for the implementation of fully digital PLL. In this paper, we first introduce an analytical expression of the tuned period as a function of design and technology parameters. Then, we propose a sizing methodology for the CMOS implementation of a tri-state inverter based DCO. Finally, we applied this methodology to

This paper presents a novel method of implementing coupled resonator micro-mechanical (MEMS) filters without mechanical springs. The method proposes to use an electrostatical spring, formed by two or more electrostatical transducers, to couple single resonators. This spring has a stiffness controlled by bias voltages, thus variable-bandwidth filters can be obtained. An original biasing scheme is used to avoid external connections on sensitive signal nodes. Theoretical analysis as well as experimental results on 4-th order bandpass filters at 2.5 MHz are presented.

This paper describes the theory, design and test of a novel architecture of highly-selective micromechanical filters employing electrostatically coupled resonators with floating or biased coupling electrodes. This original method avoids the use of mechanical coupling springs thus extending the potential of a given process to higher frequencies. It gives also the possibility to implement more complex filter architectures and to tune the coupling factor of resonators. Filters with 2.8 MHz and 10.6 MHz center frequency having tunable relative bandwidths of 0.025-0.17% have been built from pairs of clamped-clamped beam resonators. Special design techniques have been used to reduce parasitic capacitances on the coupling node.

For the past few years, the mobile phone market has been facing fast growth. However, the first generations of mobile telecommunications were based on several different standards over the world, and even at the time major operators negotiate for the third generation licenses, it seems UMTS, CDMA2000 and TD-SCDMA cannot achieve one single standard. A great challenge would be to develop flexible, re-configurable mobile phone handsets that could switch from one standard to another. To do so, MEMS technology is expected as a promising solution to provide tiny, low-consumption tunable components. Moreover, enhancing MEMS technologies to be compatible with IC processing, a novel architecture can be used for a MEMS-based transceiver that could reach the ultimate goal of a fully-integrated single-chip system. Indeed, it has been recently demonstrated that every off-chip, bulky, and expensive passive component present in a typical superheterodyne transceiver front-end could be advantageously replaced by an RF-MEMS counterpart. For example, micro-mechanical resonators could avoid the use of ceramic, SAW, and quartz off-chip resonators to allow low-loss filtering, mixing and carrier generation. But that kind of micro-scale resonators requires high quality factor and temperature stability to achieve highly selective filtering and low phase-noise frequency references. So, to demonstrate this ability, resonators and filters with center frequency up to 300 MHz were designed, and for their fabrication, two processes have been undertaken: an epitaxial thick-film polysilicon industrial technology and a thin-film polysilicon-based technology made compatible with a CMOS-SOI technology.