Test Vectors

Abstract—This paper deals with the testable design of conservative logic ogic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. ThisReversible Reversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low low power VLSI circuits. circuits.Theoptimized designs igns of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This This proposed design can identify any stuck-at-fault fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbageoutput, output, power dissipation and testability.Thisproposeddesign canidentify any stuck-at-fault in the ci...

A digital comparator is a hardware electronic device or a combinational logic circuit. It is capable of comparing two numbers as input in binary form and determines the output. In the previous designs like in the design of XOR-XNOR(XE) with cross-coupled p-MOS, even though it occupies less area, the full swing output voltage can't be able to produce which creates a problem when the bit width increases. To avoid this kind of disadvantages we are designing a N-bit digital comparator in a way such that it produces full swing output voltage with the improved power efficiency as well as the transistor count in the circuit also decreases. So that it can be used in several applications like scientific computations and test circuit applications etc. I.

In this paper, we implemented 2-bit Multiplier Circuit using Pass Transistor Logic. Pass Transistor Logic is used for high speed technology and is easy to build the basic gate structures. The developed circuit is an extension of pass transistor logic Ex-or gate. The proposed Multiplier circuit is implemented in 2x2 bit multiplier to achieve high speed, low area and less power dissipation. VLSI schematic tool and the analysis is done by using the LT Spice simulator. This paper aims at an optimization of power area and voltages of multiplier to show the better performance. The design is implemented in 0.18um CMOS technology and its functional parameters are compared and the best result is incorporated. Simulation results have been performed on LT Spice tool simulator at 1.8v and 2v supply voltage and simulations are carried out indicate the functionality of the proposed multiplier circuit compared with conventional design to verify the effectiveness and it shows the circuit has low power dissipation at high speeds.

In this paper, slice level optimization is performed on the conventional 6:3 counter and then finally integrated all the slices to the original one. Slice level optimization corresponds to partition the given circuit in to number of blocks such that final integration can be done effectively. Considering individual blocks Power testing and delay testing, results were taken by triggering the activities which lead to power consumption and all possible critical paths were also tested for every individual block and then comparison is made. Test vectors are also applied such that every consecutive cycle output is complemented, so that low to high and high to low delays can be captured with in a smaller number of test vectors. Identical strategy is applied to measure the power because for every two cycles only one power consuming event occurs on a single node under consideration. The proposed 6:3 counter is 36% faster than the conventional one and also saves the power for about 56%. Utilizing more NAND, NOR and AOI gates instead of AND, OR gates have led to the achieved optimization.

— This paper deals with the testable design of conservative logic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. This Reversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low power VLSI circuits.The optimized designs of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This proposed design can identify any stuck-at-fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbage output, power dissipation and testability.This proposed design can identify any stuck-at-fault in the circuits. Keywords- Conservative logic, Fredkin gate, gar...

Abstract—This paper deals with the testable design of conservative logic ogic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. ThisReversible Reversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low low power VLSI circuits. circuits.Theoptimized designs igns of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This This proposed design can identify any stuck-at-fault fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbageoutput, output, power dissipation and testability.Thisproposeddesign canidentify any stuck-at-fault in the ci...

Programmable reversible logic design is trending as a prospective logic design style for implementation in recent nanotechnology and quantum computing with low impact on circuit heat generation.The design of testable sequential circuits by two vectors using conservative logic. The proposed sequential circuits based on conservative logic outclass the traditional sequential circuits built using classical gates in terms of testability. Any sequential circuits based on conservative logic can test for stuck-at 0 and stuck-at 1 fault by using two vectors 0 and 1. The design of testable Master-slave D flip-flop, Double Edge triggered flip flop (DET) flip-flop using two vectors 0 and 1 are presented. The importance of the proposed work is that we are designing reversible sequential circuits suitable for testing. Hence both conservative logic and reversible logic is used. In the proposed work, we design a reversible sequential circuit using Fredkin gate. Fredkin gate is the only reversible g...

https://www.ijert.org/toffoli-based-reversible-sequential-circuits

https://www.ijert.org/research/toffoli-based-reversible-sequential-circuits-IJERTV3IS20582.pdf

A Number of fundamental principles of physics such as reversibility of dynamic laws is conservative logic. Conservative logic is reversible. Reversible logic is one of the emerging technologies and several researchers have focused their efforts on the design of reversible logic circuits. The design of reversible logic circuits is mostly used in Quantum Computing, Nano Technology and Low Power Digital Circuits. The number of garbage outputs and quantum cost depend upon reversible logic. Low power consumption, speed and delay are the major requirements in VLSI technology. In this paper, deals with the design of Toffoli gate based on Double edge Triggered Flipflop (DET). Toffoli gate is better than the Fredkin gate in terms of power consumption, number of gates and area. The proposed design of reversible sequential circuits using Toffoli gate are verified by using cadence simulation and the simulated results are presented.

Reversible logic has shown wide applications in emerging technologies such as quantum computing, optical computing, and extremely low power VLSI circuits. Recently, many researchers have focused on the design and synthesis of efficient reversible logic circuits. In this work, as an example of reversible logic sequential circuits, we propose a novel reversible logic design of the Universal Shift Register. Here, we proposed a D-flip-flop whose efficiency is shown in terms of garbage output, constant input and number of reversible gates. Using this D flip-flop, efficient universal shift register is proposed. Universal shift register is a register that has both right and left shifts and parallel load capabilities. The proposed designs were functionally verified through simulations using Verilog Hardware Description Language.

Reversible logic marks a promising new direction where all operations are performed in an invertible manner. It has wide applications like low power CMOS design, Nano-technology, Digital Signal Processing, Communication and Optical computing. In this paper, MFG and SG gates are used to realize D-latch and D-flip flop. Then, 3-bit reversible Linear Feedback Shift Register (LFSR) has been designed using the reversible D-Flip flop. These designs are compared in terms of quantum cost and garbage outputs. Then the designed LFSRs are put into the Built In Self test (BIST) architecture and they are compared with that of the conventional logic. It is definite that BIST which was implemented using reversible LFSR is better than the conventional one in terms of delay and area. The design has been done using Xilinx ISE design Suite 13.2. The circuits are simulated using Isim Simulator and the power is estimated using Xpower analyser.

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

Many of us have likely experienced the frustration of one's cell phone battery dying, or running low on battery power for your laptop when there is no plug-in available. Electronic devices have become portable, and are intended to be taken everywhere. The problem is that there is not always a source of electricity available, and so the demand for devices that use less power, so that batteries last longer, is quickly growing.

In this paper a new algorithm named Position Oriented Test Generation (POTG) is proposed which would not only detect whether the chip is faulty or not but, also provide the information regarding the position and the type of fault present. A modified fault dictionary is prepared that is used to minimize the effort in fault location. The proposed algorithm has two parts: first, generation of optimized fault dictionary, and then usage of this fault dictionary. This modified dictionary also gives a heuristic approach to minimize the number of test vectors required for testing the chip with some trade-off with fault coverage. This proposed algorithm is faster in locating a fault in a chip compared to other classical fault location technique. For validation, POTG Algorithm has been applied to ISCAS’85 Benchmark circuit and results have been obtained.