MC33879
MC33879
MC33879
Features
• Designed to operate 5.5 V < VPWR < 27.5 V
EK SUFFIX (PB-FREE)
• 16-bit SPI for control and fault reporting, 3.3 V / 5.0 V compatible
98ARL10543D
• Outputs are current limited (0.6 to 1.2 A) to drive incandescent lamps 32-PIN SOICW
• Output voltage clamp, + 45 V (low-side) and - 20 V (high-side) during
inductive switching
• On/Off control of open load detect current (LED application) Applications
• Internal reverse battery protection on VPWR • Solenoids
• Loss of ground or supply will not energize loads or damage IC • Relays
• Maximum 5.0 μA IPWR standby current at 13 V VPWR • Actuators
• RDS(ON) of 0.75 Ω at 25 °C typical • Stepper motors
• Short-circuit detect and current limit with automatic retry • Brush DC motors
• Independent overtemperature protection • Incandescent lamps
VPWR VBAT
5.0 V
33879
VPWR D1
D2
VDD D3
D4 High-side Drive
S1
MCU S2
A0 EN S3
MOSI DI S4
SCLK SCLK M H-Bridge Configuration
CS CS D5 VBAT VBAT
MISO D0 D6
D7
PWM1 IN5 D8
PWM2 IN6 S5 Low-side Drive
S6
GND S7
S8
MC33879APEK
-40 to 125 °C 32 SOICW-EP
MC33879TEK
Notes
1. To order parts in Tape & Reel, add the R2 suffix to the part number.
EN Pull-down Current
EN = 5.0 V
I EN μA
• 333879 20 45 100
• 33879A 20 45 110
33879
2 NXP Semiconductors
2 Internal block diagram
VDD VPWR
~50 μA
__
CS Internal Overvoltage
Charge
Bias Shutdown/POR
SCLK Pump Sleep State
Power Supply
DI
DO GND
D5 Drain
TLIM Open D6 Outputs
Load
Detect
Gate Current
Drive ~80 μA
EP Exposed Pad Control
Current
Limit
+
‚ S5 Source
+ S6 Outputs
‚ + ‚
33879
NXP Semiconductors 3
3 Pin connections
GND 1 32 DO
VDD 2 31 VPWR
S8 3 30 NC
NC 4 29 S7
D8 5 28 D7
S2 6 27 S4
D2 7 26 D4
NC 8 GND 25 NC
NC 9 24 NC
S1 10 23 S3
D1 11 22 D3
D6 12 21 D5
S6 13 20 S5
IN6 14 19 IN5
EN 15 18 CS
SCLK 16 17 DI
33879
4 NXP Semiconductors
Table 3. 33879 pin definitions (continued)
Pin number Pin name Pin function Formal name Definition
33879
NXP Semiconductors 5
4 Electrical characteristics
Electrical ratings
(1)
VDD VDD Supply Voltage - 0.3 to 7.0 VDC
– CS, DI, DO, SCLK, IN5, IN6, and EN - 0.3 to 7.0 VDC (1)
Thermal ratings
Operating Temperature
TA • Ambient - 40 to 125
°C
TJ • Junction - 40 to 150
TC • Case - 40 to 125
TPPRT Peak Package Reflow Temperature During Reflow Note 6 °C (5), (6)
Notes
1. Exceeding these limits may cause malfunction or permanent damage to the device.
2. Maximum output clamp energy capability at 150°C junction temperature using single non-repetitive pulse method with I = 350 mA.
3. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in accordance
with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4. Maximum power dissipation at TA = 25 °C with no heatsink used.
5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause
malfunction or permanent damage to the device.
6. NXP’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and
Moisture Sensitivity Levels (MSL), Go to www.NXP.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
33879
6 NXP Semiconductors
4.2 Static electrical characteristics
Power input
Supply Voltage Range
VPWR (FO) • Fully Operational 33879 5.5 – 26.5 V
• 33879A 5.5 – 27.5
IPWR (ON) Supply Current – 14 24 mA
Sleep State Supply Current
IPWR (SS) – 2.0 5.0 μA
• VDD or EN ≤ 0.8 V, VPWR = 13 V
Power output
Drain-to-Source ON Resistance (IOUT = 0.350 A, VPWR = 13 V)
• TJ = 125°C – – 1.4
RDS (on) Ω
TJ = 25°C – 0.75 –
TJ = -40°C – – –
IOUT (LIM) Output Self Limiting Current High-side and Low-side Configurations 0.6 – 1.2 A
Output Fault Detection Voltage Threshold Outputs Programmed OFF
(7)
VOUT(FLT-TH) • 33879 2.5 4.0 4.5 V
• 33879A 2.5 4.0 5.0
Output Fault Detection Current @ Threshold, High-side Configuration
Outputs Programmed OFF
IOUT(FLT-TH) μA
• 33879 35 55 90
• 33879A 35 55 150
Output Fault Detection Current @ Threshold, Low-side Configuration
Outputs Programmed OFF
IOUT(FLT-TH) μA
• 33879 20 30 60
• 33879A 20 30 115
Output OFF Open Load Detection Current, High-side Configuration
• VDRAIN = 16 V, VSOURCE = 0 V, Outputs Programmed OFF,
IOCO VPWR = 16 V μA
33879 65 100 160
33879A 60 100 190
Notes
7. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.
33879
NXP Semiconductors 7
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol Characteristic Min. Typ. Max. Unit Notes
CS Pull-up Current
ICS -30 – -100 μA
• CS = 0 V
CS Leakage Current to VDD
ICS(LKG) – – 10 μA
• CS = 5.0 V, VDD = 0 V
Notes
8. This parameter is guaranteed by design; however, it is not production tested.
9. Upper and lower logic threshold voltage levels apply to DI, CS, SCLK, IN5, IN6, and EN.
33879
8 NXP Semiconductors
Table 5. Static electrical characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ VDD ≤ 5.5 V, 5.5 V ≤ VPWR ≤ 18 V, - 40 °C ≤ TC ≤ 125 °C, unless otherwise noted. Where
applicable, typical values reflect the parameter’s approximate average value with VPWR = 13 V, TA = 25 °C.
Symbol Characteristic Min. Typ. Max. Unit Notes
Notes
10. This parameter is guaranteed by design; however, it is not production tested.
33879
NXP Semiconductors 9
4.3 Dynamic electrical characteristics
t LEAD Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) 100 – – ns
(16)
t DO (EN) Time from Falling Edge of CS to DO Low-impedance – – 55 ns
(17)
t DO (DIS) Time from Rising Edge of CS to DO High-impedance – – 55 ns
(18)
t VALID Time from Rising Edge of SCLK to DO Data Valid – 25 55 ns
Notes
11. Output slew rate respectively measured across a 620 Ω resistive load at 10 to 90 percent and 90 to 10 percent voltage points.
CL capacitor is connected from Drain or Source output to Ground.
12. Output turn ON and OFF delay time measured from 50 percent rising edge of CS to the beginning of the 10 and 90 percent transition points.
13. Duration of fault before fault bit is set. Duration between access times must be greater than 300 μs to read faults.
14. This parameter is guaranteed by design. Production test equipment uses 4.16 MHz, 5.5 V/3.1 V SPI interface.
15. Rise and Fall time of incoming DI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
16. Time required for output status data to be available for use at DO pin.
17. Time required for output status data to be terminated at DO pin.
18. Time required to obtain valid data out from DO following the rise of SCLK.
33879
10 NXP Semiconductors
4.4 Timing diagrams
CS 0.2 VDD
tLEAD tLAG
0.7 VDD
SCLK
0.2 VDD
tDI(SU) tDI(HOLD)
0.7 VDD
DI 0.2 VDD
MSB in
tDO(EN) tDO(DIS)
tVALID
0.7 VDD
DO 0.2 VDD
MSB out LSB out
VDD = 5.0 V
33879
SCLK Under DO
Test
CL = 200 pF
Figure 5. Valid data delay time and valid time test circuit
VOH
0.7 VDD
DO 0.2 VDD
VOL
(Low-to-High) tR(DO
DO tVALID
VOH
(High-to-Low) 0.7 VDD
0.2
VOL
33879
NXP Semiconductors 11
tF(CS) tR(CS)
< 50 ns < 50 ns
3.3/5.0 V
CS 90% 0.7 VDD
0.2 VDD 10%
0V
tDO(EN) tDO(DIS)
DO VTri-State
(Tri-State to Low) 90%
10% VOL
tDO(EN) tDO(DIS)
VOH
90%
DO VTri-State
10%
(Tri-State to High)
Figure 7. Enable and disable time waveforms
20
VPWR @ 18 V
IPWR Current into VPWR Pin (mA)
19
33879
18
17
16
33879A
15
14
7
VPWR @ 13 V
IPWR Current into VPWR Pin (µA
4
3
2
1
33879
12 NXP Semiconductors
140
TA = 25ℜ°
100
33879
80
60
40
20
33879A
0 5 10 15 20 25
VPWR
Figure 10. Sleep state IPWR vs. VPWR
1.4 VPWR @ 13 V
High-side Drive
1.2
1.0
RDS(ON) (Ω)
0.8
0.6
0.4
-40 -25 0
25 50 75 100 125
TA, Ambient Temperature (ℜ°C
Figure 11. RDS(ON) vs. temperature at 350 mA
1.4 TA = 25ℜ°
High-side Drive
1.2
1.0
RDS(ON) (Ω)
0.8
0.6
0.4
0.2
0 5 10 15 20 25
VPWR (V)
Figure 12. RDS(ON) vs. VPWR at 350 mA
33879
NXP Semiconductors 13
140
VPWR @ 13 V
120
80
60
High-side
40 Low-side
20
5.5 VPWR @ 13 V
High-side and Low-side
5.0
4.5
4.0
3.5
3.0
2.5
33879
14 NXP Semiconductors
5 Functional description
5.1.1 CS pin
The system MCU selects the 33879 with which to communicate through the use of the chip select CS pin. Logic low on CS enables the
data output (DO) driver and allows data to be transferred from the MCU to the 33879 and vice versa. Data clocked into the 33879 is acted
upon on the rising edge of CS. To avoid any spurious data, it is essential the high-to-low transition of the CS signal occur only when the
SPI clock (SCLK) is in a logic low state.
5.1.3 DI pin
The DI pin is used for serial instruction data input. DI information is latched into the input register on the falling edge of SCLK. A logic high
state present on DI programs a specific output on. The specific output turns on with the rising edge of the CS signal. Conversely, a logic
low state present on the DI pin programs the output off. The specific output turns off with the rising edge of the CS signal. To program the
eight outputs and open load detection current on or off, send the DI data beginning with the open load detection current bits, followed by
output eight, output seven, and so on to output one. For each falling edge of the SCLK while CS is logic low, a data bit instruction (on or
off) is loaded into the shift register per the data bit DI state. Sixteen bits of entered information is required to fill the input shift register.
5.1.4 DO pin
The DO pin is the output from the shift register. The DO pin remains tri-state until the CS pin is in a logic low state. All faults on the 33879
device are reported as logic [1] through the DO data pin. Regardless of the configuration of the driver, open loads and shorted loads are
reported as logic [1]. Conversely, normal operating outputs with non-faulted loads are reported as logic [0]. Outputs programmed with
open load detection current disabled report logic [0] in the off state. The first eight positive transitions of SCLK report logic [0] followed by
the status of the eight output drivers. The DI / DO shifting of data follows a first-in, first-out protocol with both input and output words
transferring the most significant bit (MSB) first.
5.1.5 EN pin
The EN pin on the 33879 enables the device. With the EN pin high, output drivers may be activated and open / short fault detection
performed and reported. With the EN pin low, all outputs become inactive, open load detection current is disabled, and the device enters
Sleep mode. The 33879 performs Power-ON Reset on the rising edge of the enable signal.
33879
NXP Semiconductors 15
5.1.7 VDD pin
The VDD input pin is used to determine logic levels on the microprocessor interface (SPI) pins. Current from VDD is used to drive the DO
output and the pull-up current for CS. VDD must be applied for normal mode operation. The 33879 device performs Power-ON Reset with
the application of VDD.
5.2.1 Introduction
The 33879 is an eight output hardware-configurable power switch with 16-bit serial control. A simplified internal block diagram of the 33879
is shown in Figure 2. The 33879 device uses high-efficiency up-drain power DMOS output transistors exhibiting low drain-to-source ON
resistance (RDS(on) = 0.75 Ω at 25 °C typical) and dense CMOS control logic. All outputs have independent voltage clamps to provide fast
inductive turn-off and transient protection.
In operation, the 33879 functions as an eight output serial switch, serving as an MCU bus expander and buffer with fault management
and fault reporting features. In doing so, the device directly relieves the MCU of the fault management functions. This device directly
interfaces to an MCU using a SPI for control and diagnostic readout. Figure 15 illustrates the basic SPI configuration between an MCU
and one 33879.
33879
16 NXP Semiconductors
MC68HCxx
Microcontroller 33879
MOSI DI
SCLK
Receive To
Buffer Logic
Parallel CS
Ports
SCLK
Parallel Port
33879 33879 33879
MOSI
33879
NXP Semiconductors 17
33879
MOSI DI
SCLK
SCLK
MISO 8 Outputs
DO
CS
MC68HCxx
Microcontroller
with 33879
SPI Interface
DI
SCLK
DO 8 Outputs
CS
33879
A DI
Parallel B SCLK
Ports
C DO 8 Outputs
CS
33879
18 NXP Semiconductors
Table 9. Fault operation
Serial output (DO) pin reports
Overtemperature Fault reported by serial output (DO) pin.
Overcurrent DO pin reports short to battery/supply or overcurrent condition.
Output ON Open Load Fault Not reported.
DO pin reports output OFF open load condition only with Open Load Detection Current enabled.
Output OFF Open Load Fault
DO pin will report “0” for Output OFF Open Load Fault with Open Load Detection Current disabled.
Device shutdowns
Total device shutdown at VPWR = VPWR(OV) V. Resumes normal operation with proper voltage. All outputs assuming
Overvoltage
the previous state upon recovery from overvoltage.
Only the output experiencing an overtemperature shuts down. Output assumes previous state upon recovery from
Overtemperature
overtemperature.
33879
NXP Semiconductors 19
5.4.4 SPI integrity check
Checking the integrity of the SPI communication with the initial power-up of the VDD and EN pins is recommended. After initial system
start-up or reset, the MCU writes one 32-bit pattern to the 33879. The first 16 bits read by the MCU are 8 logic [0]s followed by the fault
status of the outputs. The second 16 bits are the same bit pattern sent by the MCU. By the MCU receiving the same bit pattern it sent,
bus integrity is confirmed. Note the second 16-bit pattern the MCU sends to the device is the command word and is transferred to the
outputs with rising edge of CS. Important: A SCLK pulse count strategy has been implemented to ensure integrity of SPI communications.
SPI messages consisting of 16 SCLK pulses and multiples of 8 clock pulses thereafter are acknowledged. SPI messages consisting of
other than 16 + multiples of 8 SCLK pulses are ignored by the device.
33879
20 NXP Semiconductors
5.4.10 Output voltage clamp
Each output of the 33879 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. Each
clamp independently limits the drain-to-source voltage to 45 V for low-side drive configurations and -20 V for high-side drive
configurations. The total energy clamped (E J) can be calculated by multiplying the current area under the current curve (I A) times the
clamp voltage (V CL) (see Figure 18). Characterization of the output clamps, using a single pulse non-repetitive method at 0.35 A, indicates
the maximum energy per output to be 50 mJ at 150°C junction temperature.
Drain-to-Source Clamp
Voltage (VCL = 45 V) Drain Voltage
Drain-to-Source ON
Voltage (VDS(ON)) Current
Area (I A)
GND Time
Drain-to-Source ON
Voltage (VDS(ON)) BAT
VS
GND Time
Current
Area (I A)
Clamp Energy
(E J = I A x V CL)
Source Current
(IS = 0.3 A)
Source Clamp Voltage Source Voltage
(V CL = -15 V)
33879
NXP Semiconductors 21
6 Package dimensions
Important: For the most current revision of the package, visit www.nxp.com and perform a keyword search using the “98ARL10543D”
drawing number listed below. Dimensions shown are provided for reference ONLY.
33879
22 NXP Semiconductors
33879
NXP Semiconductors 23
33879
24 NXP Semiconductors
7 Revision history
• Page 2, Figure 1; An exposed pad internal block and EP pin have been added to the internal block diagram.
• Page 4, Table 1; Table 1 has been updated to reflect the Exposed pad pin and pin definition.
• Page 6, Table 3; Logic Supply Sleep State Hysteresis and Note 7 have been removed. The VDD Supply contains
no hysteresis.
• Page 7, Table 3; Output Fault Detection Current @ Threshold, High-Side Configuration Max parameter has been
increased from 70uA to 90uA.
• Page 7, Table 3; Output OFF Open Load Detection Current, High-Side Configuration has been updated to reflect
5.0 2/2006 the voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output OFF Open Load Detection Current, Low-Side Configuration has been updated to reflect the
voltage of the VPWR pin during the parameter test.
• Page 7, Table 3; Output Leakage Current High-Side and Low-Side Configuration Max parameter has been
decreased from 7uA to 5uA.
• Page 15, Functional Pin Description; A description has been added for the Exposed Pad pin.
• Page 1, Device isometric; Corrected orientation of IC pin 1 from top left to bottom right.
• ALL Pages; Updated Data Sheet to reflect Freescale formatting.
• Added 33879A version
• Added MCZ33879EK/R2 and MCZ33879AEK/R2 to the Ordering Information
• Added Device variations on page 2
• Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Rations on
6.0 6/2007
page 6. Added note with instructions from www.freescale.com.
• Changed Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Renumbered X axis on Figure 14 - Open load detection threshold vs. temperature on page 14
• Changed Overvoltage on page 19 and Overvoltage fault on page 20
7.0 8/2008 • Updated package drawing.
• Updated data sheet status from Advance Information to Technical Data
8.0 10/2009
• Updated to the current Freescale form and style
• Removed MC33879EK from the ordering information
• Removed MCZ33879AEK and added MC33879APEK to the ordering information
• Removed MCZ33879EK and added MC33879TEK to the ordering information
• Updated Output Fault Detection Current @ Threshold, High-side Configuration Outputs Programmed OFF on page 7
9.0 5/2012
• Updated Output OFF Open Load Detection Current, High-side Configuration on page 7
• Updated Output OFF Open Load Detection Current, Low-side Configuration on page 8
• Updated EN Pull-down Current, EN = 5.0 V on page 8
• Updated the Freescale form and style
• Updated Output Fault Detection Voltage Threshold Outputs Programmed OFF on page 7
• Updated Output Fault Detection Current @ Threshold, Low-side Configuration Outputs Programmed OFF on page 7
6/2012
10.0 • Updated the max limit for Output Fault Detection Current @ Threshold, High-side Configuration Outputs
Programmed OFF on page 7
4/2013 • No technical changes. Revised back page. Updated document properties.
• Changed feature on page 1 to Designed to operate 5.5 V < VPWR < 27.5 V
11/2015
11.0 • Updated Freescale form and style.
7/2016 • Updated to NXP document form and style
33879
NXP Semiconductors 25
How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products.
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
Home Page:
NXP.com based on the information in this document. NXP reserves the right to make changes without further notice to any
http://www.nxp.com/terms-of-use.html.
NXP, the NXP logo, Freescale, the Freescale logo and SMARTMOS are trademarks of NXP B.V. All other product or
service names are the property of their respective owners. All rights reserved.