BJ8P64N

8-Bit Microcontroller
with OTP ROM

Product Specification
VER 1.0

March 12, 2010

3/12/2010 REV1.0 1/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

1 General Description

The BJ8P64N is an 8-bit microprocessor designed and developed with low-power and high-speed
CMOS technology. The device has an on-chip 2K*14-bit Electrical One Time Programmable Read
Only Memory (OTP-ROM). It provides a protection bit to prevent intrusion of user’s code. Three
Code option words are also available to meet user’s requirements.

With its enhanced OTP-ROM feature, the BJ8P64N provides a convenient way of developing and
verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective
program updates, using development and programming tools. User can avail of the BJX Writer to
easily program his development code.

2 Features

„ CPU configuration TCCC) and 16-bit real time

z 2K*14 bits on-chip ROM clock/counter (TCCB) with selective
z 80*8 bits on-chip registers (SRAM) signal sources, trigger edges, and
z 8-level stacks for subroutine nesting overflow interrupt
z Less than 1.9 mA at 5V/4MHz z 4-bit channel Analog-to-Digital
z Typically 15uA, at 3V/32kHz Converter with 12-bit resolution in Vref
z Typically 1 uA, during Sleep mode mode
„ I/O port configuration z Easily implemented IR (Infrared
z 3 bidirectional I/O ports : P5, P6, P7 remote control) application circuit
z 17 I/O pins z One pair of comparators or OP
z Wake-up port : P5 „ Six available interrupts:
z 8 Programmable pull-down I/O pins z TCC, TCCA, TCCB, TCCC overflow
z 8 programmable pull-high I/O pins interrupt
z 8 programmable open-drain I/O pins z Input-port status changed interrupt
z External interrupt : P60 (wake-up from sleep mode)
„ Operating voltage range z External interrupt
z Operating voltage:2.5V~5.5V z ADC completion interrupt
„ Operating temperature range z Comparators status change interrupt
z Operating temperature: -40ć ~85ć z IR/PWM interrupt
„ Operating frequency range „ Special features
z Crystal mode: z Programmable free running
DC~20MHz/2clks@5V,DC~100ns inst. watchdog timer(4.5ms : 18ms)
cycle@5V DC~8MHz/2clks @ 3V, z Power saving Sleep mode
DC~250ns inst. cycle @ 3V z Selectable Oscillation mode
z ERC mode: z Power-on voltage detector (2.0V +/-
DC~16MHz/2clks @ 5V, DC~125ns inst. 0.1V)
cycle @ 5V DC~8MHz/2clks @ 3V, „ Package type:
DC~250ns inst. cycle @ 3V z14-pin DIP 300mil : BJ8P64N-14D

z IRC mode: z14-pin SOP 150mil : BJ8P64N-14M

Oscillation mode : 4MHz, 8MHz, 1MHz, z16-pin DIP 300mil BJ8P64N-16D

455kHz z16-pin SOP 150mil : BJ8P64N-16M
„ Peripheral configuration z18-pin DIP 300mil : BJ8P64N-18D
z 8-bit real time clock/counter (TCC) with z18-pin SOP 300mil : BJ8P64N-18M
selective signal sources, trigger edges, and z20-pin DIP 300mil : BJ8P64N-20D
overflow interrupt z20-pin SOP 300mil : BJ8P64N-20M
z 8-bit real time clock/counter (TCCA,

3/12/2010 REV1.0 2/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

3 Pin Assignment

Fig 3-1 BJ8P64N-14D/14M Fig 3-2 BJ8P64-16D/16M

Fig 3-3 BJ8P64-18D/18M Fig 3-4 BJ8P64N-20D/20M

3/12/2010 REV1.0 3/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

4 Pin Description

4.1 BJ8P64N-14D/14M
Symbol Pin No. Type Function
General purpose input/output pin
P70 11 I/O
Default value after a power-on reset
General purpose input/output pin
P60, P61 6~9 I/O
P66, P67 Open-drain Function
Default value after a power-on reset
General purpose input/output pin
1~3 Pull-high/Pull-down Function
P50~P55 I/O
12~14 Default value after a power-on reset
Wake up from sleep mode when the status of the pin changes
Crystal type: Crystal input terminal or external clock input pin
OSCI 12 I
RC type: RC oscillator input pin
Crystal type: Crystal input terminal or external clock input pin. RC type:
OSCO 11 I/O clock output with a duration of one instruction cycle External clock signal
input
If set as /RESET and remains at logic low, the device will be reset
/RESET 4 I Voltage on /RESET/Vpp must not exceed Vdd during normal mode

External Counter input

TCC, 3, 7 I
TCCA TCC is defined by CONT <5> TCCA is
defined by IOC80 <1>
ADC0~ 1, 2, Analog to Digital Converter
I
ADC3 13, 14 Defined by ADCON (R9) <1:0>
IR mode output pin, capable of driving and sinking current=20mA when
IR OUT 9 O the output voltage drops to 0.7Vdd and rise to0.3Vdd at Vdd=5V.
External reference voltage for ADC Defined by
VREF 3 I
ADCON (R9) <7>
External interrupt pin triggered by a falling or rising edge
/INT 6 I
Defined by CONT <7>
VDD 10 – Power supply
VSS 5 – Ground

3/12/2010 REV1.0 4/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

4.2 BJ8P64-16D/16M
Symbol Pin No. Type Function
General purpose input/output pin
P70 13 I/O
Default value after a power-on reset
General purpose input/output pin
P60~P61, 6~11 I/O
P64~P67 Open-drain Function
Default value after a power-on reset
General purpose input/output pin
1~3 Pull-high/Pull-down Function
P50~P55 I/O
14~16 Default value after a power-on reset
Wake up from sleep mode when the status of the pin changes
“-“ : the input pin of Vin- of the comparator
CIN-, CIN+ 10, 9 IO “+” : the input pin of Vin+ of the comparator
CO 8 Pin CO is the comparator output
Defined by IOC80 <4:3>
Crystal type: Crystal input terminal or external clock input pin
OSCI 14 I
RC type: RC oscillator input pin
Crystal type: Crystal input terminal or external clock input pin. RC type:
OSCO 13 I/O clock output with a duration of one instruction cycle External clock signal
input
If set as /RESET and remains at logic low, the device will be reset
/RESET 4 I Voltage on /RESET/Vpp must not exceed Vdd during normal mode

External Counter input

TCC, 3, 7 I
TCCA TCC is defined by CONT <5> TCCA is
defined by IOC80 <1>
ADC0~ 1, 2, Analog to Digital Converter
I
ADC3 15, 16 Defined by ADCON (R9) <1:0>
IR mode output pin, capable of driving and sinking current=20mA when
IR OUT 11 O the output voltage drops to 0.7Vdd and rise to0.3Vdd at Vdd=5V.

External reference voltage for ADC Defined by

VREF 3 I
ADCON (R9) <7>
External interrupt pin triggered by a falling or rising edge
/INT 6 I
Defined by CONT <7>
VDD 12 – Power supply
VSS 5 – Ground

3/12/2010 REV1.0 5/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

4.3 BJ8P64N-18D/18M
Symbol Pin No. Type Function
General purpose input/output pin
P70 15 I/O
Default value after a power-on reset
General purpose input/output pin
P60~P67 6~13 I/O Open-drain Function
Default value after a power-on reset
General purpose input/output pin
1~3 Pull-high/Pull-down Function
P50~P55 I/O
16~18 Default value after a power-on reset
Wake up from sleep mode when the status of the pin changes
“-“ : the input pin of Vin- of the comparator
CIN-, CIN+ 12, 11 I/O “+” : the input pin of Vin+ of the comparator
CO 10 Pin CO is the comparator output
Defined by IOC80 <4:3>
Crystal type: Crystal input terminal or external clock input pin
OSCI 16 I
RC type: RC oscillator input pin
Crystal type: Crystal input terminal or external clock input pin. RC type:
OSCO 15 I/O clock output with a duration of one instruction cycle External clock signal
input
If set as /RESET and remains at logic low, the device will be reset
/RESET 4 I Voltage on /RESET/Vpp must not exceed Vdd during normal mode

External Counter input

TCC, TCC is defined by CONT <5> TCCA is
TCCA, 3, 7,
TCCB, I defined by IOC80 <1> TCCB is defined by
8, 9
TCCC IOC90 <5> TCCC is defined by IOC90 <1>
ADC0~ 1, 2, Analog to Digital Converter
I
ADC3 17, 18 Defined by ADCON (R9) <1:0>
IR mode output pin, capable of driving and sinking current=20mA when
IR OUT 13 O the output voltage drops to 0.7Vdd and rise to0.3Vdd at Vdd=5V.
External reference voltage for ADC Defined by
VREF 3 I
ADCON (R9) <7>
External interrupt pin triggered by a falling or rising edge
/INT 6 I
Defined by CONT <7>
VDD 14 – Power supply
VSS 5 – Ground

3/12/2010 REV1.0 6/7

Free Datasheet http://www.datasheet4u.com/

 BJ8P64N Specification

4.4 BJ8P64N-20D/20M
Symbol Pin No. Type Function
General purpose input/output pin
P70 16 I/O
Default value after a power-on reset
General purpose input/output pin
P60~P67 7~14 I/O Open-drain Function
Default value after a power-on reset
General purpose input/output pin
1~4 Pull-high/Pull-down Function
P50~P57 I/O
17~20 Default value after a power-on reset
Wake up from sleep mode when the status of the pin changes
“-“ : the input pin of Vin- of the comparator
CIN-, CIN+ 13, 12 IO “+” : the input pin of Vin+ of the comparator
CO 11 Pin CO is the comparator output
Defined by IOC80 <4:3>
Crystal type: Crystal input terminal or external clock input pin
OSCI 17 I
RC type: RC oscillator input pin
Crystal type: Crystal input terminal or external clock input pin. RC type:
OSCO 16 I/O clock output with a duration of one instruction cycle External clock signal
input
If set as /RESET and remains at logic low, the device will be reset
/RESET 5 I Voltage on /RESET/Vpp must not exceed Vdd during normal mode

External Timer/Counter input TCC is

TCC, defined by CONT <5> TCCA is defined by
TCCA, 4, 8,
TCCB, I IOC80 <1> TCCB is defined by IOC90 <5>
9, 10
TCCC TCCC is defined by IOC90 <1>
ADC0~ 2, 3, Analog to Digital Converter
I
ADC3 18, 19 Defined by ADCON (R9) <1:0>
IR mode output pin, capable of driving and sinking current=20mA when
IR OUT 14 O the output voltage drops to 0.7Vdd and rise to 0.3Vdd at Vdd=5V.
External reference voltage for ADC Defined by
VREF 4 I
ADCON (R9) <7>
External interrupt pin triggered by a falling or rising edge
/INT 7 I
Defined by CONT <7>
VDD 15 – Power supply
VSS 6 – Ground

3/12/2010 REV1.0 7/7

Free Datasheet http://www.datasheet4u.com/