GP214D

1.4GHz DUAL PLL

DESCRIPTION

The GP214D is a dual frequency synthesizer designed for RF operation up to 1.4GHz. The device
contains prescalers, programmable reference, and feedback frequency dividers, phase detectors, and
charge pumps necessary for the precision control of dual VCO loops. Data transfer is made via a simple
serial data interface. The GP214D is fabricated using advanced CMOS process and available in a 16-pin
TSSOP plastic package with 0.65mm pitch.

FEATURES
▪ Two systems for transmitter and receiver
▪ 2.4V to 5.0V operation (100MHz to 1.4GHz)
▪ Low current consumption
8.5mA @ 3.0V (Typ.)
▪ Modulus prescaler, 64 / 66
▪ Selectable charge pump current Pb
± 0.2mA, ± 0.4mA, ± 0.8mA, ± 1.6mA 16TSSOP

APPLICATIONS
▪ Portable wireless communications (PCS, cordless)
▪ Other wireless communication systems

BLOCK DIAGRAM

Version 1.2 (Jan. 2006)

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PIN DESCRIPTION

Pin No. Symbol Function Description I/O

1 Fin1 RF input, channel 1. I

Power supply. -
2, 15 Vcc
Two pins are connected each other.
Charge pump output, channel 1. Charge pump current is selected by the input O
3 CP1
serial data.
4, 13 GND Ground. Two pins are connected. -

5 LD Output of lock detection. It is the open drain output. O

6 CK Clock input.
7 DATA Serial data input. Serial data interface. I
8 EN Input of enable signal.
9 BO Output of buffer amplifier. The local signal passes through the buffer amplifier. O

10 OSCO Oscillator output. O

PLL reference input. I
11 OSCI
Typically connected to a TCXO output.
Switchover terminal to control time constant of loop filter. It is the open drain O
12 SW
output. When switched off, it’s normal output.
14 CP2 Charge pump output, channel 2. O

16 Fin2 RF input, channel 2. I

ABSOLUTE MAXIMUM RATINGS

Parameters Symbol Value Unit

Power supply voltage Vcc 5.5 V

Operating temperature TOPR -30 to +85 °C

Storage temperature TSTG -35 to +150 °C

ESD (Human body model) 2000 V

Note: This device is ESD sensitive. Appropriate ESD protection is required for device handling and assembly.

Version 1.2 (Jan. 2006)

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ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Vcc = 3.0V, Ta = 25°C)

Characteristic Symbol Test Condition Min. Typ. Max. Unit

Operating power supply

Vcc Fin1= Fin2= 200MHz~1.4GHz 2.4 3.0 5.0 V
voltage
Operating current Fin1= Fin2= 800MHz/ -5dBm
Icc 7.0 8.5 14.5 mA
consumption input
Standby current ISB Standby mode - 0 80 µA

Fin operating frequency Fin Fin1=Fin2= -5dBm 200 - 1400 MHz

Vcc = 2.4V -15 - 10

Fin1= Fin2=
Vcc = 3.0V -15 - 10
200~1200MHz
Vcc = 5.0V -15 - 10
Fin input sensitivity Fin dBm
Vcc = 2.4V -15 - 0
Fin1= Fin2=
Vcc = 3.0V -15 - 0
1200~1400MHz
Vcc = 5.0V -15 - 0

OSCI operating frequency FOSC VFin= 0dBm, sinewave 4 - 40 MHz

FOSC= 4~10MHz Vcc= 2.4~3.7V -10 0 10

OSCI input voltage VOSC dBm
FOSC= 10~40MHz Vcc= 2.4~5.0V -15 0 20

Serial data input high Vcc –

VIH Vcc= 1.7 to 5.0V Vcc - V
voltage (CK, DATA, EN) 0.2

Serial data input low

VIL Vcc= 1.7 to 5.0V - 0 0.2 V
voltage (CK, DATA, EN)

ICP1 CP1= 0, CP2= 0 (VCP= 1/2 Vcc) - 15% ± 1.6 + 15%

Charge pump output ICP2 CP1= 1, CP2= 0 (VCP= 1/2 Vcc) - 15% ± 0.2 + 15%
mA
current ICP3 CP1= 0, CP2= 1 (VCP= 1/2 Vcc) - 15% ± 0.4 +15%

ICP4 CP1= 1, CP2= 1 (VCP= 1/2 Vcc) - 15% ± 0.8 +15%

Charge pump leakage ICPL Standby mode (VCP= 1/2 Vcc) -1 - 1 µA

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PROGRAMMING DESCRIPTION

SERIAL DATA INPUT AND TIMING

The programmable functions are accessed through the MCU serial data interface. The interface includes
clock (CK, pin 6), data (DATA, pin 7) and enable signal (EN, pin 8). Serial data controls programmable
reference counter and programmable counters in channel 1 and channel 2. The serial data is clocked in
on the rising edge of clock and transferred into the shift register composed of 17-bit data field and 2-bit
control field. When EN is high, stored data is latched. Data is entered LSB first.

≥0.1us ≥0.2us
≥0.2us

CK
LSB MSB
≥0.2us
DATA N1(R1) N2(R2) N17(R12) GC2 GC1

≥0.1us ≥0.1us ≥0.2us

≥0.2us
EN

GROUP CODE AND LOCATION

The data stored in the shift register is loaded into one of four appropriate latches depending on the state
of group code (control bits) listed below.

Control Bits
Data Location
GC2(MSB-1) GC1(MSB)

0 0 Control Latch

1 0 Ch 1 N Latch

0 1 Ch 2 N Latch

1 1 OSC R Latch

Version 1.2 (Jan. 2006)

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OPTIONAL CONTROL
The control register enables various functions shown in the table below.

LSB Channel 1 Channel 2 MSB

Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14

T CP CP1 CP2 SB1 CP1 CP2 SB2 SBR LD1 LD2 SW GC2 GC1
Test Charge Charge Pump Ch 1 Charge Pump Ch2 Ref. Lock Filter Group Code
Mode Pump Output Current Standby Output Current Standby Divider Detector Switch “0”, “0”
Polarity Standby

▪ Test mode selection (T)

H: test mode, L: normal mode

▪ Output polarity of charge pump (CP)

CP is set to “0” at normal and changed to “1” when reverse operation, according to the dependence of
VCO output frequency upon VCO input voltage. “Normal” denotes proportional response in the frequency
to the VCO input voltage.

▪ Charge pump output current (CP1 and CP2)

Charge pump employs circuits characterized by constant output current. The output current can be
selected for the best performance.

Control Bits Charge Pump

Output Current
CP1 CP2

0 0 ±1600µA

0 1 ±200µA

1 0 ±400µA

1 1 ±800µA

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▪ Test mode and lock detector output (T, LD1 and LD2)

The LD state can be changed via controlling SB1, SB2, LD1 and LD2.

T SB1 SB2 LD1 LD2 LD Output State

0 0 low

0 1 channel2
0
1 0 channel1

1 1 channel 1 and channel2

0
0 0 low

0 1 high
1
1 0 channel1

1 1 channel1
0
0 0 low

0 1 channel2
0
1 0 high

1 1 channel2
1
0 0 low

0 1 high
1
1 0 high

1 1 high

0 0 low

0 1 pres2
1 0
1 0 fpll2

1 1 fref

0 0 div4
1
0 1 pres1
0 1
1 0 fpll1

1 1 fosc/2

1 1 × × low

0 0 × × low

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▪ Lock detector output

When the phase difference is detected, LD (pin 5) goes “L”. When locked or at standby, LD changes to H”.
In case where the time difference, “T” less than 2/fosc (T<2/fosc) continues for more than three cycles of
reference counter output, LD goes “H”.

Fosc: OSCI operating frequency (LOCAL OSC)

T: time difference of the pulse between reference divider output and channel divider output

Number of divisions by reference dividers

A=
fosc
2
B=
fosc

A
Reference
Divider Output
B
Channel
Divider Output

T
Charge pump
Output T<2/fosc

Lock Detector
Output

▪ Programmable standby mode (SB1, SB2 and SBR)

Standby mode is controlled by three control bits of SB1, SB2 and SBR. The standby control of channel 1
and channel 2 can be made by SB1 and SB2. The on/off of reference divider is controlled by SBR.

Control Bit Standby Mode Status

SB1 SB2 SBR CH1 CH2 REF Mode Status
0 0 0 ON ON ON Inter-locking
0 1 0 ON OFF ON CH1 locking
1 0 0 OFF ON ON CH2 locking
1 1 0 OFF OFF ON REF ON
1 1 1 OFF OFF OFF Standby

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▪ Filter switch control (SW)

SW terminal, for switching time constant of loop filter is controlled by “SW” bit. High lock mode and
normal lock mode can be arbitrarily selected by filter switch control (SW) with the charge pump output
current.

Control Bits
Mode
SW CP1 CP2
0 0 0
0 0 1
High Lock
0 1 0
0 1 1
1 0 0
1 0 1
Normal Lock
1 1 0
1 1 1

CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO)

Reference frequency input is made directly to OSCI (pin 11). Buffer output (BO, pin 9) can be used for the
2nd mixer input.

REFERENCE COUNTER

When the control bits (GC1, GC2) are “11”, data is transferred from shift register into the OSC R latch
which sets the divide ratio of 12-bit reference counter. The divide ratio is programmed using the bits as
shown in the table below.

LSB MSB
GC2 GC1
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12
“1” “1”

Reference Counter Group Code

Divide ratio: 2×R = 2×(3 to 4095) = 6 to 8190

Divide
R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1
Ratio
3 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 1 0 0
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
4095 1 1 1 1 1 1 1 1 1 1 1 1

Version 1.2 (Jan. 2006)

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PROGRAMMABLE N-COUNTER, CH1 AND CH2

These counters consist of the 5-bit swallow counter, the 12-bit programmable main counter, and two
modulus prescaler providing divisions of 64 and 66. The swallow counter and main counter enable to set
any of 192 to 262142 divisions.

LSB MSB
Swallow counter Main counter

N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19

N-Counter divide ratio, N

Group code
CH1, “10”
CH2, “01"

5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER)

Divide ratio: 0 to 31, B≥A

Divide
N5 N4 N3 N2 N1
Ratio (A)
0 0 0 0 0 0
1 0 0 0 0 1
・ ・ ・ ・ ・ ・
31 1 1 1 1 1

12-BIT MAIN COUNTER DIVIDE RATIO (B COUNTER)

Divide ratio: 3 to 4095

Divide
N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6
Ratio (B)
3 0 0 0 0 0 0 0 0 0 0 1 1
4 0 0 0 0 0 0 0 0 0 1 0 0
・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・
4095 1 1 1 1 1 1 1 1 1 1 1 1

Divide ratio of channel 1 and 2 = N

N = 2×(32×B+A), B≥A
Divide ratio: 192 to 262142

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TEST CIRCUIT

▪ Sensitivity measurement
- RF signal input is to be matched to 50Ohm and short line is recommended.
- R1 and R2 (51Ohm) are connected to GND.
- Tests at different bias and power levels are normally conducted.
- Turn on DC voltage and RF signal before the data programming.
- Frequency is monitored from TP1 (test point, 1) via frequency counter or oscilloscope.

▪ Charge pump current measurement

- VCP can be fixed to 1/2 VCC or varied from 0 to maximum VCC.
- Charge pump polarity is changed from normal to reverse.

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APPLICATION CIRCUIT

- R3~R6 & C1~C6: Loop filter components (depending on frequency, phase noise and lock time)
- SW turns on when R7 is connected.

PACKAGE DEMENSIONS

16-pin TSSOP

(Unit: Millimeters)

Version 1.2 (Jan. 2006)

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Version 1.2 (Jan. 2006)

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Version 1.2 (Jan. 2006)

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Version 1.2 (Jan. 2006)

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