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  • Tut 3 - FSM

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    Tay Koonle
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    The document contains 9 questions about designing finite state machines (FSMs) and sequential logic circuits. The questions cover topics such as creating state diagrams, state tables, and logic expressions for FSMs that recognize specific sequences of inputs or compare multi-bit numbers.

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    The document contains 9 questions about designing finite state machines (FSMs) and sequential logic circuits. The questions cover topics such as creating state diagrams, state tables, and logic expressions for FSMs that recognize specific sequences of inputs or compare multi-bit numbers.

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    35 views2 pages

    Tut 3 - FSM

    Uploaded by

    Tay Koonle
    The document contains 9 questions about designing finite state machines (FSMs) and sequential logic circuits. The questions cover topics such as creating state diagrams, state tables, and logic expressions for FSMs that recognize specific sequences of inputs or compare multi-bit numbers.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
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    of 2

    PSDC ENGINEERING DIPLOMA ASSESSMENT: TUTORIAL 3

    1. Create a state diagram for a sequence detector that outputs a 1 when it detects the final bit
    in the serial data stream 1101.

    2. Design a simple sequence detector for the sequence 011. Include three outputs that indicate how
    many bits have been received in the correct sequence. (For example, each output could be connected
    to an LED.)
    i. Draw a State Diagram (Moore) and then assign binary State Identifiers.
    ii. Make a Next State Truth Table

    3. Design a finite state machine that recognizes the particular pattern "111". The input to a finite state
    machine (FSM) is a sequence of binary bits in series. When the FSM sees three 1's in a row, it it
    should output "1" - otherwise it should output a "0".

    i. X= 011110010
    ii. Create a finite state machine that would reset and look for a new series of three 1's after it
    sees a "111" pattern.
    X= 011110111

    4. Draw a FSM state diagram (Mealy/Moore) to describe a serial comparator with n‐bit unsigned
    numbers x and y as inputs. The FSM takes two bits xi and yi at a time (every clock cycle). Assume
    the two bits are being fed in from MSB to LSB. E.g. xn‐1 and yn‐1 arrive at time unit 1 and xn‐2 and
    yn‐2 at time unit 2.
    The output of the FSM should be
    • 00 if the two values are equal
    • 10 if x has a larger value
    • 01 if y has a larger value
    You can assume that FSM has start state and can be reset to this state when new n‐bit inputs (x & y)
    need to be evaluated.

    5. Consider a sequence detector that receives a bit‐serial input X and asserts an output Z (i.e. Z = 1)
    when it detects a binary string 0110 in sequence of 0s and 1s. Use symbolic states with letters
    such as A, B, etc. You can also assume that ‘A’ is start state, in which the machine can start out
    or reset.
    i. Draw a Moore Machine state diagram for this sequence detector.
    ii. Draw a Mealy Machine state diagram for this sequence detector.

    6. Design a four-state (S1, S2, S3, S4) asynchronous FSM. The machine has two inputs, c (clear) and a
    (advance). The machine starts in S1. If a is 0, the machine remains in S1. If a is 1, it advances to, and
    remains in S2. Each time a change occurs, the machine advances, then remains in, the next state. The
    machine advances from S4 to S1. If, at any time, c is 1, the machine immediately transits to, and
    remains in S1. The machine has the following two-bit outputs, depending only on the current
    state:
    S1 = 00, S2 = 01, S3 = 11, S4 = 10.

    i. Is this a Mealy or Moore machine?


    ii. Draw the state diagram for the machine.
    iii. Show the state assignment.
    iv. Draw the state table, indicating the state names and assigned values.
    v. Find the expression using D/JK flip flops
    vi. draw the logic diagram

    7. A sequential network has two inputs (X1, X2) and one output (Z). The output remains a constant value
    unless one of the following input sequences occurs:

    a) The input sequence X1X2 = 00, 11 causes the output to become 0.


    b) The input sequence X1X2 = 01, 11 causes the output to become 1.
    c) The input sequence X1X2 = 10, 11 causes the output to change value.

    Derive a Mealy state table and state graph

    8. Make the state diagram that will output a ‘1’ when the sequence ‘000’ is detected in a serial stream of
    bits, D. For example, if the following binary stream is received:
    001010000100010011110001001
     Consider overlapping case

    9. Create the next state truth table and the output truth table for the state diagram below. Use the
    variable names S1 and S0 to represent the most significant and least significant bits respectively of
    the binary number identifying the state.

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