SEMICONDUCTOR TECHNICAL DATA


   


The MC14522B BCD counter and the MC14526B binary counter are
constructed with MOS P–channel and N–channel enhancement mode
devices in a monolithic structure.
These devices are presettable, cascadable, synchronous down counters L SUFFIX
with a decoded “0” state output for divide–by–N applications. In single stage CERAMIC
applications the “0” output is applied to the Preset Enable input. The CASE 620
Cascade Feedback input allows cascade divide–by–N operation with no
additional gates required. The Inhibit input allows disabling of the pulse
counting function. Inhibit may also be used as a negative edge clock. P SUFFIX
These complementary MOS counters can be used in frequency synthesiz- PLASTIC
ers, phase–locked loops, and other frequency division applications requiring CASE 648
low power dissipation and/or high noise immunity.
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
DW SUFFIX
• Logic Edge–Clocked Design — Incremented on Positive Transition of
SOIC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock or Negative Transition of Inhibit CASE 751G
• Asynchronous Preset Enable

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
• Capable of Driving Two Low–power TTL Loads or One Low–power ORDERING INFORMATION

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Schottky TTL Load Over the Rated Temperature Range MC14XXXBCP Plastic

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS) MC14XXXBCL Ceramic
MC14XXXBDW SOIC
Symbol Parameter Value Unit
TA = – 55° to 125°C for all packages.
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient), ± 10 mA PIN ASSIGNMENT
per Pin
PD Power Dissipation, per Package† 500 mW Q3 1 16 VDD

Tstg Storage Temperature – 65 to + 150 _C P3 2 15 Q2

TL Lead Temperature (8–Second Soldering) 260 _C PE 3 14 P2

* Maximum Ratings are those values beyond which damage to the device may occur. INHIBIT 4 13 CF
†Temperature Derating: P0 5 12 “0”
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C CLOCK 6 11 P1
FUNCTION TABLE Q0 7 10 RESET
Inputs Output VSS 8 9 Q1
Preset Cascade Resulting
Clock Reset Inhibit Enable Feedback “0” Function
X H X L L L Asynchronous reset*
X H X H L H Asynchronous reset This device contains protection circuitry to
X H X X H H Asynchronous reset guard against damage due to high static
voltages or electric fields. However, pre-
X L X H X L Asynchronous preset cautions must be taken to avoid applications of
L H L X L Decrement inhibited any voltage higher than maximum rated volt-
L L L X L Decrement inhibited ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained

H
L
L
L L
L
L
L
L
L
No change** (inactive edge)
No change** (inactive edge)
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an
L L L L L Decrement** appropriate logic voltage level (e.g., either VSS
H L L L L Decrement** or VDD). Unused outputs must be left open.
X = Don’t Care
NOTES:
* Output “0” is low when reset goes high only it PE and CF are low.
** Output “0” is high when reset is low, only if CF is high and count is 0000.

REV 3
1/94

MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14522B MC14526B
1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
VDD – 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.7 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (3.4 µA/kHz) f + IDD
Per Package) 15 IT = (5.1 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns (Figures 4, 5) 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time (Inhibit Used as Negative tPLH, ns
Edge Clock) tPHL
Clock or Inhibit to Q (Figures 4, 5, 6)
tPLH, tPHL = (1.7 ns/pF) CL + 465 ns 5.0 — 550 1100
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns 10 — 225 450
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns 15 — 160 320
Clock or Inhibit to “0”
tPLH, tPHL = (1.7 ns/pF) CL + 155 ns 5.0 — 240 480
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns 10 — 130 260
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 100 200

Propagation Delay Time tPLH, 5.0 — 260 520 ns

Pn to Q tPHL 10 — 120 240
(Figures 4, 7) 15 — 100 200
Propagation Delay Time tPHL 5.0 — 250 500 ns
Reset to Q 10 — 110 220
(Figure 8) 15 — 80 160
Propagation Delay Time tPHL, 5.0 — 220 440 ns
Preset Enable to “0” tPLH 10 — 100 200
(Figures 4, 9) 15 — 80 160
Clock or Inhibit Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figures 5, 6) 15 80 40 —
Clock Pulse Frequency (with PE = low) fmax 5.0 — 2.0 1.5 MHz
10 — 5.0 3.0
(Figures 4, 5, 6) 15 — 6.6 4.0
Clock or Inhibit Rise and Fall Time tr, 5.0 — — 15 µs
tf 10 — — 5
(Figures 5, 6) 15 — — 4
Setup Time tsu 5.0 90 40 — ns
Pn to Preset Enable 10 50 15 —
(Figure 10) 15 40 10 —
Hold Time th 5.0 30 – 15 — ns
Preset Enable to Pn 10 30 –5 —
(Figure 10) 15 30 0 —
Preset Enable Pulse Width tw 5.0 250 125 — ns
10 100 50 —
(Figure 10) 15 80 40 —
Reset Pulse Width tw 5.0 350 175 — ns
10 250 125 —
(Figure 8) 15 200 100 —
Reset Removal Time trem 5.0 10 – 110 — ns
10 20 – 30 —
(Figure 8) 15 30 – 20 —
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

3
 VOH VOL
VDD = –VGS VDD = VGS

CF Q0 CF Q0
PE PE
P0 Q1 P0 Q1
P1 P1
P2 Q2 P2 Q2
P3 IOH P3 IOL
RESET Q3 RESET Q3
INHIBIT INHIBIT
CLOCK “0” CLOCK “0”
EXTERNAL EXTERNAL
VSS VSS
POWER POWER
SUPPLY SUPPLY

Figure 1. Typical Output Source Figure 2. Typical Output Sink

Characteristics Test Circuit Characteristics Test Circuit

VDD

CF Q0
PE
P0 Q1
P1
P2 Q2
P3 CL
RESET Q3 TEST POINT
CL
INHIBIT CL
CLOCK “0” Q or “0”
CL DEVICE
VSS CL UNDER
TEST CL*

PULSE
GENERATOR 20 ns 20 ns
90% VDD
CLOCK 50%
10% VSS
VARIABLE
WIDTH 50% DUTY CYCLE * Includes all probe and jig capacitance.

Figure 3. Power Dissipation Figure 4. Test Circuit

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

4
 SWITCHING WAVEFORMS

tr tf tf tr
VDD VDD
90% 90%
CLOCK 50% INHIBIT 50%
10% VSS 10%
VSS
tw tw

1/fmax 1/fmax
tPLH tPHL tPLH tPHL

ANY Q 90% 90%

ANY Q
OR “0” 50% OR “0” 50%
10% 10%

tTLH tTHL tTLH tTHL

Figure 5. Figure 6.

tw
VDD
RESET 50%
VSS
tr tf
tPHL
VDD
90%
ANY P 50%
10% ANY Q 50%
VSS

tPLH tPHL
trem

ANY Q VDD
50%
CLOCK
50%
VSS

Figure 7. Figure 8.

VALID
tr tf VDD
VDD ANY P 50%
PRESET 90%
ENABLE 50% VSS
10% GND
tsu th
tPHL tPLH VDD
PRESET
ENABLE 50%
“0” 50% VSS

tw

Figure 9. Figure 10.

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

5
 PIN DESCRIPTIONS

Preset Enable (Pin 3) — If Reset is low, a high level on other than all zeroes, the “0” output is valid after the rising
the Preset Enable input asynchronously loads the counter edge of Preset Enable (when Cascade Feedback is high).
with the programmed values on P0, P1, P2, and P3. See the Function Table.
Inhibit (Pin 4) — A high level on the Inhibit input pre– Cascade Feedback (Pin 13) — If the Cascade Feedback
vents the Clock from decrementing the counter. With Clock input is high, a high level is generated at the “0” output when
(pin 6) held high, Inhibit may be used as a negative edge the count is all zeroes. If Cascade Feedback is low, the “0”
clock input. output depends on the Preset Enable input level. See the
Function Table.
Clock (Pin 6) — The counter decrements by one for each
rising edge of Clock. See the Function Table for level require- P0, P1, P2, P3 (Pins 5, 11, 14, 2) — These are the preset
ments on the other inputs. data inputs. P0 is the LSB.
Reset (Pin 10) — A high level on Reset asynchronously Q0, Q1, Q2, Q3 (Pins 7, 9, 15, 1) — These are the syn-
forces Q0, Q1, Q2, and Q3 low and, if Cascade Feedback is chronous counter outputs. Q0 is the LSB.
high, causes the “0” output to go high.
VSS (Pin 8) — The most negative power supply potential.
“0” (Pin 12) — The “0” (Zero) output issues a pulse one This pin is usually ground.
clock period wide when the counter reaches terminal count
(Q0 = Q1 = Q2 = Q3 = low) if Cascade Feedback is high and VDD (Pin 16) — The most positive power supply potential.
Preset Enable is low. When presetting the counter to a value VDD may range from 3 to 18 V with respect to VSS.

STATE DIAGRAMS

MC14522B MC14526B

0 1 2 3 4 0 1 2 3 4

15 5 15 5

14 6 14 6

13 7 13 7

12 11 10 9 8 12 11 10 9 8

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

6
 MC14522B LOGIC DIAGRAM (BCD Down Counter)

P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1

D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VSS

13
CF

3
PE
4
INHIBIT
12
“0”

CLOCK 6
10
RESET

MC14526B LOGIC DIAGRAM (Binary Down Counter)

P0 Q0 P1 Q1 P2 Q2 P3 Q3
5 7 11 9 14 15 2 1

D R D RQ D RQ D RQ
C C C C
T PE Q T PE Q T PE Q T PE Q
VDD VDD

13
CF

PE 3

INHIBIT 4

12
“0”

CLOCK 6
10
RESET

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

7
 APPLICATIONS INFORMATION

Divide–By–N, Single Stage The Inhibit pin may be used to stop pulse counting. When
this pin is taken high, decrementing is inhibited.

Figure 11 shows a single stage divide–by–N application. Cascaded, Presettable Divide–By–N

The MC14522B (BCD version) can accept a number greater
than 9 and count down in binary fashion. Hence, the BCD Figure 12 shows a three stage cascade application. Taking
Reset high loads N. Only the first stage’s Reset pin (least sig-
and binary single stage divide–by–N counters (as shown in
nificant counter) must be taken high to cause the preset for
Figure 11) function the same.
all stages, but all pins could be tied together, as shown.
To initialize counting a number, N is set on the parallel in-
When the first stage’s Reset pin goes high, the “0” output is
puts (P0, P1, P2, and P3) and reset is taken high asynchro-
latched in a high state. Reset must be released while Clock is
nously. A zero is forced into the master and slave of each bit
high and time allowed for Preset Enable to load N into all
and, at the same time, the “0” output goes high. Because stages before Clock goes low.
Preset Enable is tied to the “0” output, preset is enabled. Re- When Preset Enable is high and Clock is low, time must be
set must be released while the Clock is high so the slaves of allowed for the zero digits to propagate a Cascade Feedback
each bit may receive N before the Clock goes low. When the to the first non–zero stage. Worst case is from the most sig-
Clock goes low and Reset is low, the “0” output goes low (if nificant bit (M.S.B.) to the L.S.B., when the L.S.B. is equal to
P0 through P3 are unequal to zero). one (i.e. N = 1).
The counter downcounts with each rising edge of the After N is loaded, each stage counts down to zero with
Clock. When the counter reaches the zero state, an output each rising edge of Clock. When any stage reaches zero and
pulse occurs on “0” which presets N. The propagation delays the leading stages (more significant bits) are zero, the “0”
from the Clock’s rising and falling edges to the “0” output’s output goes high and feeds back to the preceding stage.
rising and falling edges are about equal, making the “0” out- When all stages are zero, the Preset Enable automatically
put pulse approximately equal to that of the Clock pulse. loads N while the Clock is high and the cycle is renewed.

P0 Q0
P1 Q1
N
P2 Q2
P3 Q3 BUFFER
VDD fin
CF
“0” N
RESET
VSS INHIBIT
fin CLOCK

PE

Figure 11. ÷ N Counter

LSB MSB
N0 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11

VDD
P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3 P0 P1 P2 P3 Q0 Q1 Q2 Q3
fin CLOCK CLOCK CLOCK
CF CF CF
INHIBIT INHIBIT INHIBIT
VSS RESET “0” PE VSS RESET “0” PE VSS RESET “0” PE
VDD

LOAD
N BUFFER
10 KΩ
fin
VSS N

Figure 12. 3 Stages Cascaded

MC14522B MC14526B MOTOROLA CMOS LOGIC DATA

8
 OUTLINE DIMENSIONS

L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
1 8 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
–T– C ––– 0.200 ––– 5.08
N K D 0.015 0.020 0.39 0.50
SEATING
PLANE E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
E M H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
F G J 16 PL
L 0.300 BSC 7.62 BSC
D 16 PL 0.25 (0.010) M T B S M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
0.25 (0.010) M T A S

P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

MOTOROLA CMOS LOGIC DATA MC14522B MC14526B

9
 OUTLINE DIMENSIONS

DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16 9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
–B– 8X P 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
0.010 (0.25) M B M
PROTRUSION.
1 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
J PROTRUSION. ALLOWABLE DAMBAR
16X D PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
0.010 (0.25) M T A S B S MATERIAL CONDITION.
F MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 10.15 10.45 0.400 0.411
R X 45 _ B 7.40 7.60 0.292 0.299
C 2.35 2.65 0.093 0.104
D 0.35 0.49 0.014 0.019
C F 0.50 0.90 0.020 0.035
–T– G 1.27 BSC 0.050 BSC
SEATING M J 0.25 0.32 0.010 0.012
14X G K PLANE K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 10.05 10.55 0.395 0.415
R 0.25 0.75 0.010 0.029

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
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*MC14522B/D*
MC14522B MC14526B ◊ MOTOROLA CMOS LOGIC DATA
MC14522B/D
10