SEMICONDUCTOR TECHNICAL DATA

 
#
  # ! !
$  # # ! L SUFFIX
CERAMIC
! $ &$"% ' # CASE 620

The MC14519B is constructed with MOS P–channel and N–channel

enhancement mode devices in a monolithic structure. These complementary P SUFFIX
MOS logic gates find primary use where low power dissipation and/or high PLASTIC
noise immunity is desired. CASE 648
This device provides three functions in one package; a 4–Bit AND/OR
Selector, a Quad 2–Channel Data Selector, or a Quad Exclusive NOR Gate.
• Diode Protection on All Inputs D SUFFIX
• Supply Voltage Range = 3.0 Vdc to 18 Vdc SOIC
CASE 751B
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range ORDERING INFORMATION
• Plug–in Replacement for CD4019 in Most Applications
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
LOGIC DIAGRAM
TA = – 55° to 125°C for all packages.
A 9
CONTROL
INPUTS
B 14 TRUTH TABLE
X0 6 10 Z0 Control Inputs Output
A B Zn
Y0 7
0 0 0
0 1 Yn
X1 4 11 Z1
1 0 Xn
Y1 5
1 1 xn ĥ Yn
DATA
INPUTS NOTE: Xn ĥYn means Xn
X2 2 12 Z2 (Exclusive–NOR) Yn

Y2 3

X3 15 13 Z3

Y3 1

VDD = PIN 16
VSS = PIN 8

REV 3
1/94

MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995 MC14519B
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit PIN ASSIGNMENT

VDD DC Supply Voltage – 0.5 to + 18.0 V Y3 1 16 VDD

Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V X2 2 15 X3

Iin, Iout Input or Output Current (DC or Transient), ± 10 mA Y2 3 14 B

per Pin X1 4 13 Z3
PD Power Dissipation, per Package† 500 mW Y1 5 12 Z2
Tstg Storage Temperature – 65 to + 150 _C X0 6 11 Z1
TL Lead Temperature (8–Second Soldering) 260 _C Y0 7 10 Z0

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* Maximum Ratings are those values beyond which damage to the device may occur. VSS 8 9 A
†Temperature Derating:

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Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

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Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

VDD
– 55_C 25_C 125_C
Characteristic Symbol Vdc Min Max Min Typ # Max Min Max Unit
Output Voltage “0” Level VOL 5.0 — 0.05 — 0 0.05 — 0.05 Vdc
Vin = VDD or 0 10 — 0.05 — 0 0.05 — 0.05
15 — 0.05 — 0 0.05 — 0.05
“1” Level VOH 5.0 4.95 — 4.95 5.0 — 4.95 — Vdc
Vin = 0 or VDD 10 9.95 — 9.95 10 — 9.95 —
15 14.95 — 14.95 15 — 14.95 —
Input Voltage “0” Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 — 1.5 — 2.25 1.5 — 1.5
(VO = 9.0 or 1.0 Vdc) 10 — 3.0 — 4.50 3.0 — 3.0
(VO = 13.5 or 1.5 Vdc) 15 — 4.0 — 6.75 4.0 — 4.0
“1” Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 — 3.5 2.75 — 3.5 —
(VO = 1.0 or 9.0 Vdc) 10 7.0 — 7.0 5.50 — 7.0 —
(VO = 1.5 or 13.5 Vdc) 15 11 — 11 8.25 — 11 —

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 – 3.0 — – 2.4 – 4.2 — – 1.7 —
(VOH = 4.6 Vdc) 5.0 – 0.64 — – 0.51 – 0.88 — – 0.36 —
(VOH = 9.5 Vdc) 10 – 1.6 — – 1.3 – 2.25 — – 0.9 —
(VOH = 13.5 Vdc) 15 – 4.2 — – 3.4 – 8.8 — – 2.4 —
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 — 0.51 0.88 — 0.36 — mAdc
(VOL = 0.5 Vdc) 10 1.6 — 1.3 2.25 — 0.9 —
(VOL = 1.5 Vdc) 15 4.2 — 3.4 8.8 — 2.4 —
Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc
Input Capacitance Cin — — — — 5.0 7.5 — — pF
(Vin = 0)
Quiescent Current IDD 5.0 — 5.0 — 0.005 5.0 — 150 µAdc
(Per Package) 10 — 10 — 0.010 10 — 300
15 — 20 — 0.015 20 — 600
Total Supply Current**† IT 5.0 IT = (1.2 µA/kHz) f + IDD µAdc
(Dynamic plus Quiescent, 10 IT = (2.4 µA/kHz) f + IDD
Per Package) 15 IT = (3.6 µA/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14519B MOTOROLA CMOS LOGIC DATA

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SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 — 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 — 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 — 40 80
Propagation Delay Time tPLH, ns
tPLH, tPHL = (1.7 ns/pF) CL + 165 ns tPHL 5.0 — 250 500
tPLH, tPHL = (0.66 ns/pF) CL + 82 10 — 115 225
tPLH, tPHL = (0.5 ns/pF) CL + 65 ns 15 — 90 165
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

+VDD

VDD
A Z0
PULSE Vin CL
GENERATOR B
X0 20 ns 20 ns
Y0 Z1 VDD
CL 90%
X1
Vin
Y1 10%
VSS
X2 Z2 50% DUTY CYCLE
CL
Y2
X3
Y3 Z3
VSS CL

ISS
500 µF

Figure 1. Dynamic Power Dissipation Test Circuit and Waveform

VDD
20 ns 20 ns
V VDD
PULSE A DD Z0 INPUT 90%
GENERATOR CL 50%
B
10% VSS
X0
Z1 tPHL tPLH
Y0
CL 90% VOH
X1
OUTPUTS 50%
Y1 OUTPUT 10%
Z2 VOL
X2
Y2 CL
tTHL tTLH
X3 tPLH tPHL
Y3 V Z3 VOH
SS CL OUTPUT 50%
VOL

Figure 2. Switching Time Test Circuit and Waveforms

MOTOROLA CMOS LOGIC DATA MC14519B

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 TYPICAL CIRCUIT APPLICATIONS

DATA REGISTER SELECTION COMPARISON

DATA A MC14015B DATA B

CLOCK A 4–BIT REGISTER A DUAL 4–BIT REGISTER 4–BIT REGISTER B CLOCK B
RESET A Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RESET B

X0 X1 X2 X3 Y0 Y1 Y2 Y3
CONTROL A A MC14519B
AND/OR SELECT/EXCL NOR
CONTROL B B Z0 Z1 Z2 Z3

INVERT

MC14070B
QUAD
EXCLUSIVE OR

Q0 Q1 Q2 Q3

CONVERSION TABLE
Operation Code Output
A B INV Q0 Q1 Q2 Q3 Function
0 0 0 0 0 0 0 Inhibit, all zeros
0 0 1 1 1 1 1 Inhibit, all ones
1 0 0 X0 X1 X2 X3 Control A
1 0 1 X0 X1 X2 X3 Control A and Invert
0 1 0 Y0 Y1 Y2 Y3 Control B
0 1 1 Y0 Y1 Y2 Y3 Control B and Invert
1 1 0 X0 ĥ Y0 X1 ĥ Y1 X2 ĥ Y2 X3 ĥ Y3 Exclusive NOR
1 1 1 X0 ę Y0 X1 ę Y1 X2 ę Y2 X3 ę Y3 Exclusive OR

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.

MC14519B MOTOROLA CMOS LOGIC DATA

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 OUTLINE DIMENSIONS

L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
16 9
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
–B– FORMED PARALLEL.
1 8 4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
C L BODY.

INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.93
B 0.240 0.295 6.10 7.49
–T– C ––– 0.200 ––– 5.08
N K D 0.015 0.020 0.39 0.50
SEATING
PLANE E 0.050 BSC 1.27 BSC
F 0.055 0.065 1.40 1.65
G 0.100 BSC 2.54 BSC
E M H 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
F G J 16 PL
L 0.300 BSC 7.62 BSC
D 16 PL 0.25 (0.010) M T B S M 0_ 15 _ 0_ 15 _
N 0.020 0.040 0.51 1.01
0.25 (0.010) M T A S

P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
–A– 1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
–T– PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

MOTOROLA CMOS LOGIC DATA MC14519B

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 OUTLINE DIMENSIONS

D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J

–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16 9 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
–B– MOLD PROTRUSION.
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
1 8
0.25 (0.010) M B S PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
F A 9.80 10.00 0.386 0.393
K R X 45 _ B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
C F 0.40 1.25 0.016 0.049
–T– SEATING G 1.27 BSC 0.050 BSC
PLANE
M J J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
D 16 PL M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
0.25 (0.010) M T B S A S R 0.25 0.50 0.010 0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent
rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a
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Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
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*MC14519B/D*
MC14519B ◊ MOTOROLA CMOS LOGIC DATA
MC14519B/D
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