R5F364A6NFA Renesas

Datasheet
M16C/64A Group
R01DS0032EJ0200
RENESAS MCU Rev.2.00
Feb 07, 2011
1. Overview
1.1 Features
The M16C/64A Group microcomputer (MCU) incorporates the M16C/60 Series CPU core and flash
memory, employing sophisticated instructions for a high level of efficiency. This MCU has 1 MB of address
space (expandable to 4 MB), and it is capable of executing instructions at high speed. In addition, the
CPU core boasts a multiplier for high-speed operation processing.
This MCU consumes low power, and supports operating modes that allow additional power control. The
MCU also uses an anti-noise configuration to reduce emissions of electromagnetic noise and is designed
to withstand electromagnetic interference (EMI). By integrating many of the peripheral functions, including
the multifunction timer and serial interface, the number of system components has been reduced.
1.1.1 Applications
This MCU can be used in audio components, cameras, televisions, household appliances, office
equipment, communication devices, mobile devices, industrial equipment, and other applications.
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M16C/64A Group 1. Overview
1.2 Specifications
The M16C/64A Group includes 100-pin package. Table 1.1 and Table 1.2 list specifications.
Table 1.1 Specifications for the 100-Pin Package (1/2)

Item Function Description
M16C/60 Series core
(multiplier: 16 bit × 16 bit 32 bit,
multiply and accumulate instruction: 16 bit × 16 bit + 32 bit 32 bit)
CPU Central processing unit • Number of basic instructions: 91
• Minimum instruction execution time:
40.0 ns (f(BCLK) = 25 MHz, VCC1 = VCC2 = 2.7 to 5.5 V)
• Operating modes: Single-chip, memory expansion, and microprocessor
Memory ROM, RAM, data flash See Table 1.3 “Product List”.
• Power-on reset
Voltage
Detection
Voltage detector • 3 voltage detection points (detection level of voltage detection 0 and 1
selectable)
• 4 circuits: Main clock, sub clock, low-speed on-chip oscillator (125 kHz),
PLL frequency synthesizer
• Oscillation stop detection: Main clock oscillation stop/restart detection
Clock Clock generator function
• Frequency divider circuit: Divide ratio selectable from 1, 2, 4, 8, and 16
• Power saving features: Wait mode, stop mode
• Real-time clock
• Address space: 1 MB
• External bus interface: 0 to 3 waits inserted, 4 chip select outputs,
memory area expansion function (expandable to 4 MB), 3 V and 5 V
External Bus
Bus memory expansion interfaces
Expansion
• Bus format: Separate bus or multiplexed bus selectable, data bus width
selectable (8 or 16 bits), number of address buses selectable (12, 16, or
20)
• CMOS I/O ports: 85 (selectable pull-up resistors)
I/O Ports Programmable I/O ports
• N-channel open drain ports: 3
• Interrupt vectors: 70
Interrupts • External interrupt inputs: 13 (NMI, INT × 8, key input × 4)
• Interrupt priority levels: 7
15-bit timer × 1 (with prescaler)
Watchdog Timer
Automatic reset start function selectable
• 4 channels, cycle steal mode
DMA DMAC • Trigger sources: 43
• Transfer modes: 2 (single transfer, repeat transfer)
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Table 1.2 Specifications for the 100-Pin Package (2/2)

Item Function Description
16-bit timer × 5
Timer mode, event counter mode, one-shot timer mode, pulse width
modulation (PWM) mode
Timer A
Event counter two-phase pulse signal processing (two-phase encoder
input) × 3
Programmable output mode × 3
16-bit timer × 6
Timer B Timer mode, event counter mode, pulse period measurement mode,
pulse width measurement mode
Timers Three-phase motor control • Three-phase inverter control (timer A1, timer A2, timer A4, timer B2)
timer functions • On-chip dead time timer
Real-time clock Count: seconds, minutes, hours, days of the week
PWM function 8 bits × 2
• 2 circuits
• 4 wave pattern matchings (differentiate wave pattern for headers, data
Remote control signal receiver 0, data 1, and special data)
• 6-byte receive buffer (1 circuit only)
• Operating frequency of 32 kHz
Clock synchronous/asynchronous × 6 channels
UART0 to UART2, UART5 to
Serial I2C-bus, IEBus, special mode 2
UART7
Interface SIM (UART2)
SI/O3, SI/O4 Clock synchronization only × 2 channels
Multi-master I2C-bus Interface 1 channel
CEC transmit/receive, arbitration lost detection, ACK automatic output,
CEC Functions (2)
operation frequency of 32 kHz
10-bit resolution × 26 channels, including sample and hold function
A/D Converter
Conversion time: 1.72 µs
D/A Converter 8-bit resolution × 2 circuits
CRC-CCITT (X16 + X12 + X5 + 1),
CRC Calculator
CRC-16 (X16 + X15 + X2 + 1) compliant
• Program and erase power supply voltage: 2.7 to 5.5 V
Flash Memory
• Program and erase cycles: 1,000 times (program ROM 1, program
ROM 2), 10,000 times (data flash)
• Program security: ROM code protect, ID code check
Debug Functions On-chip debug, on-board flash rewrite, address match interrupt × 4
Operation Frequency/Supply Voltage 25 MHz/VCC1 = 2.7 to 5.5 V, VCC2 = 2.7 V to VCC1
Current Consumption Described in Electrical Characteristics
Operating Temperature -20°C to 85°C, -40°C to 85°C (1)
100-pin QFP: PRQP0100JD-B (Previous package code: 100P6F-A)
Package
100-pin LQFP: PLQP0100KB-A (Previous package code: 100P6Q-A)
Notes:
1. See Table 1.3 “Product List” for the operating temperature.
2. The CEC function indicates circuitry which supports the transmission and reception of CEC signals standardized
by the High-Definition Multimedia Interface (HDMI). HDMI and High-Definition Multimedia Interface are
registered trademarks of HDMI Licensing, LLC.
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1.3 Product List

Table 1.3 lists product information. Figure 1.1 shows the Part No., with Memory Size and Package, and
Figure 1.2 shows the Marking Diagram (Top View).
Table 1.3 Product List As of December 2010

ROM Capacity
RAM
Part No. Program Program Package Code Remarks
Data flash Capacity
ROM 1 ROM 2
R5F364A6NFA 128 KB 16 KB 4 KB 12 KB PRQP0100JD-B Operating
× 2 blocks temperature
R5F364A6NFB PLQP0100KB-A
-20°C to 85°C
R5F364A6DFA PRQP0100JD-B Operating
temperature
R5F364A6DFB PLQP0100KB-A
-40°C to 85°C
R5F364AENFA 256 KB 16 KB 4 KB 20 KB PRQP0100JD-B Operating
R5F364AENFB PLQP0100KB-A
-20°C to 85°C
R5F364AEDFA PRQP0100JD-B Operating
temperature
R5F364AEDFB PLQP0100KB-A
-40°C to 85°C
R5F364AKNFA 384 KB 16 KB 4 KB 31 KB PRQP0100JD-B Operating
R5F364AKNFB PLQP0100KB-A
-20°C to 85°C
R5F364AKDFA PRQP0100JD-B Operating
temperature
R5F364AKDFB PLQP0100KB-A
-40°C to 85°C
R5F364AMNFA 512 KB 16 KB 4 KB 31 KB PRQP0100JD-B Operating
R5F364AMNFB PLQP0100KB-A
-20°C to 85°C
R5F364AMDFA PRQP0100JD-B Operating
temperature
R5F364AMDFB PLQP0100KB-A
-40°C to 85°C
(D): Under development
(P): Planning
Previous package codes are as follows:

PRQP0100JD-B: 100P6F-A
PLQP0100KB-A: 100P6Q-A
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Part No. R 5 F 3 6 4 A 6 D FA
Package type
FA: Package PRQP0100JD-B (100P6F-A)
FB: Package PLQP0100KB-A (100P6Q-A)
Property code
N: Operating temperature: -20°C to 85°C
D: Operating temperature: -40°C to 85°C
Memory capacity
Program ROM 1/RAM
6: 128 KB/12 KB
E: 256 KB/20 KB
K: 384 KB/31KB
M: 512 KB/31 KB
M16C/64A Group (100 pins)

16-bit MCU
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1 Part No., with Memory Size and Package
M1 6 C
R 5 F 3 6 4 A6 DF A Type No. (See Figure 1.1 “Part No., with Memory Size and Package”)
XXXXXXX
Running No. 0 to 9, A to Z (except for I, O, Q)
Week code (from 01 to 54)
Last digit of year
Figure 1.2 Marking Diagram (Top View)
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1.4 Block Diagram

Figure 1.3 shows block diagram.
8 8 8 8 8 8
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5

VCC2 ports
Internal peripheral functions System clock generator

UART or
clock synchronous serial I/O
Timer (16 bit) (6 channels) XIN-XOUT
XCIN-XCOUT
Outputs (timer A): 5 PLL frequency synthesizer
Inputs (timer B): 6 Clock synchronous serial I/O
(8 bit x 2 channels)
On-chip oscillator (125 kHz)
Three-phase motor control Multi-master I2C-bus interface

circuit DMAC (4 channels)
(1 channel)
Real-time clock CRC calculator

CEC function
(CRC-CCITT or CRC-16)
PWM function (8 bit x 2)
Voltage detector
Remote control signal
receiver (2 circuits) Power-on reset
Watchdog timer On-chip debugger

(15 bit)
A/D converter M16C/60 Series CPU core Memory

(10-bit resolution x 26
channels) SB ROM (1)
R0H R0L
R1H R1L USP
D/A converter R2
(8-bit resolution x 2 R3 ISP RAM (2)
circuits) INTB
A0
A1 PC
FB FLG Multiplier
VCC1 ports
Port P10 Port P9 Port P8 Port P7 Port P6
8 8 8 8 8
Notes:
1. ROM size depends on MCU type.
2. RAM size depends on MCU type.
Figure 1.3 Block Diagram for the 100-Pin Package
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Feb 07, 2011
1.5 Pin Assignments

Figure 1.4 and Figure 1.5 show pin assignments. Table 1.4 and Table 1.5 list pin names.
See Note 3
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]

P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]

P2_7/AN2_7/A7, [A7/D7], [A7/D6]
P2_0/AN2_0/A0, [A0/D0], A0
P1_2/RXD6/SCL6/D10
P1_3/TXD6/SDA6/D11
P1_0/CTS6/RTS6/D8
P1_6/INT4/IDW/D14
P1_7/INT5/IDU/D15
P1_5/INT3/IDV/D13
P3_0/A8 [A8/D7]
P1_1/CLK6/D9
P1_4/D12
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P3_1/A9
VCC2
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P0_7/AN0_7/D7 81 50 P4_4/CTS7/RTS7/CS0
P0_6/AN0_6/D6 82 VCC2 ports 49 P4_5/CLK7/CS1
P0_5/AN0_5/D5 83 48 P4_6/PWM0/RXD7/SCL7/CS2
P0_4/AN0_4/D4 84 47 P4_7/PWM1/TXD7/SDA7/CS3
P0_3/AN0_3/D3 85 46 P5_0/WRL/WR
P0_2/AN0_2/D2
P0_1/AN0_1/D1
86
87
M16C/64A Group 45
44
P5_1/WRH/BHE
P5_2/RD
P0_0/AN0_0/D0 88 43 P5_3/BCLK
P10_7/AN7/KI3 89 42 P5_4/HLDA
P10_6/AN6/KI2
P10_5/AN5/KI1
90
91
PRQP0100JD-B 41
40
P5_5/HOLD
P5_6/ALE
P10_4/AN4/KI0
P10_3/AN3
92
93
(100P6F-A) 39
38
P5_7/RDY/CLKOUT
P6_0/RTCOUT/CTS0/RTS0
37 P6_1/CLK0
P10_2/AN2
P10_1/AN1
94
95 (Top view) 36 P6_2/RXD0/SCL0
AVSS 96 35 P6_3/TXD0/SDA0
P10_0/AN0 97 34 P6_4/CTS1/RTS1/CTS0/CLKS1
VREF 98 33 P6_5/CLK1
AVCC 99 VCC1 ports 32 P6_6/RXD1/SCL1
P9_7/ADTRG/SIN4 100 31 P6_7/TXD1/SDA1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
P8_5/NMI/SD/CEC (1)
P7_3/CTS2/RTS2/TA1IN/V
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
P9_6/ANEX1/SOUT4
BYTE
CNVSS
VSS
XIN
P8_7/XCIN
P8_6/XCOUT
RESET
XOUT
P9_5/ANEX0/CLK4
P9_4/DA1/TB4IN/PWM1
P9_3/DA0/TB3IN/PWM0
VCC1
P8_4/INT2/ZP
P9_1/TB1IN/PMC1/SIN3
P9_0/TB0IN/CLK3
P8_3/INT1
P8_2/INT0
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
P7_6/TA3OUT/TXD5/SDA5
P7_5/TA2IN/W
P9_2/TB2IN/PMC0/SOUT3
P7_4/TA2OUT/W
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal.
They should not be considered as two separate functional signals.
Figure 1.4 Pin Assignment for the 100-Pin Package
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See Note 3
P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]

P2_5/INT7/AN2_5/A5, [A5/D5], [A5/D4]
P2_1/AN2_1/A1, [A1/D1], [A1/D0]
P2_2/AN2_2/A2, [A2/D2], [A2/D1]
P2_3/AN2_3/A3, [A3/D3], [A3/D2]
P2_6/AN2_6/A6, [A6/D6], [A6/D5]

P2_7/AN2_7/A7, [A7/D7], [A7/D6]
P2_0/AN2_0/A0, [A0/D0], A0
P1_3/TXD6/SDA6/D11
P1_6/INT4/IDW/D14
P1_7/INT5/IDU/D15
P1_5/INT3/IDV/D13
P3_0/A8 [A8/D7]
P1_4/D12
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P3_1/A9
VCC2
VSS
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P1_2/RXD6/SCL6/D10 76 50 P4_2/A18
P1_1/CLK6/D9 77 49 P4_3/A19
P1_0/CTS6/RTS6/D8 78 VCC2 ports 48 P4_4/CTS7/RTS7/CS0
P0_7/AN0_7/D7 79 47 P4_5/CLK7/CS1
P0_6/AN0_6/D6 80 46 P4_6/PWM0/RXD7/SCL7/CS2
P0_5/AN0_5/D5 81 45 P4_7/PWM1/TXD7/SDA7/CS3
P0_4/AN0_4/D4 82 44 P5_0/WRL/WR
P0_3/AN0_3/D3 83 43 P5_1/WRH/BHE
P0_2/AN0_2/D2
P0_1/AN0_1/D1
84
85
M16C/64A Group 42
41
P5_2/RD
P5_3/BCLK
P0_0/AN0_0/D0 86 40 P5_4/HLDA
P10_7/AN7/KI3 87 39 P5_5/HOLD
P10_6/AN6/KI2
P10_5/AN5/KI1
88
89
PLQP0100KB-A 38
37
P5_6/ALE
P5_7/RDY/CLKOUT
P10_4/AN4/KI0
P10_3/AN3
90
91
(100P6Q-A) 36
35
P6_0/RTCOUT/CTS0/RTS0
P6_1/CLK0
P10_2/AN2
P10_1/AN1
92
93
(Top view) 34
33
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
AVSS 94 32 P6_4/CTS1/RTS1/CTS0/CLKS1
P10_0/AN0 95 31 P6_5/CLK1
VREF 96 30 P6_6/RXD1/SCL1
AVCC 97 29 P6_7/TXD1/SDA1
P9_7/ADTRG/SIN4 98 VCC1 ports 28 P7_0/TXD2/SDA2/SDAMM/TA0OUT (1)
P9_6/ANEX1/SOUT4 99 27 P7_1/RXD2/SCL2/SCLMM/TA0IN/TB5IN (1)
P9_5/ANEX0/CLK4 100 26 P7_2/CLK2/TA1OUT/V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
P9_4/DA1/TB4IN/PWM1
P9_3/DA0/TB3IN/PWM0
P9_1/TB1IN/PMC1/SIN3
P8_3/INT1
P8_2/INT0
P7_6/TA3OUT/TXD5/SDA5
P9_0/TB0IN/CLK3
VCC1
P9_2/TB2IN/PMC0/SOUT3
P8_1/TA4IN/U/CTS5/RTS5
P8_0/TA4OUT/U/RXD5/SCL5
P7_7/TA3IN/CLK5
BYTE
CNVSS
P8_7/XCIN
P7_3/CTS2/RTS2/TA1IN/V
VSS
XIN
P8_5/NMI/SD/CEC (1)
P8_4/INT2/ZP
P7_5/TA2IN/W
P8_6/XCOUT
RESET
P7_4/TA2OUT/W
XOUT
Notes:
1. N-channel open drain output.
2. Check the position of Pin 1 by referring to appendix 1, Package Dimensions.
3. Pin names in brackets [ ] represent a single functional signal.
They should not be considered as two separate functional signals.
Figure 1.5 Pin Assignment for the 100-Pin Package
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Table 1.4 Pin Names for the 100-Pin Package (1/2)

Pin No. I/O Pin for Peripheral Function
Bus Control
Control Pin Port A/D converter,
FA FB Interrupt Timer Serial interface Pin
D/A converter
1 99 P9_6 SOUT4 ANEX1
2 100 P9_5 CLK4 ANEX0
3 1 P9_4 TB4IN/PWM1 DA1
4 2 P9_3 TB3IN/PWM0 DA0
5 3 P9_2 TB2IN/PMC0 SOUT3
6 4 P9_1 TB1IN/PMC1 SIN3
7 5 P9_0 TB0IN CLK3
8 6 BYTE
9 7 CNVSS
10 8 XCIN P8_7
11 9 XCOUT P8_6
12 10 RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC1
17 15 P8_5 NMI SD CEC
18 16 P8_4 INT2 ZP
19 17 P8_3 INT1
20 18 P8_2 INT0
21 19 P8_1 TA4IN/U CTS5/RTS5
22 20 P8_0 TA4OUT/U RXD5/SCL5
23 21 P7_7 TA3IN CLK5
24 22 P7_6 TA3OUT TXD5/SDA5
25 23 P7_5 TA2IN/W
26 24 P7_4 TA2OUT/W
27 25 P7_3 TA1IN/V CTS2/RTS2
28 26 P7_2 TA1OUT/V CLK2
29 27 P7_1 TA0IN/TB5IN RXD2/SCL2/SCLMM
30 28 P7_0 TA0OUT TXD2/SDA2/SDAMM
31 29 P6_7 TXD1/SDA1
32 30 P6_6 RXD1/SCL1
33 31 P6_5 CLK1
CTS1/RTS1/CTS0
34 32 P6_4
/CLKS1
35 33 P6_3 TXD0/SDA0
36 34 P6_2 RXD0/SCL0
37 35 P6_1 CLK0
38 36 P6_0 RTCOUT CTS0/RTS0
39 37 CLKOUT P5_7 RDY
40 38 P5_6 ALE
41 39 P5_5 HOLD
42 40 P5_4 HLDA
43 41 P5_3 BCLK
44 42 P5_2 RD
45 43 P5_1 WRH/BHE
46 44 P5_0 WRL/WR
47 45 P4_7 PWM1 TXD7/SDA7 CS3
48 46 P4_6 PWM0 RXD7/SCL7 CS2
49 47 P4_5 CLK7 CS1
50 48 P4_4 CTS7/RTS7 CS0
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Table 1.5 Pin Names for the 100-Pin Package (2/2)

Pin No. I/O Pin for Peripheral Function
Control
Port A/D converter, Bus Control Pin
FA FB Pin Interrupt Timer Serial interface
D/A converter
51 49 P4_3 A19
52 50 P4_2 A18
53 51 P4_1 A17
54 52 P4_0 A16
55 53 P3_7 A15
56 54 P3_6 A14
57 55 P3_5 A13
58 56 P3_4 A12
59 57 P3_3 A11
60 58 P3_2 A10
61 59 P3_1 A9
62 60 VCC2
63 61 P3_0 A8, [A8/D7]
64 62 VSS
65 63 P2_7 AN2_7 A7, [A7/D7], [A7/D6]
66 64 P2_6 AN2_6 A6, [A6/D6], [A6/D5]
67 65 P2_5 INT7 AN2_5 A5, [A5/D5], [A5/D4]
68 66 P2_4 INT6 AN2_4 A4, [A4/D4], [A4/D3]
69 67 P2_3 AN2_3 A3, [A3/D3], [A3/D2]
70 68 P2_2 AN2_2 A2, [A2/D2], [A2/D1]
71 69 P2_1 AN2_1 A1, [A1/D1], [A1/D0]
72 70 P2_0 AN2_0 A0, [A0/D0], A0
73 71 P1_7 INT5 IDU D15
74 72 P1_6 INT4 IDW D14
75 73 P1_5 INT3 IDV D13
76 74 P1_4 D12
77 75 P1_3 TXD6/SDA6 D11
78 76 P1_2 RXD6/SCL6 D10
79 77 P1_1 CLK6 D9
80 78 P1_0 CTS6/RTS6 D8
81 79 P0_7 AN0_7 D7
82 80 P0_6 AN0_6 D6
83 81 P0_5 AN0_5 D5
84 82 P0_4 AN0_4 D4
85 83 P0_3 AN0_3 D3
86 84 P0_2 AN0_2 D2
87 85 P0_1 AN0_1 D1
88 86 P0_0 AN0_0 D0
89 87 P10_7 KI3 AN7
90 88 P10_6 KI2 AN6
91 89 P10_5 KI1 AN5
92 90 P10_4 KI0 AN4
93 91 P10_3 AN3
94 92 P10_2 AN2
95 93 P10_1 AN1
96 94 AVSS
97 95 P10_0 AN0
98 96 VREF
99 97 AVCC
100 98 P9_7 SIN4 ADTRG
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1.6 Pin Functions
Table 1.6 Pin Functions for the 100-Pin Package (1/3)

Signal Name Pin Name I/O Power Supply Description
Power supply VCC1, Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2)
I -
input VCC2, VSS and 0 V to the VSS pin.
This is the power supply for the A/D and D/A converters.
Analog power
AVCC, AVSS I VCC1 Connect the AVCC pin to VCC1, and connect the AVSS pin
supply input
to VSS.
Reset input RESET I VCC1 Driving this pin low resets the MCU.
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
CNVSS CNVSS I VCC1
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
Input pin to select the data bus of the external area. The data
External data bus bus is 16 bits when it is low, and 8 bits when it is high. This
BYTE I VCC1
width select input pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
Inputs or outputs data (D0 to D7) while accessing an
D0 to D7 I/O VCC2
external area with a separate bus.
Inputs or outputs data (D8 to D15) while accessing an
D8 to D15 I/O VCC2
external area with a 16-bit separate bus.
A0 to A19 O VCC2 Outputs address bits A0 to A19.
Inputs or outputs data (D0 to D7) and outputs address bits
A0/D0 to
I/O VCC2 (A0 to A7) by timesharing, while accessing an external area
A7/D7
with an 8-bit multiplexed bus.
Inputs or outputs data (D0 to D7) and outputs address bits
A1/D0 to
I/O VCC2 (A1 to A8) by timesharing, while accessing an external area
A8/D7
with a 16-bit multiplexed bus.
Outputs chip-select signals CS0 to CS3 to specify an
CS0 to CS3 O VCC2
external area.
Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and
WRH can be switched with BHE and WR.
Bus control pins • WRL, WRH, and RD selected
If the external data bus is 16 bits, data is written to an even
address in an external area when WRL is driven low. Data
WRL/WR
is written to an odd address when WRH is driven low. Data
WRH/BHE O VCC2
is read when RD is driven low.
RD
• WR, BHE, and RD selected
Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD when using an 8-bit external data bus.
ALE O VCC2 Outputs an ALE signal to latch the address.
HOLD input is unavailable. Connect the HOLD pin to VCC2
HOLD I VCC2
via a resistor (pull-up).
HLDA O VCC2 In a hold state, HLDA outputs a low-level signal.
The MCU bus is placed in a wait state while the RDY pin is
RDY I VCC2
driven low.
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
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Power
Signal Name Pin Name I/O Description
Supply
Main clock input XIN I VCC1 I/O for the main clock oscillator. Connect a ceramic resonator
or crystal between pins XIN and XOUT. (1) Input an external
Main clock output XOUT O VCC1 clock to XIN pin and leave XOUT pin open.
Sub clock input XCIN I VCC1 I/O for a sub clock oscillator. Connect a crystal between XCIN
pin and XCOUT pin. (1) Input an external clock to XCIN pin and
Sub clock output XCOUT O VCC1 leave XCOUT pin open.
BCLK output BCLK O VCC2 Outputs the BCLK signal.

Clock output CLKOUT O VCC2 Outputs a clock with the same frequency as fC, f1, f8, or f32.
INT0 to INT2 I VCC1
INT interrupt input Input for the INT interrupt.
INT3 to INT7 I VCC2
NMI interrupt input NMI I VCC1 Input for the NMI interrupt.
Key input interrupt
KI0 to KI3 I VCC1 Input for the key input interrupt.
input
TA0OUT to I/O for timers A0 to A4 (TA0OUT is N-channel open drain
I/O VCC1
TA4OUT output).
Timer A
TA0IN to TA4IN I VCC1 Input for timers A0 to A4.
ZP I VCC1 Input for Z-phase.
Timer B TB0IN to TB5IN I VCC1 Input for timers B0 to B5.
U, U, V, V, W, W O VCC1 Output for the three-phase motor control timer.
Three-phase motor
SD I VCC1 Forced cutoff input.
control timer
IDU, IDV, IDW I VCC2 Input for the position data.
Real-time clock output RTCOUT O VCC1 Output for the real-time clock.
VCC1,
PWM output PWM0, PWM1 O PWM output.
VCC2
Remote control signal
PMC0, PMC1 I VCC1 Input for the remote control signal receiver.
receiver input
CTS0 to CTS2,
I VCC1
CTS5 Input pins to control data transmission.
CTS6, CTS7 I VCC2
RTS0 to RTS2,
O VCC1
RTS5 Output pins to control data reception.
RTS6, RTS7 O VCC2
CLK0 to CLK2,
Serial interface I/O VCC1
CLK5 Transmit/receive clock I/O.
UART0 to UART2,
UART5 to UART7 CLK6, CLK7 I/O VCC2
RXD0 to RXD2,
I VCC1
RXD5 Serial data input.
RXD6, RXD7 I VCC2
TXD0 to TXD2,
O VCC1
TXD5 Serial data output. (2)
TXD6, TXD7 O VCC2
CLKS1 O VCC1 Output for the transmit/receive clock multiple-pin output function.
Notes:
1. Contact the manufacturer of crystal/ceramic resonator regarding the oscillation characteristics.
2. TXD2, SDA2, and SCL2 are N-channel open drain output pins. TXDi (i = 0, 1, 5 to 7), SDAi, and SCLi can be
selected as CMOS output pins or N-channel open drain output pins.
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Power
Signal Name Pin Name I/O Description
Supply
SDA0 to SDA2,
I/O VCC1
UART0 to SDA5 Serial data I/O.
UART2, SDA6, SDA7 I/O VCC2
UART5 to
UART7 SCL0 to SCL2,
I/O VCC1
I2C mode SCL5 Transmit/receive clock I/O.
SCL6, SCL7 I/O VCC2
Serial CLK3, CLK4 I/O VCC1 Transmit/receive clock I/O.

interface SIN3, SIN4 I VCC1 Serial data input.
SI/O3, SI/O4 SOUT3, SOUT4 O VCC1 Serial data output.
Multi-master SDAMM I/O VCC1 Serial data I/O (N-channel open drain output).
I2C-bus
interface SCLMM I/O VCC1 Transmit/receive clock I/O (N-channel open drain output).
CEC I/O CEC I/O VCC1 CEC I/O (N-channel open drain output).
Reference
VREF I VCC1 Reference voltage input for the A/D and D/A converters.
voltage input
AN0 to AN7 I VCC1
AN0_0 to AN0_7 Analog input.
A/D I VCC2
AN2_0 to AN2_7
converter
ADTRG I VCC1 External trigger input.
ANEX0, ANEX1 I VCC1 Extended analog input.
D/A
DA0, DA1 O VCC1 Output for the D/A converter.
converter
P0_0 to P0_7
P1_0 to P1_7 8-bit CMOS I/O ports. A direction register determines whether
P2_0 to P2_7 each pin is used as an input port or an output port. A pull-up
I/O VCC2
P3_0 to P3_7 resistor may be enabled or disabled for input ports in 4-bit
P4_0 to P4_7 units.
I/O ports P5_0 to P5_7
P6_0 to P6_7
8-bit I/O ports having equivalent functions to P0. However,
P7_0 to P7_7
P7_0, P7_1, and P8_5 are N-channel open drain output ports.
P8_0 to P8_7 I/O VCC1
No pull-up resistor is provided. P8_5 is an input port for
P9_0 to P9_7
verifying the NMI pin level and shares a pin with NMI.
P10_0 to P10_7
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M16C/64A Group 2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31 b15 b8 b7 b0
R2 R0H (upper bits of R0) R0L (lower bits of R0)
R3 R1H (upper bits of R1) R1L (lower bits of R1)

Data registers (1)
R2
R3
A0
Address registers (1)
A1
FB Frame base registers (1)
b19 b15 b0
INTBH INTBL Interrupt table register
INTBH is the 4 upper bits of the INTB register and INTBL

is the 16 lower bits.
b19 b0
PC Program counter
b15 b0
USP User stack pointer

ISP Interrupt stack pointer
SB Static base register
b15 b0
FLG Flag register
b15 b8 b7 b0
IPL U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1 CPU Registers
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2.1 Data Registers (R0, R1, R2, and R3)

R0, R1, R2, and R3 are 16-bit registers used for transfer, arithmetic, and logic operations. R0 and R1 can
be split into upper (R0H/R1H) and lower (R0L/R1L) bits to be used separately as 8-bit data registers.
R0 can be combined with R2, and R3 can be combined with R1 and be used as 32-bit data registers
R2R0 and R3R1, respectively.
2.2 Address Registers (A0 and A1)

A0 and A1 are 16-bit registers used for indirect addressing, relative addressing, transfer, arithmetic, and
logic operations. A0 can be combined with A1 and used as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)

FB is a 16-bit register that is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)

INTB is a 20-bit register that indicates the start address of a relocatable interrupt vector table.
2.5 Program Counter (PC)

The PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The USP and ISP stack pointers (SP) are each comprised of 16 bits. The U flag is used to switch between
USP and ISP.
2.7 Static Base Register (SB)

SB is a 16-bit register used for SB relative addressing.
2.8 Flag Register (FLG)

FLG is an 11-bit register that indicates the CPU state.
2.8.1 Carry Flag (C Flag)

The C flag retains a carry, borrow, or shift-out bit generated by the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)

The D flag is for debugging only. Set it to 0.
2.8.3 Zero Flag (Z Flag)

The Z flag becomes 1 when an arithmetic operation results in 0. Otherwise, it becomes 0.
2.8.4 Sign Flag (S Flag)

The S flag becomes 1 when an arithmetic operation results in a negative value. Otherwise, it becomes
0.
2.8.5 Register Bank Select Flag (B Flag)

Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is 1.
2.8.6 Overflow Flag (O Flag)

The O flag becomes 1 when an arithmetic operation results in an overflow. Otherwise, it becomes 0.
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Feb 07, 2011
2.8.7 Interrupt Enable Flag (I Flag)

The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)

IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10 Reserved Areas

Only set these bits to 0. The read value is undefined.
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M16C/64A Group 3. Address Space
3. Address Space
3.1 Address Space

The M16C/64A Group has a 1 MB address space from 00000h to FFFFFh. Address space is expandable to
4 MB with the memory area expansion function. Addresses 40000h to BFFFFh can be used as external
areas from bank 0 to bank 7. Figure 3.1 shows the Address Space. Areas that can be accessed vary
depending on processor mode and the status of each control bit.
Memory expansion mode

00000h SFR
00400h
The internal RAM is allocated
Internal RAM from address 00400h higher.
Reserved area
04000h
External area
0D000h SFR
0D800h
External area
In 4 MB mode
0E000h Internal ROM When data flash is enabled
(data flash)
10000h Bank 7
Internal ROM When program ROM 2
(program ROM 2) is enabled Bank 6
1 MB
14000h Bank 5
address space External area
Bank 4
27000h
Reserved area Bank 3
28000h Bank 2
Bank 1
40000h
External area
Bank 0
BFFFFh 512 KB × 8
D0000h
Reserved area
Internal ROM Program ROM 1 is allocated from

(program ROM 1) address FFFFFh lower.
FFFFFh
Notes:
1. Do not access reserved areas.
2. The figure above applies under the following condition:
- The PM13 bit in the PM1 register is 0
(addresses 04000h to 0CFFFh and 80000h to CFFFFh are used as external areas)
Figure 3.1 Address Space
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3.2 Memory Map

Special function registers (SFRs) are allocated from address 00000h to 003FFh and from 0D000h to
0D7FFh. Peripheral function control registers are located here. All blank areas within SFRs are reserved.
Do not access these areas.
Internal RAM is allocated from address 00400h and higher, with 10 KB of internal RAM allocated from
00400h to 02BFFh. Internal RAM is used not only for data storage, but also for the stack area when
subroutines are called or when an interrupt request is accepted.
The internal ROM is flash memory. Three internal ROM areas are available: data flash, program ROM 1,
and program ROM 2.
The data flash is allocated from 0E000h to 0FFFFh. This data flash area is mostly used for data storage, but
can also store programs.
Program ROM 2 is allocated from 10000h to 13FFFh. Program ROM 1 is allocated from FFFFFh and lower,
with the 64-KB program ROM 1 area allocated from address F0000h to FFFFFh.
The special page vectors are allocated from FFE00h to FFFD7h. They are used for the JMPS and JSRS
instructions. Refer to the M16C/60, M16C/20, M16C/Tiny Series Software Manual for details.
The fixed vector table for interrupts is allocated from FFFDCh to FFFFFh.
The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table
for interrupts.
Figure 3.2 shows the Memory Map.
00000h SFR
Internal RAM 00400h
Internal RAM
Size Address XXXXXh XXXXXh
12 KB 033FFh Reserved area (1)
20 KB 053FFh 0D000h SFR

31 KB 07FFFh 0D800h
External area
0E000h Internal ROM 13000h
On-chip debugger
(data flash)
monitor area
10000h Internal ROM 13FF0h
User boot code area
(program ROM 2) 13FFFh
14000h
External area
27000h
Reserved area (1)
28000h
Relocatable vector table
External area
256 bytes beginning with the
Program ROM 1 start address set in the INTB
Size Address YYYYYh register
80000h
128 KB E0000h
256 KB C0000h Reserved area (1)
FFE00h
384 KB A0000h Special page vector table
FFFD8h
512 KB 80000h YYYYYh Reserved area (3)
Internal ROM FFFDCh
Fixed vector table
(program ROM 1) Address for ID code stored
FFFFFh FFFFFh OFS1 address
Notes:
2. The figure above applies under the following conditions:
- Memory expansion mode
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
3. Do not change the data from FFh.
Figure 3.2 Memory Map
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Feb 07, 2011
3.3 Accessible Area in Each Mode

Areas that can be accessed vary depending on processor mode and the status of each control bit. Figure
3.3 shows the Accessible Area in Each Mode.
In single-chip mode, the SFRs, internal RAM, and internal ROM can be accessed.
In memory expansion mode, the SFRs, internal RAM, internal ROM, and external areas can be accessed.
Address space is expandable to 4 MB with the memory area expansion function.
In microprocessor mode, the SFRs, internal RAM, and external areas can be accessed. Address space is
expandable to 4 MB with the memory area expansion function. Allocate ROM to the fixed vector table
from FFFDCh to FFFFFh.
Single-Chip Mode Memory Expansion Mode Microprocessor Mode

00000h SFR 00000h SFR 00000h SFR
00400h 00400h 00400h
Internal RAM Internal RAM Internal RAM
Reserved area Reserved area Reserved area

0D000h 0D000h 0D000h
SFR SFR SFR
0D800h Reserved area 0D800h 0D800h
External area
0E000h Internal ROM 0E000h Internal ROM
(data flash) (data flash)
10000h Internal ROM 10000h Internal ROM External area
(program ROM 2) (program ROM 2)
14000h 14000h
External area
27000h 27000h
Reserved area Reserved area
28000h 28000h
External area
Reserved area
80000h
Reserved area External area
Internal ROM Internal ROM

(program ROM 1) (program ROM 1)
FFFFFh FFFFFh FFFFFh
Notes:
2. The figure above applies under the following conditions:
Single-chip mode and memory expansion mode
(addresses 0E000h to 0FFFFh are used as data flash)
- The PRG2C0 bit in the PRG2C register is 0 (program ROM 2 enabled)
(all areas in internal RAM, and the program ROM 1 area from 80000h are usable)
Microprocessor mode
- The PM10 bit is 0 (addresses 0E000h to 0FFFFh are used as the CS2 area)
- The PRG2C0 bit is 1 (program ROM 2 disabled)
Figure 3.3 Accessible Area in Each Mode
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Feb 07, 2011
M16C/64A Group 4. Special Function Registers (SFRs)
4. Special Function Registers (SFRs)
4.1 SFRs
An SFR is a control register for a peripheral function.
Table 4.1 SFR Information (1) (1)

Address Register Symbol Reset Value
0000h
0001h
0002h
0003h
0000 0000b
(CNVSS pin is low)
0004h Processor Mode Register 0 PM0
0000 0011b
(CNVSS pin is high) (2)
0005h Processor Mode Register 1 PM1 0000 1000b
0006h System Clock Control Register 0 CM0 0100 1000b
0007h System Clock Control Register 1 CM1 0010 0000b
0008h Chip Select Control Register CSR 01h
0009h
000Ah Protect Register PRCR 00h
000Bh Data Bank Register DBR 00h
000Ch Oscillation Stop Detection Register CM2 0X00 0010b (3)
000Dh
000Eh
000Fh
0010h Program 2 Area Control Register PRG2C XXXX XX00b
0011h
0012h Peripheral Clock Select Register PCLKR 0000 0011b
0013h
0014h
0015h Clock Prescaler Reset Flag CPSRF 0XXX XXXXb
0016h
0017h
XX00 001Xb
0018h Reset Source Determine Register RSTFR
(hardware reset) (4)
0019h Voltage Detector 2 Flag Register VCR1 0000 1000b (5)
001Ah Voltage Detector Operation Enable Register VCR2 00h (5)
001Bh Chip Select Expansion Control Register CSE 00h
001Ch PLL Control Register 0 PLC0 0X01 X010b
001Dh
001Eh Processor Mode Register 2 PM2 XX00 0X01b
001Fh
X: Undefined
Notes:
1. The blank areas are reserved. No access is allowed.
2. Software reset, watchdog timer reset, oscillator stop detect reset, voltage monitor 1 reset, and voltage monitor 2 reset
do not affect the following bits: bits PM01 and PM00 in the PM0 register.
3. Oscillator stop detect reset does not affect bits CM20, CM21, and CM27.
4. The state of bits in the RSTFR register depends on the reset type.
5. This is the reset value after hardware reset. Refer to the explanation of each register for details.
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Feb 07, 2011

0020h
0021h
0022h
0023h
0024h
0025h
0026h Voltage Monitor Function Select Register VWCE 00h
0027h
0028h Voltage Detector 1 Level Select Register VD1LS 0000 1010b (2)
0029h
002Ah Voltage Monitor 0 Control Register VW0C 1000 XX10b (2)
002Bh Voltage Monitor 1 Control Register VW1C 1000 1010b (2)
002Ch Voltage Monitor 2 Control Register VW2C 1000 0X10b (2)
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
X: Undefined
Notes:
2. This is the reset value after hardware reset. Refer to the explanation of each register for details.
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0040h
0041h
0042h INT7 Interrupt Control Register INT7IC XX00 X000b
0045h Timer B5 Interrupt Control Register TB5IC XXXX X000b
Timer B4 Interrupt Control Register TB4IC
0046h XXXX X000b
UART1 Bus Collision Detection Interrupt Control Register U1BCNIC
Timer B3 Interrupt Control Register TB3IC
0047h XXXX X000b
SI/O4 Interrupt Control Register S4IC
SI/O3 Interrupt Control Register S3IC
0049h XX00 X000b
INT4 Interrupt Control Register INT4IC
004Ah UART2 Bus Collision Detection Interrupt Control Register BCNIC XXXX X000b
004Bh DMA0 Interrupt Control Register DM0IC XXXX X000b
004Ch DMA1 Interrupt Control Register DM1IC XXXX X000b
004Dh Key Input Interrupt Control Register KUPIC XXXX X000b
004Eh A/D Conversion Interrupt Control Register ADIC XXXX X000b
004Fh UART2 Transmit Interrupt Control Register S2TIC XXXX X000b
0050h UART2 Receive Interrupt Control Register S2RIC XXXX X000b
0051h UART0 Transmit Interrupt Control Register S0TIC XXXX X000b
0053h UART1 Transmit Interrupt Control Register S1TIC XXXX X000b
0055h Timer A0 Interrupt Control Register TA0IC XXXX X000b
005Ah Timer B0 Interrupt Control Register TB0IC XXXX X000b
005Bh Timer B1 Interrupt Control Register TB1IC XXXX X000b
005Ch Timer B2 Interrupt Control Register TB2IC XXXX X000b
005Dh INT0 Interrupt Control Register INT0IC XX00 X000b
005Eh INT1 Interrupt Control Register INT1IC XX00 X000b
005Fh INT2 Interrupt Control Register INT2IC XX00 X000b
X: Undefined
Note:
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Feb 07, 2011

0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h DMA2 Interrupt Control Register DM2IC XXXX X000b
006Ah DMA3 Interrupt Control Register DM3IC XXXX X000b
006Bh XXXX X000b
CEC1 Interrupt Control Register CEC1IC
UART5 Transmit Interrupt Control Register S5TIC
006Ch XXXX X000b
CEC2 Interrupt Control Register CEC2IC
006Dh UART5 Receive Interrupt Control Register S5RIC XXXX X000b
U6BCNIC
UART6 Bus Collision Detection Interrupt Control Register
006Eh XXXX X000b
Real-Time Clock Periodic Interrupt Control Register
RTCTIC
006Fh XXXX X000b
Real-Time Clock Compare Interrupt Control Register RTCCIC
0071h XXXX X000b
Remote Control Signal Receiver 0 Interrupt Control Register PMC0IC
0072h XXXX X000b
Remote Control Signal Receiver 1 Interrupt Control Register PMC1IC
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh XXXX X000b
I2C-bus Interface Interrupt Control Register IICIC
007Ch XXXX X000b
SCL/SDA Interrupt Control Register SCLDAIC
007Dh
007Eh
007Fh
0080h to
017Fh
X: Undefined
Note:
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0180h XXh
0181h DMA0 Source Pointer SAR0 XXh
0182h 0Xh
0183h
0184h XXh
0185h DMA0 Destination Pointer DAR0 XXh
0186h 0Xh
0187h
0188h XXh
DMA0 Transfer Counter TCR0
0189h XXh
018Ah
018Bh
018Ch DMA0 Control Register DM0CON 0000 0X00b
018Dh
018Eh
018Fh
0190h XXh
0191h DMA1 Source Pointer SAR1 XXh
0192h 0Xh
0193h
0194h XXh
0195h DMA1 Destination Pointer DAR1 XXh
0196h 0Xh
0197h
0198h XXh
0199h XXh
019Ah
019Bh
019Ch DMA1 Control Register DM1CON 0000 0X00b
019Dh
019Eh
019Fh
01A0h XXh
01A1h DMA2 Source Pointer SAR2 XXh
01A2h 0Xh
01A3h
01A4h XXh
01A5h DMA2 Destination Pointer DAR2 XXh
01A6h 0Xh
01A7h
01A8h XXh
01A9h XXh
01AAh
01ABh
01ACh DMA2 Control Register DM2CON 0000 0X00b
01ADh
01AEh
01AFh
X: Undefined
Note:
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01B0h XXh
01B1h DMA3 Source Pointer SAR3 XXh
01B2h 0Xh
01B3h
01B4h XXh
01B5h DMA3 Destination Pointer DAR3 XXh
01B6h 0Xh
01B7h
01B8h XXh
01B9h XXh
01BAh
01BBh
01BCh DMA3 Control Register DM3CON 0000 0X00b
01BDh
01BEh
01BFh
01C0h XXh
Timer B0-1 Register TB01
01C1h XXh
01C2h XXh
01C3h XXh
01C4h XXh
01C5h XXh
Pulse Period/Pulse Width Measurement Mode Function Select
01C6h PPWFS1 XXXX X000b
Register 1
01C7h
01C8h Timer B Count Source Select Register 0 TBCS0 00h
01C9h Timer B Count Source Select Register 1 TBCS1 X0h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h Timer A Count Source Select Register 0 TACS0 00h
01D1h Timer A Count Source Select Register 1 TACS1 00h
01D2h Timer A Count Source Select Register 2 TACS2 X0h
01D3h
01D4h 16-bit Pulse Width Modulation Mode Function Select Register PWMFS 0XX0 X00Xb
01D5h Timer A Waveform Output Function Select Register TAPOFS XXX0 0000b
01D6h
01D7h
01D8h Timer A Output Waveform Change Enable Register TAOW XXX0 X00Xb
01D9h
01DAh Three-Phase Protect Control Register TPRC 00h
01DBh
01DCh
01DDh
01DEh
01DFh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 25 of 88

Feb 07, 2011

01E0h XXh
01E1h XXh
01E2h XXh
01E3h XXh
01E4h XXh
01E5h XXh
Pulse Period/Pulse Width Measurement Mode Function Select Reg-
01E6h PPWFS2 XXXX X000b
ister 2
01E7h
01E8h Timer B Count Source Select Register 2 TBCS2 00h
01E9h Timer B Count Source Select Register 3 TBCS3 X0h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h PMC0 Function Select Register 0 PMC0CON0 00h
01F1h PMC0 Function Select Register 1 PMC0CON1 00XX 0000b
01F2h PMC0 Function Select Register 2 PMC0CON2 0000 00X0b
01F3h PMC0 Function Select Register 3 PMC0CON3 00h
01F4h PMC0 Status Register PMC0STS 00h
01F5h PMC0 Interrupt Source Select Register PMC0INT 00h
01F6h PMC0 Compare Control Register PMC0CPC XXX0 X000b
01F7h PMC0 Compare Data Register PMC0CPD 00h
01F8h PMC1 Function Select Register 0 PMC1CON0 XXX0 X000b
01F9h PMC1 Function Select Register 1 PMC1CON1 XXXX 0X00b
01FAh PMC1 Function Select Register 2 PMC1CON2 0000 00X0b
01FBh PMC1 Function Select Register 3 PMC1CON3 00h
01FCh PMC1 Status Register PMC1STS X000 X00Xb
01FDh PMC1 Interrupt Source Select Register PMC1INT X000 X00Xb
01FEh
01FFh
0200h
0201h
0202h
0203h
0204h
0205h Interrupt Source Select Register 3 IFSR3A 00h
0206h Interrupt Source Select Register 2 IFSR2A 00h
0207h Interrupt Source Select Register IFSR 00h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh Address Match Interrupt Enable Register AIER XXXX XX00b
020Fh Address Match Interrupt Enable Register 2 AIER2 XXXX XX00b
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 26 of 88

Feb 07, 2011

0210h 00h
0211h Address Match Interrupt Register 0 RMAD0 00h
0212h X0h
0213h
0214h 00h
0216h X0h
0217h
0218h 00h
021Ah X0h
021Bh
021Ch 00h
021Dh Address Match Interrupt Register 3 RMAD3 00h
021Eh X0h
021Fh
0000 0001b
(Other than user boot mode)
0220h Flash Memory Control Register 0 FMR0
0010 0001b
(User boot mode)
0221h Flash Memory Control Register 1 FMR1 00X0 XX0Xb
0222h Flash Memory Control Register 2 FMR2 XXXX 0000b
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h Flash Memory Control Register 6 FMR6 XX0X XX00b
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 27 of 88

Feb 07, 2011

0240h
0241h
0242h
0243h
0244h UART0 Special Mode Register 4 U0SMR4 00h
0245h UART0 Special Mode Register 3 U0SMR3 000X 0X0Xb
0246h UART0 Special Mode Register 2 U0SMR2 X000 0000b
0247h UART0 Special Mode Register U0SMR X000 0000b
0248h UART0 Transmit/Receive Mode Register U0MR 00h
0249h UART0 Bit Rate Register U0BRG XXh
024Ah XXh
UART0 Transmit Buffer Register U0TB
024Bh XXh
024Ch UART0 Transmit/Receive Control Register 0 U0C0 0000 1000b
024Dh UART0 Transmit/Receive Control Register 1 U0C1 00XX 0010b
024Eh XXh
UART0 Receive Buffer Register U0RB
024Fh XXh
0250h UART Transmit/Receive Control Register 2 UCON X000 0000b
0251h
0252h
0253h
025Ah XXh
025Bh XXh
025Dh UART1 Transmit/Receive Control Register 1 U1C1 00XX 0010b
025Eh XXh
025Fh XXh
0260h
0261h
0262h
0263h
026Ah XXh
026Bh XXh
026Dh UART2 Transmit/Receive Control Register 1 U2C1 0000 0010b
026Eh XXh
026Fh XXh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 28 of 88

Feb 07, 2011

0270h SI/O3 Transmit/Receive Register S3TRR XXh
0271h
0272h SI/O3 Control Register S3C 0100 0000b
0273h SI/O3 Bit Rate Register S3BRG XXh
0274h SI/O4 Transmit/Receive Register S4TRR XXh
0275h
0276h SI/O4 Control Register S4C 0100 0000b
0277h SI/O4 Bit Rate Register S4BRG XXh
0278h SI/O3, 4 Control Register 2 S34C2 00XX X0X0b
0279h
027Ah
027Bh
027Ch
027Dh
027Eh
027Fh
0280h
0281h
0282h
0283h
028Ah XXh
028Bh XXh
028Eh XXh
028Fh XXh
0290h
0291h
0292h
0293h
029Ah XXh
029Bh XXh
029Eh XXh
029Fh XXh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 29 of 88

Feb 07, 2011

02A0h
02A1h
02A2h
02A3h
02A4h UART7 Special Mode Register 4 U7SMR4 00h
02A5h UART7 Special Mode Register 3 U7SMR3 000X 0X0Xb
02A6h UART7 Special Mode Register 2 U7SMR2 X000 0000b
02A7h UART7 Special Mode Register U7SMR X000 0000b
02A8h UART7 Transmit/Receive Mode Register U7MR 00h
02A9h UART7 Bit Rate Register U7BRG XXh
02AAh XXh
02ABh XXh
02ACh UART7 Transmit/Receive Control Register 0 U7C0 0000 1000b
02ADh UART7 Transmit/Receive Control Register 1 U7C1 0000 0010b
02AEh XXh
02AFh XXh
02B0h I2C0 Data Shift Register S00 XXh
02B1h
02B2h I2C0 Address Register 0 S0D0 0000 000Xb
02B3h I2C0 Control Register 0 S1D0 00h
02B4h I2C0 Clock Control Register S20 00h
02B5h I2C0 Start/Stop Condition Control Register S2D0 0001 1010b
02B6h I2C0 Control Register 1 S3D0 0011 0000b
02B7h I2C0 Control Register 2 S4D0 00h
02B8h I2C0 Status Register 0 S10 0001 000Xb
02B9h I2C0 Status Register 1 S11 XXXX X000b
02BAh I2C0 Address Register 1 S0D1 0000 000Xb
02BBh I2C0 Address Register 2 S0D2 0000 000Xb
02BCh
02BDh
02BEh
02BFh
02C0h to
02FFh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 30 of 88

Feb 07, 2011

0300h Timer B3/B4/B5 Count Start Flag TBSR 000X XXXXb
0301h
0302h XXh
Timer A1-1 Register TA11
0303h XXh
0304h XXh
0305h XXh
0306h XXh
0307h XXh
0308h Three-Phase PWM Control Register 0 INVC0 00h
0309h Three-Phase PWM Control Register 1 INVC1 00h
030Ah Three-Phase Output Buffer Register 0 IDB0 XX11 1111b
030Bh Three-Phase Output Buffer Register 1 IDB1 XX11 1111b
030Ch Dead Time Timer DTT XXh
030Dh Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XXh
030Eh Position-Data-Retain Function Control Register PDRF XXXX 0000b
030Fh
0310h XXh
Timer B3 Register TB3
0311h XXh
0312h XXh
0313h XXh
0314h XXh
0315h XXh
0316h
0317h
0318h Port Function Control Register PFCR 0011 1111b
0319h
031Ah
031Bh Timer B3 Mode Register TB3MR 00XX 0000b
031Ch Timer B4 Mode Register TB4MR 00XX 0000b
031Dh Timer B5 Mode Register TB5MR 00XX 0000b
031Eh
031Fh
0320h Count Start Flag TABSR 00h
0321h
0322h One-Shot Start Flag ONSF 00h
0323h Trigger Select Register TRGSR 00h
0324h Increment/Decrement Flag UDF 00h
0325h
0326h XXh
Timer A0 Register TA0
0327h XXh
0328h XXh
0329h XXh
032Ah XXh
032Bh XXh
032Ch XXh
032Dh XXh
032Eh XXh
032Fh XXh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 31 of 88

Feb 07, 2011

0330h XXh
0331h XXh
0332h XXh
0333h XXh
0334h XXh
0335h XXh
0336h Timer A0 Mode Register TA0MR 00h
033Ah Timer A4 Mode Register TA4MR 00h
033Bh Timer B0 Mode Register TB0MR 00XX 0000b
033Ch Timer B1 Mode Register TB1MR 00XX 0000b
033Dh Timer B2 Mode Register TB2MR 00XX 0000b
033Eh Timer B2 Special Mode Register TB2SC X000 0000b
033Fh
0340h Real-Time Clock Second Data Register RTCSEC 00h
0341h Real-Time Clock Minute Data Register RTCMIN X000 0000b
0342h Real-Time Clock Hour Data Register RTCHR XX00 0000b
0343h Real-Time Clock Day Data Register RTCWK XXXX X000b
0344h Real-Time Clock Control Register 1 RTCCR1 0000 X00Xb
0345h Real-Time Clock Control Register 2 RTCCR2 X000 0000b
0346h Real-Time Clock Count Source Select Register RTCCSR XXX0 0000b
0347h
0348h Real-Time Clock Second Compare Data Register RTCCSEC X000 0000b
0349h Real-Time Clock Minute Compare Data Register RTCCMIN X000 0000b
034Ah Real-Time Clock Hour Compare Data Register RTCCHR X000 0000b
034Bh
034Ch
034Dh
034Eh
034Fh
0350h CEC Function Control Register 1 CECC1 XXXX X000b
0351h CEC Function Control Register 2 CECC2 00h
0352h CEC Function Control Register 3 CECC3 XXXX 0000b
0353h CEC Function Control Register 4 CECC4 00h
0354h CEC Flag Register CECFLG 00h
0355h CEC Interrupt Source Select Register CISEL 00h
0356h CEC Transmit Buffer Register 1 CCTB1 00h
0357h CEC Transmit Buffer Register 2 CCTB2 XXXX XX00b
0358h CEC Receive Buffer Register 1 CCRB1 00h
0359h CEC Receive Buffer Register 2 CCRB2 XXXX X000b
035Ah CEC Receive Follower Address Set Register 1 CRADRI1 00h
035Bh CEC Receive Follower Address Set Register 2 CRADRI2 00h
035Ch
035Dh
035Eh
035Fh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 32 of 88

Feb 07, 2011

0360h Pull-Up Control Register 0 PUR0 00h
0361h Pull-Up Control Register 1 PUR1 0000 0000b (2)
0000 0010b
0362h Pull-Up Control Register 2 PUR2 00h
0363h
0364h
0365h
0366h Port Control Register PCR 0000 0XX0b
0367h
0368h
0369h NMI/SD Digital Filter Register NMIDF XXXX X000b
036Ah
036Bh
036Ch
036Dh
036Eh
036Fh
0370h PWM Control Register 0 PWMCON0 00h
0371h
0372h PWM0 Prescaler PWMPRE0 00h
0373h PWM0 Register PWMREG0 00h
0374h PWM1 Prescaler PWMPRE1 00h
0375h PWM1 Register PWMREG1 00h
0376h PWM Control Register 1 PWMCON1 00h
0377h
0378h
0379h
037Ah
037Bh
037Ch Count Source Protection Mode Register CSPR 00h (3)
037Dh Watchdog Timer Refresh Register WDTR XXh
037Eh Watchdog Timer Start Register WDTS XXh
037Fh Watchdog Timer Control Register WDC 00XX XXXXb
0380h to
038Fh
X: Undefined
Notes:
2. Values after hardware reset, power-on reset, or voltage monitor 0 reset are as follows:
- 00000000b when a low-level signal is input to the CNVSS pin
- 00000010b when a high-level signal is input to the CNVSS pin
Values after voltage monitor 1 reset, voltage monitor 2 reset, software reset, watchdog timer reset, or oscillation stop
detect reset are as follows:
- 00000000b when bits PM01 and PM00 in the PM0 register are 00b (single-chip mode).
- 00000010b when bits PM01 and PM00 in the PM0 register are 01b (memory expansion mode) or 11b
(microprocessor mode).
3. When the CSPROINI bit in the OFS1 address is 0, the reset value is 10000000b.
R01DS0032EJ0200 Rev.2.00 Page 33 of 88

Feb 07, 2011

0390h DMA2 Source Select Register DM2SL 00h
0391h
0393h
0394h
0395h
0396h
0397h
0399h
039Ah DMA1 Source Select Register DM1SL 00h
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h Open-Circuit Detection Assist Function Register AINRST XX00 XXXXb
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h XXXX XXXXb
SFR Snoop Address Register CRCSAR
03B5h 00XX XXXXb
03B6h CRC Mode Register CRCMR 0XXX XXX0b
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh XXh
CRC Data Register CRCD
03BDh XXh
03BEh CRC Input Register CRCIN XXh
03BFh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 34 of 88

Feb 07, 2011

03C0h XXXX XXXXb
A/D Register 0 AD0
03C1h 0000 00XXb
03C2h XXXX XXXXb
A/D Register 1 AD1
03C3h 0000 00XXb
03C4h XXXX XXXXb
A/D Register 2 AD2
03C5h 0000 00XXb
03C6h XXXX XXXXb
A/D Register 3 AD3
03C7h 0000 00XXb
03C8h XXXX XXXXb
A/D Register 4 AD4
03C9h 0000 00XXb
03CAh XXXX XXXXb
A/D Register 5 AD5
03CBh 0000 00XXb
03CCh XXXX XXXXb
A/D Register 6 AD6
03CDh 0000 00XXb
03CEh XXXX XXXXb
A/D Register 7 AD7
03CFh 0000 00XXb
03D0h
03D1h
03D2h
03D3h
03D4h A/D Control Register 2 ADCON2 0000 X00Xb
03D5h
03D6h A/D Control Register 0 ADCON0 0000 0XXXb
03D7h A/D Control Register 1 ADCON1 0000 X000b
03D8h D/A0 Register DA0 00h
03D9h
03DAh D/A1 Register DA1 00h
03DBh
03DCh D/A Control Register DACON 00h
03DDh
03DEh
03DFh
03E0h Port P0 Register P0 XXh
03E2h Port P0 Direction Register PD0 00h
03EAh Port P4 Direction Register PD4 00h
03EBh Port P5 Direction Register PD5 00h
03ECh Port P6 Register P6 XXh
03EDh Port P7 Register P7 XXh
03EEh Port P6 Direction Register PD6 00h
03EFh Port P7 Direction Register PD7 00h
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 35 of 88

Feb 07, 2011

03F0h Port P8 Register P8 XXh
03F2h Port P8 Direction Register PD8 00h
03F5h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 36 of 88

Feb 07, 2011

D080h 0000 0000b
PMC0 Header Pattern Set Register (Min) PMC0HDPMIN
D081h XXXX X000b
D082h 0000 0000b
PMC0 Header Pattern Set Register (Max) PMC0HDPMAX
D083h XXXX X000b
D084h PMC0 Data 0 Pattern Set Register (Min) PMC0D0PMIN 00h
D085h PMC0 Data 0 Pattern Set Register (Max) PMC0D0PMAX 00h
D088h 00h
PMC0 Measurements Register PMC0TIM
D089h 00h
D08Ah
D08Bh
D08Ch PMC0 Receive Data Store Register 0 PMC0DAT0 00h
D08Dh PMC0 Receive Data Store Register 1 PMC0DAT1 00h
D08Eh PMC0 Receive Data Store Register 2 PMC0DAT2 00h
D08Fh PMC0 Receive Data Store Register 3 PMC0DAT3 00h
D090h PMC0 Receive Data Store Register 4 PMC0DAT4 00h
D091h PMC0 Receive Data Store Register 5 PMC0DAT5 00h
D092h PMC0 Receive Bit Count Register PMC0RBIT XX00 0000b
D093h
D094h 0000 0000b
PMC1 Header Pattern Set Register (Min) PMC1HDPMIN
D095h XXXX X000b
D096h 0000 0000b
PMC1 Header Pattern Set Register (Max) PMC1HDPMAX
D097h XXXX X000b
D09Ah PMC1 Data 1 Pattern Set Register (Min) PMC1D1PMIN 00h
D09Bh PMC1 Data 1 Pattern Set Register (Max) PMC1D1PMAX 00h
D09Ch 00h
PMC1 Measurements Register PMC1TIM
D09Dh 00h
D09Eh
D09Fh
X: Undefined
Note:
R01DS0032EJ0200 Rev.2.00 Page 37 of 88

Feb 07, 2011
4.2 Notes on SFRs
4.2.1 Register Settings

Table 4.19 lists Registers with Write-Only Bits and registers whose function differs between reading and
writing. Set these registers with immediate values. Do not use read-modify-write instructions. When
establishing the next value by altering the existing value, write the existing value to the RAM as well as
to the register. Transfer the next value to the register after making changes in the RAM.
Read-modify-write instructions can be used when writing to the no register bits.
Table 4.19 Registers with Write-Only Bits

Address Register Symbol
0249h UART0 Bit Rate Register U0BRG
024Bh to 024Ah UART0 Transmit Buffer Register U0TB
0273h SI/O3 Bit Rate Register S3BRG
0277h SI/O4 Bit Rate Register S4BRG
02A9h UART7 Bit Rate Register U7BRG
02ABh to 02AAh UART7 Transmit Buffer Register U7TB
02B6h I2C0 Control Register 1 S3D0
02B8h I2C0 Status Register 0 S10
0303h to 0302h Timer A1-1 Register TA11
030Ah Three-Phase Output Buffer Register 0 IDB0
030Bh Three-Phase Output Buffer Register 1 IDB1
030Ch Dead Time Timer DTT
030Dh Timer B2 Interrupt Generation Frequency Set Counter ICTB2
0327h to 0326h Timer A0 Register TA0
0329h to 0328h Timer A1 Register TA1
032Bh to 032Ah Timer A2 Register TA2
032Dh to 032Ch Timer A3 Register TA3
032Fh to 032Eh Timer A4 Register TA4
037Dh Watchdog Timer Refresh Register WDTR
037Eh Watchdog Timer Start Register WDTS
R01DS0032EJ0200 Rev.2.00 Page 38 of 88

Feb 07, 2011
Table 4.20 Read-Modify-Write Instructions

Function Mnemonic
Transfer MOVDir
Bit processing BCLR, BMCnd, BNOT, BSET, BTSTC, and BTSTS
Shifting ROLC, RORC, ROT, SHA, and SHL
ABS, ADC, ADCF, ADD, DEC, DIV, DIVU, DIVX, EXTS, INC, MUL, MULU, NEG,
Arithmetic operation
SBB, and SUB
Decimal operation DADC, DADD, DSBB, and DSUB
Logical operation AND, NOT, OR, and XOR
Jump ADJNZ, SBJNZ
R01DS0032EJ0200 Rev.2.00 Page 39 of 88

Feb 07, 2011
M16C/64A Group 5. Electrical Characteristics
5. Electrical Characteristics
5.1 Electrical Characteristics (Common to 3 V and 5 V)
5.1.1 Absolute Maximum Rating
Table 5.1 Absolute Maximum Ratings

Symbol Parameter Condition Rated Value Unit
VCC1 Supply voltage VCC1 = AVCC −0.3 to 6.5 V
VCC2 Supply voltage VCC1 = AVCC −0.3 to VCC1 + 0.1 (1) V
AVCC Analog supply voltage VCC1 = AVCC −0.3 to 6.5 V
VREF Analog reference voltage VCC1 = AVCC −0.3 to VCC1 + 0.1 (1) V
VI Input voltage RESET, CNVSS, BYTE, −0.3 to VCC1 + 0.3 (1) V
P6_0 to P6_7, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
XIN
P0_0 to P0_7, P1_0 to P1_7, −0.3 to VCC2 + 0.3 (1) V
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
P7_0, P7_1, P8_5 −0.3 to 6.5 V
VO Output voltage P6_0 to P6_7, P7_2 to P7_7, −0.3 to VCC1 + 0.3 (1) V
P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
XOUT
P0_0 to P0_7, P1_0 to P1_7, −0.3 to VCC2 + 0.3 (1) V
P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7
P7_0, P7_1, P8_5 −0.3 to 6.5 V
Pd Power consumption −40°C < Topr ≤ 85°C 300 mW
Topr Operating When the MCU is operating −20 to 85/−40 to 85 °C
temperature Flash program erase Program area 0 to 60
Data area −20 to 85/−40 to 85
Tstg Storage temperature −65 to 150 °C
Note:
1. Maximum value is 6.5 V.
R01DS0032EJ0200 Rev.2.00 Page 40 of 88

Feb 07, 2011
5.1.2 Recommended Operating Conditions
Table 5.2 Recommended Operating Conditions (1/3)

VCC1 = VCC2 = 2.7 to 5.5 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Standard
Symbol Parameter Unit
Min. Typ. Max.
VCC1, Supply voltage (VCC1 ≥ VCC2) CEC function is not used 2.7 5.0 5.5 V
VCC2 CEC function is used 2.7 3.63 V
AVCC Analog supply voltage VCC1 V
VSS Supply voltage 0 V
AVSS Analog supply voltage 0 V
VIH High input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 0.8VCC2 VCC2 V
voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0.8VCC2 VCC2 V
(in single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0.5VCC2 VCC2 V
(data input in memory expansion and microprocessor
modes)
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7, 0.8VCC1 VCC1 V
P9_0 to P9_7, P10_0 to P10_7
XIN, RESET, CNVSS, BYTE
P7_0, P7_1, P8_5 0.8VCC1 6.5 V
CEC 0.7VCC1 V
VIL Low input P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 0 0.2VCC2 V
voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0 0.2VCC2 V
(in single-chip mode)
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 0 0.16VCC2 V
(data input in memory expansion and microprocessor mode)
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to P9_7, 0 0.2VCC1 V
P10_0 to P10_7
CEC 0.26VCC1 V
IOH(sum) High peak Sum of IOH(peak) at P0_0 to P0_7, P1_0 to P1_7, -40.0 mA
output
P2_0 to P2_7
current
Sum of IOH(peak) at P3_0 to P3_7, P4_0 to P4_7, -40.0 mA
P5_0 to P5_7
Sum of IOH(peak) at P6_0 to P6_7, P7_2 to P7_7, -40.0 mA
P8_0 to P8_4
Sum of IOH(peak) at P8_6, P8_7, P9_0 to P9_7, -40.0 mA
P10_0 to P10_7
IOH(peak) High peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, −10.0 mA
output P4_0 to P4_7, P5_0 to P5_7,
current P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOH(avg) High P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, −5.0 mA
average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, P8_6, P8_7,
current (1) P9_0 to P9_7, P10_0 to P10_7
Note:
1. The average output current is the mean value within 100 ms.
R01DS0032EJ0200 Rev.2.00 Page 41 of 88

Feb 07, 2011
Table 5.3 Recommended Operating Conditions (2/3)

VCC1 = VCC2 = 2.7 to 5.5 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Standard
Min. Typ. Max.
IOL(sum) Low peak Sum of IOL(peak) at P0_0 to P0_7, P1_0 to P1_7, 80.0 mA
output P2_0 to P2_7, P8_6, P8_7, P9_0 to P9_7,
current P10_0 to P10_7
IOL(peak) Low peak P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, 10.0 mA
output P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
current P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IOL(avg) Low P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, 5.0 mA
average P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
current (1) P9_0 to P9_7, P10_0 to P10_7
f(XIN) Main clock input VCC1 = 2.7 V to 5.5 V 2 20 MHz
oscillation frequency
f(XCIN) Sub clock oscillation frequency 32.768 50 kHz
f(PLL) PLL clock oscillation VCC1 = 2.7 V to 5.5 V 10 25 MHz
frequency
f(BCLK) CPU operation clock 2 25 MHz
tSU(PLL) PLL frequency VCC1 = 5.0 V 2 ms
synthesizer
VCC1 = 3.0 V 3 ms
stabilization wait time
Note:
1. The average output current is the mean value within 100 ms.
Table 5.4 Recommended Operating Conditions (3/3) (1)

VCC1 = 2.7 to 5.5 V, VSS = 0 V, and Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
The ripple voltage must not exceed Vr(VCC1) and/or dVr(VCC1)/dt.
Standard
Min. Typ. Max.
Vr(VCC1) Allowable ripple voltage VCC1 = 5.0 V 0.5 Vp-p
VCC1 = 3.0 V 0.3 Vp-p
dVr(VCC1)/dt Ripple voltage falling gradient VCC1 = 5.0 V 0.3 V/ms
VCC1 = 3.0 V 0.3 V/ms
Note:
1. The device is operationally guaranteed under these operating conditions.
VCC1
Vr( VCC1)
Figure 5.1 Ripple Waveform
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Feb 07, 2011
5.1.3 A/D Conversion Characteristics

Table 5.5 A/D Conversion Characteristics (1/2) (1)
VCC1 = AVCC = 3.0 to 5.5 V ≥ VCC2 ≥ VREF, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise
specified.
Standard
Symbol Parameter Measuring Condition Unit
Min. Typ. Max.
- Resolution AVCC = VCC1 ≥ VCC2 ≥ VREF 10 Bits
INL Integral non-linearity error 10bit VCC1 = AN0 to AN7 input, ±3 LSB
5.0 V AN0_0 to AN0_7 input,
AN2_0 to AN2_7 input,
ANEX0, ANEX1 input
(Note 2)
VCC1 = AN0 to AN7 input, ±3 LSB
ANEX0, ANEX1 input
(Note 2)
ANEX0, ANEX1 input
(Note 2)
- Absolute accuracy 10bit VCC1 = AN0 to AN7 input, ±3 LSB
ANEX0, ANEX1 input
(Note 2)
ANEX0, ANEX1 input
(Note 2)
ANEX0, ANEX1 input
(Note 2)
Notes:
1. Use when AVCC = VCC1.
2. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and
connect them to VSS. See Figure 5.2 “A/D Accuracy Measure Circuit”.
AN Analog input
P0 to P10 AN: One of the analog input pin

P0 to P10: I/O pins other than AN
Figure 5.2 A/D Accuracy Measure Circuit
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Feb 07, 2011
Table 5.6 A/D Conversion Characteristics (2/2) (1)

VCC1 = AVCC = 3.0 to 5.5 V ≥ VCC2 ≥ VREF, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise
specified.
Standard
Min. Typ. Max.
φAD A/D operating clock AN0 to AN7 input, 4.0 V ≤ VCC1 ≤ 5.5 V 2 25 MHz
frequency ANEX0 to ANEX1 3.2 V ≤ V
CC1 ≤ 4.0 V 2 16 MHz
input
3.0 V ≤ VCC1 ≤ 3.2 V 2 10 MHz
AN0_0 to AN0_7 4.0 V ≤ VCC2 ≤ 5.5 V 2 25 MHz
input, AN2_0 to 3.2 V ≤ VCC2 ≤ 4.0 V 2 16 MHz
AN2_7 input 3.0 V ≤ V ≤ 3.2 V 2 10
CC2 MHz
- Tolerance level impedance 3 kΩ
DNL Differential non-linearity error (4) ±1 LSB
- Offset error (4) ±3 LSB
- Gain error (4) ±3 LSB
tCONV 10-bit conversion time VCC1 = 5 V, φAD = 25 MHz 1.60 μs
tSAMP Sampling time 0.60 μs
VREF Reference voltage 3.0 VCC1 V
VIA Analog input voltage (2), (3) 0 VREF V
Notes:
1. Use when AVCC = VCC1.
2. When VCC1 ≥ VCC2, set as below:
Analog input voltage (AN0 to AN7, ANEX0, and ANEX1) ≤ VCC1
Analog input voltage (AN0_0 to AN0_7 and AN2_0 to AN2_7) ≤ VCC2.
3. When analog input voltage is over reference voltage, the result of A/D conversion is 3FFh.
4. Flash memory rewrite disabled. Except for the analog input pin, set the pins to be measured as input ports and
connect them to VSS. See Figure 5.2 “A/D Accuracy Measure Circuit”.
5.1.4 D/A Conversion Characteristics
Table 5.7 D/A Conversion Characteristics

VCC1 = AVCC = VREF = 3.0 to 5.5 V, VSS = AVSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Standard
Min. Typ. Max.
- Resolution 8 Bits
- Absolute Accuracy 2.5 LSB
tSU Setup Time 3 μs
RO Output Resistance 5 6 8.2 kΩ
IVREF Reference Power Supply Input Current See Notes 1 and 2 1.5 mA
Notes:
1. This applies when using one D/A converter, with the D/A register for the unused D/A converter set to 00h.
2. The current consumption of the A/D converter is not included. Also, the IVREF of the D/A converter will flow even
if the ADSTBY bit in the ADCON1 register is 0 (A/D operation stopped (standby)).
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Feb 07, 2011
5.1.5 Flash Memory Electrical Characteristics

Table 5.8 CPU Clock When Operating Flash Memory (f(BCLK))
VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified.
Standard
Symbol Parameter Conditions Unit
Min. Typ. Max.
- CPU rewrite mode 10 (1) MHz
f(SLOW_R) Slow read mode 5 (3) MHz
- Low current consumption read mode fC(32.768) 35 kHz
- Data flash read 2.7 V ≤ VCC1 ≤ 3.0 V 16 (2) MHz
3.0 V < VCC1 ≤ 5.5 V 20 (2) MHz
Notes:
1. Set the PM17 bit in the PM1 register to 1 (one wait).
2. When the frequency is over this value, set the FMR17 bit in the FMR1 register to 0 (one wait) or the PM17 bit in
the PM1 register to 1 (one wait)
3. Set the PM17 bit in the PM1 register to 1 (one wait). When using 125 kHz on-chip oscillator clock or sub clock as
the CPU clock source, a wait is not necessary.
Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics

VCC1 = 2.7 to 5.5 V at Topr = 0°C to 60°C (option: -40°C to 85°C), unless otherwise specified.
Standard
Min. Typ. Max.
- Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C 1,000 (2) times
- 2 word program time VCC1 = 3.3 V, Topr = 25°C 150 4000 μs
- Lock bit program time VCC1 = 3.3 V, Topr = 25°C 70 3000 μs
- Block erase time VCC1 = 3.3 V, Topr = 25°C 0.2 3.0 s
- Program, erase voltage 2.7 5.5 V
- Read voltage Topr= -20°C to 85°C/-40°C to 85°C 2.7 5.5 V
- Program, erase temperature 0 60 °C
tPS Flash memory circuit stabilization wait time 50 μs
- Data hold time (6) Ambient temperature = 55°C 20 year
Notes:
1. Definition of program and erase cycles:
The program and erase cycles refer to the number of per-block erasures. If the program and erase cycles are n
(n = 1,000), each block can be erased n times. For example, if a block is erased after writing 2 word data 16,384
times, each to a different address, this counts as one program and erase cycles. Data cannot be written to the
same address more than once without erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. It is advisable to retain data on the erasure cycles of each block and limit the number of erase
operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
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Feb 07, 2011
Table 5.10 Flash Memory (Data Flash) Electrical Characteristics

VCC1 = 2.7 to 5.5 V at Topr = -20 to 85°C/-40 to 85°C, unless otherwise specified.
Standard
Min. Typ. Max.
- Program and erase cycles (1), (3), (4) VCC1 = 3.3 V, Topr = 25°C 10,000 (2) times
- 2 word program time VCC1 = 3.3 V, Topr = 25°C 300 4000 μs
- Lock bit program time VCC1 = 3.3 V, Topr = 25°C 140 3000 μs
- Block erase time VCC1 = 3.3 V, Topr = 25°C 0.2 3.0 s
- Program, erase voltage 2.7 5.5 V
- Read voltage 2.7 5.5 V
- Program, erase temperature −20/−40 85 °C
tPS Flash memory circuit stabilization wait time 50 μs
- Data hold time (6) Ambient temperature = 55 °C 20 year
Notes:
1. Definition of program and erase cycles
The program and erase cycles refer to the number of per-block erasures.
If the program and erase cycles are n (n = 10,000), each block can be erased n times.
For example, if a 4 KB block is erased after writing 2 word data 1,024 times, each to a different address, this
counts as one program and erase cycles. Data cannot be written to the same address more than once without
erasing the block (rewrite prohibited).
2. Cycles to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
3. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing
to sequential addresses in turn so that as much of the block as possible is used up before performing an erase
operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be
minimized by programming up to 256 groups before erasing them all in one operation. In addition, averaging the
erasure cycles between blocks A and B can further reduce the actual erasure cycles. It is also advisable to retain
data on the erasure cycles of each block and limit the number of erase operations to a certain number.
4. If an error occurs during block erase, attempt to execute the clear status register command, then execute the
block erase command at least three times until the erase error does not occur.
5. Customers desiring program/erase failure rate information should contact a Renesas Electronics sales office.
6. The data hold time includes time that the power supply is off or the clock is not supplied.
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Feb 07, 2011
5.1.6 Voltage Detector and Power Supply Circuit Electrical Characteristics
Table 5.11 Voltage Detector 0 Electrical Characteristics

The measurement condition is VCC1 = 2.7 to 5.5 V, Topr = -20°C to 85°C/-40°C to 85°C, unless otherwise specified.
Standard
Symbol Parameter Condition Unit
Min. Typ. Max.
Vdet0 Voltage detection level Vdet0_0 (1) When VCC1 is falling. 1.60 1.90 2.20 V
Voltage detection level Vdet0_2 (1) When VCC1 is falling. 2.55 2.85 3.15 V
- Voltage detector 0 response time (3) When VCC1 falls from 5 V
200 μs
to (Vdet0_0 - 0.1) V
- Voltage detector self power consumption VC25 = 1, VCC1 = 5.0 V 1.8 μA
td(E-A) Waiting time until voltage detector operation
100 μs
starts (2)
Notes:
1. Select the voltage detection level with the VDSEL1 bit in the OFS1 address.
2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC25 bit in the VCR2
register to 0.
3. Time from when passing the Vdet0 until when a voltage monitor 0 reset is generated.

Standard
Min. Typ. Max.
Vdet1 Voltage detection level Vdet1_6 (1) When VCC1 is falling. 2.79 3.09 3.39 V
Voltage detection level Vdet1_B (1) When VCC1 is falling. 3.54 3.84 4.14 V
Voltage detection level Vdet1_F (1) When VCC1 is falling. 3.94 4.44 4.94 V
- Hysteresis width when VCC1 of voltage detector
0.15 V
1 is rising
- Voltage detector 1 response time (3) When VCC1 falls from 5 V
200 μs
to (Vdet1_0 - 0.1) V
td(E-A) Waiting time until voltage detector operation
100 μs
starts (2)
Notes:
1. Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
2. Necessary time until the voltage detector operates when setting to 1 again after setting the VC26 bit in the VCR2
register to 0.
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Feb 07, 2011

Standard
Min. Typ. Max.
Vdet2 Voltage detection level Vdet2_0 When VCC1 is falling 3.50 4.00 4.50 V
- Hysteresis width at the rising of VCC1 in voltage
0.15 V
detector 2
- Voltage detector 2 response time (2) When VCC1 falls from 5
200 μs
V to (Vdet2_0 - 0.1) V
td(E-A) Waiting time until voltage detector operation starts (1) 100 μs
Notes:
1. Necessary time until the voltage detector operates after setting to 1 again after setting the VC27 bit in the VCR2
register to 0.
Table 5.14 Power-On Reset Circuit

The measurement condition is VCC1 = 2.0 to 5.5 V, Topr = -20°C to 85°C/ -40°C to 85°C, unless otherwise specified.
Standard
Min. Typ. Max.
Vpor1 Voltage at which power-on reset enabled (1) 0.1 V
trth External power VCC1 rise gradient 2.0 50000 mV/ms
tw(por) Time necessary to enable power-on reset 300 ms
Note:
1. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS1 address
to 0. Also, set the VDSEL1 bit to 0 (Vdet0_2).
Vdet0 (1) Vdet0 (1)

t rth
t rth
VCC1
Vpor1
tw(por) Voltage detection 0
circuit response time
Internal
reset signal
1 1
× 32 × 32
fOCO-S fOCO-S
Note:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit.
Figure 5.3 Power-On Reset Circuit Electrical Characteristics
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Feb 07, 2011
Table 5.15 Power Supply Circuit Timing Characteristics

The measurement condition is VCC1 = 2.7 to 5.5 V and Topr = 25°C, unless otherwise specified.
Standard
Min. Typ. Max.
td(P-R) Internal power supply stability time when power is on (1) 5 ms
td(R-S) STOP release time 150 μs
td(W-S) Low power mode wait mode release time 150 μs
Note:
1. Waiting time until the internal power supply generator stabilizes when power is on.
td(P-R) Recommended
operation voltage
Internal power supply stability
time when power is on
VCC1
td(P-R)
CPU clock
td(R-S) Interrupt for

STOP release time (a) Stop mode release
or
(b) Wait mode release
td(W-S)
Low power mode
wait mode release time
CPU clock
(a)
td(R-S)
(b) td(W-S)
td(E-A)
Voltage detector VC25, VC26, VC27
operation start time
Voltage detector Stop Operate
td(E-A)
Figure 5.4 Power Supply Circuit Timing Diagram
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Feb 07, 2011
5.1.7 Oscillator Electrical Characteristics
Table 5.16 125 kHz On-Chip Oscillator Electrical Characteristics

VCC1 = 2.7 to 5.5 V, Topr = −20°C to 85°C/−40°C to 85°C, unless otherwise specified.
Standard
Min. Typ. Max.
fOCO-S 125 kHz on-chip oscillator frequency Average frequency in a 10 ms period 100 125 150 kHz
tsu(fOCO-S) Wait time until 125 kHz on-chip
20 μs
oscillator stabilizes
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Feb 07, 2011
5.2 Electrical Characteristics (VCC1 = VCC2 = 5 V)
5.2.1 Electrical Characteristics

VCC1 = VCC2 = 5 V
Table 5.17 Electrical Characteristics (1) (1)
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 25 MHz unless otherwise
specified.
Measuring Standard
Condition Min. Typ. Max.
VOH High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = −5 mA VCC1 − 2.0 VCC1 V
voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = −5 mA VCC2 − 2.0 VCC2
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
VOH High output P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = −200 μA VCC1 − 0.3 VCC1 V
voltage P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = −200 μA VCC2 − 0.3 VCC2
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
VOH High output voltage XOUT HIGH POWER IOH = −1 mA VCC1 − 2.0 VCC1 V
LOW POWER IOH = −0.5 mA VCC1 − 2.0 VCC1
High output voltage XCOUT HIGH POWER With no load 2.6 V
applied
LOW POWER With no load 2.2
applied
VOL Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, IOL = 5 mA 2.0 V
voltage P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 5 mA 2.0
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
VOL Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, IOL = 200 μA 0.45 V
voltage P9_0 to P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 200 μA 0.45
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
VOL Low output voltage XOUT HIGH POWER IOL = 1 mA 2.0 V
LOW POWER IOL = 0.5 mA 2.0
Low output voltage XCOUT HIGH POWER With no load 0 V
applied
LOW POWER With no load 0
applied
Note:
1. When VCC1 ≠ VCC2, refer to 5 V or 3 V standard depending on the voltage.
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Feb 07, 2011
VCC1 = VCC2 = 5 V
VCC1 = VCC2 = 4.2 to 5.5 V, VSS = 0 V at Topr = −20°C to 85°C/−40°C to 85°C, f(BCLK) = 25 MHz unless otherwise specified.
Measuring Standard
Condition Min. Typ. Max.
VT+ - VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, 0.5 2.0 V
INT0 to INT7, NMI, ADTRG, CTS0 to CTS2,
CTS5 to CTS7, SCL0 to SCL2, SCL5 to SCL7,
SDA0 to SDA2, SDA5 to SDA7, CLK0 to CLK7,
TA0OUT to TA4OUT,
KI0 to KI3, RXD0 to RXD2, RXD5 to RXD7,
SIN3, SIN4, SD, PMC0, PMC1, SCLMM,
SDAMM, CEC, ZP, IDU, IDV, IDW
VT+ - VT- Hysteresis RESET 0.5 2.5 V
IIH High input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 5 V 5.0 μA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
IIL Low input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V −5.0 μA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
RPULLUP Pull-up P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 30 50 100 kΩ
resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
RfXIN Feedback resistance XIN 1.5 MΩ
RfXCIN Feedback resistance XCIN 8 MΩ
VRAM RAM retention voltage In stop mode 1.8 V
Note:
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Feb 07, 2011
VCC1 = VCC2 = 5 V
Table 5.19 Electrical Characteristics (3)
R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB,
R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB
Standard
Min. Typ. Max.
ICC Power supply current High-speed mode f(BCLK) = 25 MHz
XIN = 4.2 MHz (square wave), PLL multiplied by 6 20.0 mA
In single-chip, mode, 125 kHz on-chip oscillator stopped
the output pin are f(BCLK) =25 MHz, A/D conversion
open and other pins XIN = 4.2 MHz (square wave), PLL multiplied by 6 20.7 mA
are VSS 125 kHz on-chip oscillator stopped
f(BCLK) = 20 MHz
XIN = 20 MHz (square wave) 16.0 mA
125 kHz on-chip oscillator stopped
125 kHz on-chip Main clock stopped
oscillator mode 125 kHz on-chip oscillator on, no division 500.0 μA
FMR22 = 1 (slow read mode)
Low-power mode f(BCLK) = 32 kHz
In low-power mode
160.0 μA
FMR22 = FMR23 = 1
On flash memory (1)
f(BCLK) = 32 kHz
In low-power mode 45.0 μA
On RAM (1)
Wait mode Main clock stopped
125 kHz on-chip oscillator on
20.0 μA
Peripheral clock operating
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity High)
11.0 μA
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity Low)
6.0 μA
Topr = 25°C
Stop mode Main clock stopped
1.7 μA
Peripheral clock stopped
Topr = 25°C
During flash f(BCLK) = 10 MHz, PM17 = 1 (one wait)
memory program VCC1 = 5.0 V 20.0 mA

memory erase 30.0 mA
VCC1 = 5.0 V
Note:
1. This indicates the memory in which the program to be executed exists.
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Feb 07, 2011
VCC1 = VCC2 = 5 V
R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB
R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB
Standard
Min. Typ. Max.
the output pin are f(BCLK) = 25 MHz, A/D conversion
f(BCLK) = 20 MHz
Low-power mode f(BCLK) = 32 kHz
In low-power mode
170.0 μA
FMR22 = FMR23 = 1
on flash memory (1)
f(BCLK) = 32 kHz
on RAM (1)
20.5 μA
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity High)
11.0 μA
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity low)
6.0 μA
Topr = 25°C
1.7 μA
Topr = 25°C
During flash memory f(BCLK) = 10 MHz, PM17 = 1 (one wait)
program 20.0 mA
VCC1 = 5.0 V
During flash memory f(BCLK) = 10 MHz, PM17 = 1 (one wait)
erase 30.0 mA
VCC1 = 5.0 V
Note:
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Feb 07, 2011
VCC1 = VCC2 = 5 V
5.2.2 Timing Requirements (Peripheral Functions and Others)

(VCC1 = VCC2 = 5 V, VSS = 0 V, at Topr = -20°C to 85°C/-40°C to 85°C unless otherwise specified)
5.2.2.1 Reset Input (RESET Input)
Table 5.21 Reset Input (RESET Input)

Standard
Min. Max.
tw(RSTL) RESET input low pulse width 10 μs
RESET input
t w(RTSL)
Figure 5.5 Reset Input (RESET Input)
5.2.2.2 External Clock Input
Table 5.22 External Clock Input (XIN Input) (1)

Standard
Min. Max.
tc External clock input cycle time 50 ns
tw(H) External clock input high pulse width 20 ns
tw(L) External clock input low pulse width 20 ns
tr External clock rise time 9 ns
tf External clock fall time 9 ns
Note:
1. The condition is VCC1 = VCC2 = 3.0 to 5.0 V.
XIN input
tf
tr t w(H) t w(L)
tc
Figure 5.6 External Clock Input (XIN Input)
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
5.2.2.3 Timer A Input
Table 5.23 Timer A Input (Counter Input in Event Counter Mode)

Standard
Min. Max.
tc(TA) TAiIN input cycle time 100 ns
tw(TAH) TAiIN input high pulse width 40 ns
tw(TAL) TAiIN input low pulse width 40 ns
Table 5.24 Timer A Input (Gating Input in Timer Mode)

Standard
Min. Max.
Table 5.25 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Min. Max.
Table 5.26 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Standard
Min. Max.
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.7 Timer A Input
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
Table 5.27 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
tsu(TAIN-TAOUT) TAiOUT input setup time 200 ns
tsu(TAOUT-TAIN) TAiIN input setup time 200 ns
Two-phase pulse input in event counter mode

tc(TA)
TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.8 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
5.2.2.4 Timer B Input
Table 5.28 Timer B Input (Counter Input in Event Counter Mode)

Standard
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 100 ns
tw(TBH) TBiIN input high pulse width (counted on one edge) 40 ns
tw(TBL) TBiIN input low pulse width (counted on one edge) 40 ns
tc(TB) TBiIN input cycle time (counted on both edges) 200 ns
tw(TBH) TBiIN input high pulse width (counted on both edges) 80 ns
tw(TBL) TBiIN input low pulse width (counted on both edges) 80 ns
Table 5.29 Timer B Input (Pulse Period Measurement Mode)

Standard
Min. Max.
tc(TB) TBiIN input cycle time 400 ns
tw(TBH) TBiIN input high pulse width 200 ns
tw(TBL) TBiIN input low pulse width 200 ns
Table 5.30 Timer B Input (Pulse Width Measurement Mode)

Standard
Min. Max.
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.9 Timer B Input
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
5.2.2.5 Serial Interface
Table 5.31 Serial Interface

Standard
Min. Max.
tc(CK) CLKi input cycle time 200 ns
tw(CKH) CLKi input high pulse width 100 ns
tw(CKL) CLKi input low pulse width 100 ns
td(C-Q) TXDi output delay time 80 ns
th(C-Q) TXDi hold time 0 ns
tsu(D-C) RXDi input setup time 70 ns
th(C-D) RXDi input hold time 90 ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q) tsu(D-C)
th(C-D)
RXDi
Figure 5.10 Serial Interface
5.2.2.6 External Interrupt INTi Input
Table 5.32 External Interrupt INTi Input

Standard
Min. Max.
tw(INH) INTi input high pulse width 250 ns
tw(INL) INTi input low pulse width 250 ns
t w(INL)
INTi input
t w(INH)
Figure 5.11 External Interrupt INTi Input
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
5.2.2.7 Multi-master I2C-bus
Table 5.33 Multi-master I2C-bus

Standard Clock Mode Fast-mode
Min. Max. Min. Max.
tBUF Bus free time 4.7 1.3 μs
tHD;STA Hold time in start condition 4.0 0.6 μs
tLOW Hold time in SCL clock 0 status 4.7 1.3 μs
tR SCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns
tHD;DAT Data hold time 0 0 0.9 μs
tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs
fF SCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns
tsu;DAT Data setup time 250 100 ns
tsu;STA Setup time in restart condition 4.7 0.6 μs
tsu;STO Stop condition setup time 4.0 0.6 μs
SDA
t BUF t HD;STA t su;STO

t LOW
tR tF
p s Sr p
SCL
t HD;STA t HD;DAT t HIGH t su;DAT t su;STA
Figure 5.12 Multi-master I2C-bus
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Feb 07, 2011
VCC1 = VCC2 = 5V
Timing Requirements
5.2.3 Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)
Table 5.34 Memory Expansion Mode and Microprocessor Mode

Standard
Min. Max.
tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns
tac2(RD-DB) Data input access time (for setting with 1 to 3 waits) (Note 2) ns
tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns
tsu(DB-RD) Data input setup time 40 ns
tsu(RDY-BCLK) RDY input setup time 80 ns
th(RD-DB) Data input hold time 0 ns
th(BCLK-RDY) RDY input hold time 0 ns
Notes:
1. Calculated according to the BCLK frequency as follows:
9
0.5 × 10 - – 45 [ ns ]
---------------------
f ( BCLK )
9
( n + 0.5 ) × 10 - – 45 [ ns ] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
-----------------------------------
f ( BCLK )
9
( n – 0.5 ) × 10 - – 45 [ ns ] n is 2 for 2 waits setting, and 3 for 3 waits setting.
-----------------------------------
f ( BCLK )
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Feb 07, 2011
VCC1 = VCC2 = 5 V
Memory Expansion Mode and Microprocessor Mode
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR, WRL, WRH

(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH

(Multiplexed bus)
RDY input
tsu(RDY-BCLK) th(BCLK-RDY)
Measuring conditions
y VCC1 = VCC2 = 5 V
y Input timing voltage: VIL = 1.0 V, VIH = 4.0 V
y Output timing voltage: VOL = 2.5 V, VOH = 2.5 V
Figure 5.13 Timing Diagram
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Feb 07, 2011
VCC1 = VCC2 = 5 V
5.2.4 Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)
5.2.4.1 In No Wait State Setting
Table 5.35 Memory Expansion Mode and Microprocessor Mode (in No Wait State Setting)
Measuring Standard
Condition Min. Max.
td(BCLK-AD) Address output delay time 25 ns
th(BCLK-AD) Address output hold time (in relation to BCLK) 0 ns
th(RD-AD) Address output hold time (in relation to RD) 0 ns
th(WR-AD) Address output hold time (in relation to WR) (Note 2) ns
td(BCLK-CS) Chip select output delay time 25 ns
th(BCLK-CS) Chip select output hold time (in relation to BCLK) 0 ns
td(BCLK-ALE) ALE signal output delay time 15 ns
th(BCLK-ALE) ALE signal output hold time See −4 ns
td(BCLK-RD) RD signal output delay time Figure 5.14 25 ns
th(BCLK-RD) RD signal output hold time 0 ns
td(BCLK-WR) WR signal output delay time 25 ns
th(BCLK-WR) WR signal output hold time 0 ns
td(BCLK-DB) Data output delay time (in relation to BCLK) 40 ns
th(BCLK-DB) Data output hold time (in relation to BCLK) (3) 0 ns
td(DB-WR) Data output delay time (in relation to WR) (Note 1) ns
th(WR-DB) Data output hold time (in relation to WR) (3) (Note 2) ns
Notes:
9
0.5 × 10 - – 40 [ ns ] f
--------------------- (BCLK) is 12.5 MHz or less.
f ( BCLK )
9
0.5 × 10 - – 10 [ ns ]
---------------------
f ( BCLK )
3. This standard value shows the timing when the output is off, and does not
show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up (pull-down)
resistance value. R
Hold time of data bus is expressed in
t = −CR × ln(1−VOL/VCC2) DBi
by a circuit of the right figure. C
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold time of output
low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
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Feb 07, 2011
P0
P1
P2
P3 30 pF
P4
P5
P6
P7
P8
P9
P10
Figure 5.14 Ports P0 to P10 Measurement Circuit
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Feb 07, 2011
Memory Expansion Mode and Microprocessor Mode VCC1 = VCC2 = 5V

(in no wait state setting)
Read timing
BCLK
td(BCLK-CS) th(BCLK-CS)
25ns(max.) 0ns(min.)
CSi
tcyc
td(BCLK-AD) th(BCLK-AD)
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) th(RD-AD)
15ns(max.) -4ns(min.) 0ns(min.)
ALE
td(BCLK-RD) th(BCLK-RD)
RD
tac1(RD-DB)
(0.5 × t cyc - 45)ns(max.)
Hi-Z
DBi
tsu(DB-RD) th(RD-DB)
40ns(min.) 0ns(min.)
Write timing
BCLK
25ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE)
15ns(max.) -4ns(min.) th(WR-AD)
(0.5 × t cyc - 10)ns(min.)
ALE
td(BCLK-WR) th(BCLK-WR)
WR, WRL,
WRH
td(BCLK-DB) th(BCLK-DB)
Hi-Z
DBi
td(DB-WR) th(WR-DB)
(0.5 × t cyc - 40)ns(min.) (0.5 × t cyc - 10)ns(min.)
tcyc = 1
f(BCLK)
y VCC1 = VCC2 = 5V
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Feb 07, 2011
VCC1 = VCC2 = 5V
Switching Characteristics
5.2.4.2 In 1 to 3 Waits Setting and When Accessing External Area
Table 5.36 Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Measuring Standard
Condition Min. Max.
th(BCLK-ALE) ALE signal output hold time See -4 ns
th(WR-DB) Data output hold time (in relation to WR)(3) (Note 2) ns
Notes:
9
(-----------------------------------
n – 0.5 ) × 10 - – 40 [ ns ] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
f ( BCLK ) When n = 1, f(BCLK) is 12.5 MHz or less.

9
0.5 × 10 - – 10 [ ns ]
---------------------
f ( BCLK )
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
Hold time of data bus varies with capacitor volume and pull-up
(pull-down) resistance value.
R
t = −CR × ln(1 − VOL/VCC2) DBi
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
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Feb 07, 2011

(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
CSi
tcyc
ADi
BHE
ALE
RD
tac2(RD-DB)
{(n+0.5) × tcyc -45}ns(max.)
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD) 0ns(min.)
40ns(min.)
Write timing
BCLK
CSi
tcyc
ADi
BHE
(0.5 × t cyc-10)ns(min.)
ALE
WR, WRL,
WRH
td(BCLK-DB)
40ns(max.) th(BCLK-DB)
0ns(min.)
Hi-Z
DBi
td(DB-WR) th(WR-DB)
{(n-0.5) × tcyc -40}ns(min.) (0.5 × t cyc-10)ns(min.)
1
tcyc =
f(BCLK)
Measuring conditions n: 1 (when 1 wait)

y VCC1 = VCC2 = 5V 2 (when 2 waits)
y Input timing voltage: VIL = 0.8 V, VIH = 2.0 V 3 (when 3 waits)
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Feb 07, 2011
VCC1 = VCC2 = 5V
5.2.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 5.37 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Measuring Standard
Condition Min. Max.
th(RD-AD) Address output hold time (in relation to RD) (Note 1) ns
th(RD-CS) Chip select output hold time (in relation to RD) (Note 1) ns
th(WR-CS) Chip select output hold time (in relation to WR) (Note 1) ns
td(BCLK-RD) RD signal output delay time 25 ns
See
Figure 5.14
th(BCLK-DB) Data output hold time (in relation to BCLK) 0 ns
th(WR-DB) Data output hold time (in relation to WR) (Note 1) ns
td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) 15 ns
th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) −4 ns
td(AD-ALE) ALE signal output delay time (in relation to Address) (Note 3) ns
th(AD-ALE) ALE signal output hold time (in relation to Address) (Note 4) ns
td(AD-RD) RD signal output delay from the end of address 0 ns
td(AD-WR) WR signal output delay from the end of address 0 ns
tdz(RD-AD) Address output floating start time 8 ns
Notes:
9
0.5 × 10 - – 10 [ ns ]
---------------------
f ( BCLK )
9
( n – 0.5 ) × 10 - – 40 [ ns ] n is 2 for 2-wait setting, 3 for 3-wait setting.
-----------------------------------
f ( BCLK )
9
0.5 × 10 - – 25 [ ns ]
---------------------
f ( BCLK )
9
0.5 × 10 - – 15 [ ns ]
---------------------
f ( BCLK )
5. When using multiplex bus, set f(BCLK) 12.5 MHz or less.
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Feb 07, 2011

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK th(BCLK-CS)
td(BCLK-CS) th(RD-CS) 0ns(min.)
25ns(max.) tcyc
(0.5 × t cyc-10)ns(min.)
CSi
td(AD-ALE) th(ALE-AD)
(0.5 × t cyc-25ns(min.) (0.5 × t cyc-15ns(min.)
ADi Address Data input Address

/DBi tdz(RD-AD)
8ns(max.) th(RD-DB)
tac3(RD-DB) tsu(DB-RD) 0ns(min.)
{(n-0.5) × tcyc -45}ns(max.) 40ns(min.)
td(AD-RD)
td(BCLK-AD) 0ns(min.)
25ns(max.) th(BCLK-AD)
0ns(min.)
ADi
BHE
15ns(max.) th(RD-AD)
-4ns(min.)
(0.5 × t cyc-10)ns(min.)
ALE
RD
Write timing
BCLK
td(BCLK-CS) tcyc th(BCLK-CS)
25ns(max.) th(WR-CS) 0ns(min.)
(0.5 × t cyc-10)ns(min.)
CSi
ADi Address Data output Address
/DBi
td(AD-ALE) td(DB-WR) th(WR-DB)
(0.5 × t cyc-25ns(min.) {(n-0.5) × tcyc -40}ns(min.) (0.5 × t cyc-10)ns(min.)
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) td(AD-WR)
th(WR-AD)
(0.5 × t cyc-10)ns(min.)
ALE
WR, WRL,
WRH
Measuring conditions n: 2 (when 2 waits)

3 (when 3 waits)
y VCC1 = VCC2 = 5V
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Feb 07, 2011
5.3 Electrical Characteristics (VCC1 = VCC2 = 3 V)
5.3.1 Electrical Characteristics

VCC1 = VCC2 = 3 V
VCC1 = VCC2 = 2.7 to 3.3 V, VSS = 0 V at Topr = -20°C to 85°C/-40°C to 85°C, f(BCLK) = 25 MHz unless otherwise specified.
Standard
Min. Typ. Max.
VOH High P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4, IOH = −1 mA VCC1 − 0.5 VCC1 V
output P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = −1 mA VCC2 − 0.5 VCC2
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
VOH High output voltage XOUT HIGH POWER IOH = −0.1 mA VCC1 − 0.5 VCC1 V
LOW POWER IOH = −50 μA VCC1 − 0.5 VCC1
High output voltage XCOUT HIGH POWER With no load applied 2.6 V
LOW POWER With no load applied 2.2
VOL Low output P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7, P9_0 to IOL = 1 mA 0.5 V
voltage P9_7, P10_0 to P10_7
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOL = 1 mA 0.5
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7
CEC IOL = 1 mA 0 0.5 V
VOL Low output voltage XOUT HIGH POWER IOL = 0.1 mA 0.5 V
LOW POWER IOL = 50 μA 0.5
Low output voltage XCOUT HIGH POWER With no load applied 0 V
LOW POWER With no load applied 0
VT+-VT- Hysteresis HOLD, RDY, TA0IN to TA4IN, TB0IN to TB5IN, INT0 to 0.2 1.0 V
INT7, NMI, ADTRG, CTS0 to CTS2, CTS5 to CTS7,
SCL0 to SCL2, SCL5 to SCL7, SDA0 to SDA2, SDA5
to SDA7, CLK0 to CLK7, TA0OUT to TA4OUT, KI0 to
KI3, RXD0 to RXD2, RXD5 to RXD7, SIN3, SIN4, SD,
PMC0, PMC1, SCLMM, SDAMM, ZP, IDU, IDV, IDW
CEC 0.2 0.5 1.0 V
RESET 0.2 1.8 V
IIH High input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 3 V 4.0 μA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
− Leakage current in powered-off state CEC VCC1 = 0 V 1.8 μA
IIL Low input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V −4.0 μA
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7
RPULLUP Pull-up P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, VI = 0 V 50 80 150 kΩ
resistance P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7
RfXIN Feedback resistance XIN 3.0 MΩ
RfXCIN Feedback resistance XCIN 16 MΩ
VRAM RAM retention voltage In stop mode 1.8 V
Note:
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Feb 07, 2011
VCC1 = VCC2 = 3 V
R5F364A6NFA, R5F364A6NFB, R5F364A6DFA, R5F364A6DFB,
R5F364AENFA, R5F364AENFB, R5F364AEDFA, R5F364AEDFB
Standard
Min. Typ. Max.
the output pin are f(BCLK) = 25 MHz, A/D conversion
f(BCLK) = 20 MHz
Low-power mode f(BCLK) = 32 MHz
In low-power mode
160.0 μA
FMR 22 = FMR23 = 1
On flash memory (1)
f(BCLK) = 32 MHz
On RAM (1)
20.0 μA
Topr = 25°C
f(BCLK) = 32 MHz (oscillation capacity High)
8.0 μA
Topr = 25°C
f(BCLK) = 32 kHz (oscillation capacity Low)
4.0 μA
Topr = 25°C
1.6 μA
Topr = 25°C
memory program 20.0 mA
VCC1 = 3.0 V
VCC1 = 3.0 V
Note:
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Feb 07, 2011
VCC1 = VCC2 = 3 V
R5F364AKNFA, R5F364AKNFB, R5F364AKDFA, R5F364AKDFB
R5F364AMNFA, R5F364AMNFB, R5F364AMDFA, R5F364AMDFB
Standard
Min. Typ. Max.
XIN = 4.2 MHz (square wave),
In single-chip, mode, PLL multiplied by 6
the output pin are 125 kHz on-chip oscillator stopped 22.0 mA
open and other pins
are VSS
f(BCLK) = 25 MHz, A/D conversion

XIN = 4.2 MHz (square wave),
22.7 mA
PLL multiplied by 6
f(BCLK) = 20 MHz
Low-power mode f(BCLK) = 32 MHz
In low-power mode, FMR 22 = FMR23 = 1 170.0 μA
on flash memory (1)
f(BCLK) = 32 MHz
In low-power mode, 40.0 μA
on RAM (1)
20.0 μA
Topr = 25°C
f(BCLK) = 32 MHz (oscillation capacity High)
8.0 μA
Topr = 25°C
f(BCLK) = 32kHz (oscillation capacity Low)
4.0 μA
Topr = 25°C
1.6 μA
Topr = 25°C
memory program 20.0 mA
VCC1 = 3.0 V
VCC1 = 3.0 V
Note:
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Feb 07, 2011
VCC1 = VCC2 = 3 V
5.3.2 Timing Requirements (Peripheral Functions and Others)

5.3.2.1 Reset Input (RESET Input)
Table 5.41 Reset Input (RESET Input)

Standard
Min. Max.
tw(RSTL) RESET input low pulse width 10 μs
RESET input
t w(RTSL)
Figure 5.18 Reset Input (RESET Input)
5.3.2.2 External Clock Input
Table 5.42 External Clock Input (XIN Input) (1)

Standard
Min. Max.
tc External clock input cycle time 50 ns
tw(H) External clock input high pulse width 20 ns
tw(L) External clock input low pulse width 20 ns
tr External clock rise time 9 ns
tf External clock fall time 9 ns
Note:
1. The condition is VCC1 = VCC2 = 2.7 to 3.0 V.
XIN input
tf
tr t w(H) t w(L)
tc
Figure 5.19 External Clock Input (XIN Input)
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Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
5.3.2.3 Timer A Input
Table 5.43 Timer A Input (Counter Input in Event Counter Mode)

Standard
Min. Max.
Table 5.44 Timer A Input (Gating Input in Timer Mode)

Standard
Min. Max.
Table 5.45 Timer A Input (External Trigger Input in One-Shot Timer Mode)
Standard
Min. Max.
Table 5.46 Timer A Input (External Trigger Input in Pulse Width Modulation Mode and
Programmable Output Mode)
Standard
Min. Max.
tc(TA)
t w(TAH)
TAiIN input
t w(TAL)
tc(UP)
t w(UPH)
TAiOUT input
t w(UPL)
Figure 5.20 Timer A Input
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Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
Table 5.47 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
Standard
Min. Max.
tc(TA) TAiIN input cycle time 2 μs
tsu(TAIN-TAOUT) TAiOUT input setup time 500 ns
tsu(TAOUT-TAIN) TAiIN input setup time 500 ns
Two-phase pulse input in event counter mode

tc(TA)
TAiIN input
tsu(TAIN-TAOUT) tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
TAiOUT input
tsu(TAOUT-TAIN)
Figure 5.21 Timer A Input (Two-Phase Pulse Input in Event Counter Mode)
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Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
5.3.2.4 Timer B Input
Table 5.48 Timer B Input (Counter Input in Event Counter Mode)

Standard
Min. Max.
tc(TB) TBiIN input cycle time (counted on one edge) 150 ns
tw(TBH) TBiIN input high pulse width (counted on one edge) 60 ns
tw(TBL) TBiIN input low pulse width (counted on one edge) 60 ns
tc(TB) TBiIN input cycle time (counted on both edges) 300 ns
tw(TBH) TBiIN input high pulse width (counted on both edges) 120 ns
tw(TBL) TBiIN input low pulse width (counted on both edges) 120 ns
Table 5.49 Timer B Input (Pulse Period Measurement Mode)

Standard
Min. Max.
Table 5.50 Timer B Input (Pulse Width Measurement Mode)

Standard
Min. Max.
tc(TB)
t w(TBH)
TBiIN input
t w(TBL)
Figure 5.22 Timer B Input
R01DS0032EJ0200 Rev.2.00 Page 76 of 88

Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
5.3.2.5 Serial Interface
Table 5.51 Serial Interface

Standard
Min. Max.
tc(CK) CLKi input cycle time 300 ns
tw(CKH) CLKi input high pulse width 150 ns
tw(CKL) CLKi input low pulse width 150 ns
td(C-Q) TXDi output delay time 160 ns
th(C-Q) TXDi hold time 0 ns
tsu(D-C) RXDi input setup time 100 ns
th(C-D) RXDi input hold time 90 ns
tc(CK)
t w(CKH)
CLKi
t w(CKL)
th(C-Q)
TXDi
td(C-Q) tsu(D-C)
th(C-D)
RXDi
Figure 5.23 Serial Interface
5.3.2.6 External Interrupt INTi Input
Table 5.52 External Interrupt INTi Input

Standard
Min. Max.
tw(INH) INTi input high pulse width 380 ns
tw(INL) INTi input low pulse width 380 ns
t w(INL)
INTi input
t w(INH)
Figure 5.24 External Interrupt INTi Input
R01DS0032EJ0200 Rev.2.00 Page 77 of 88

Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
5.3.2.7 Multi-master I2C-bus
Table 5.53 Multi-master I2C-bus

Standard Clock Mode Fast-mode
Min. Max. Min. Max.
tBUF Bus free time 4.7 1.3 μs
tHD;STA Hold time in start condition 4.0 0.6 μs
tLOW Hold time in SCL clock 0 status 4.7 1.3 μs
tR SCL, SDA signals’ rising time 1000 20 + 0.1 Cb 300 ns
tHD;DAT Data hold time 0 0 0.9 μs
tHIGH Hold time in SCL clock 1 status 4.0 0.6 μs
fF SCL, SDA signals’ falling time 300 20 + 0.1 Cb 300 ns
tsu;DAT Data setup time 250 100 ns
tsu;STA Setup time in restart condition 4.7 0.6 μs
tsu;STO Stop condition setup time 4.0 0.6 μs
SDA
t BUF t HD;STA t su;STO

t LOW
tR tF
p s Sr p
SCL
t HD;STA t HD;DAT t HIGH t su;DAT t su;STA
Figure 5.25 Multi-master I2C-bus
R01DS0032EJ0200 Rev.2.00 Page 78 of 88

Feb 07, 2011
VCC1 = VCC2 = 3V
Timing Requirements
5.3.3 Timing Requirements (Memory Expansion Mode and Microprocessor

Mode)
Table 5.54 Memory Expansion Mode and Microprocessor Mode

Standard
Min. Max.
tac1(RD-DB) Data input access time (for setting with no wait) (Note 1) ns
tac2(RD-DB) Data input access time (for setting with wait) (Note 2) ns
tac3(RD-DB) Data input access time (when accessing multiplex bus area) (Note 3) ns
tsu(DB-RD) Data input setup time 50 ns
tsu(RDY-BCLK) RDY input setup time 85 ns
th(RD-DB) Data input hold time 0 ns
th(BCLK-RDY) RDY input hold time 0 ns
Notes:
9
0.5 × 10 - – 60 [ ns ]
---------------------
f ( BCLK )
9
( n + 0.5 ) × 10 - – 60 [ ns ] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
-----------------------------------
f ( BCLK )
9
( n – 0.5 ) × 10 - – 60 [ ns ] n is 2 for 2 waits setting, 3 for 3 waits setting.
-----------------------------------
f ( BCLK )
R01DS0032EJ0200 Rev.2.00 Page 79 of 88

Feb 07, 2011
VCC1 = VCC2 = 3 V
Memory Expansion Mode and Microprocessor Mode
(Effective in wait state setting)
BCLK
RD
(Separate bus)
WR, WRL, WRH

(Separate bus)
RD
(Multiplexed bus)
WR, WRL, WRH

(Multiplexed bus)
RDY input
tsu(RDY-BCLK) th(BCLK-RDY)
y VCC1 = VCC2 = 3 V
R01DS0032EJ0200 Rev.2.00 Page 80 of 88

Feb 07, 2011
VCC1 = VCC2 = 3 V
5.3.4 Switching Characteristics (Memory Expansion Mode and Microprocessor

Mode)
5.3.4.1 In No Wait State Setting
Table 5.55 Memory Expansion and Microprocessor Modes (in No Wait State Setting)
Measuring Standard
Condition Min. Max.
th(BCLK-ALE) ALE signal output hold time See −4 ns
Notes:
9
0.5 × 10 - – 40 [ ns ] f(BCLK) is 12.5 MHz or less.
---------------------
f ( BCLK )
9
0.5 × 10 - – 10 [ ns ]
---------------------
f ( BCLK )
3. This standard value shows the timing when the output is off, and
does not show hold time of data bus.
(pull-down) resistance value. R
t = −CR × ln(1 − VOL/VCC2) DBi
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ,
hold time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
R01DS0032EJ0200 Rev.2.00 Page 81 of 88

Feb 07, 2011
P0
P1
P2
P3 30 pF
P4
P5
P6
P7
P8
P9
P10
Figure 5.27 Ports P0 to P10 Measurement Circuit
R01DS0032EJ0200 Rev.2.00 Page 82 of 88

Feb 07, 2011

(in no wait state setting)
Read timing
BCLK
CSi
tcyc
ADi
BHE
ALE
RD
tac1(RD-DB)
(0.5 × t cyc-60)ns(max.)
Hi-Z
DBi
tsu(DB-RD) th(RD-DB)
50ns(min.) 0ns(min.)
Write timing
BCLK
30ns(max.)
0ns(min.)
CSi
tcyc
ADi
BHE
(0.5 × t cyc-10)ns(min.)
ALE
WR, WRL,
WRH
Hi-Z
DBi
td(DB-WR) th(WR-DB)
(0.5 × t cyc-40)ns(min.) (0.5 × t cyc-10)ns(min.)
tcyc = 1
f(BCLK)
y VCC1 = VCC2 = 3V
R01DS0032EJ0200 Rev.2.00 Page 83 of 88

Feb 07, 2011
VCC1 = VCC2 = 3V
5.3.4.2 In 1 to 3 Waits Setting and When Accessing External Area
Table 5.56 Memory Expansion Mode and Microprocessor Mode (in 1 to 3 Waits Setting and When
Accessing External Area)
Measuring Standard
Condition Min. Max.
th(BCLK-ALE) ALE signal output hold time See -4 ns
Notes:
9
(-----------------------------------
n – 0.5 ) × 10 - – 40 [ ns ] n is 1 for 1 wait setting, 2 for 2 waits setting and 3 for 3 waits setting.
f ( BCLK ) When n = 1, f(BCLK) is 12.5 MHz or less.

9
0.5 × 10 - – 10 [ ns ]
---------------------
f ( BCLK )
3. This standard value shows the timing when the output is off,
and does not show hold time of data bus.
(pull-down) resistance value.
R
t=−CR × ln(1−VOL/VCC2) DBi
For example, when VOL = 0.2VCC2, C = 30 pF, R = 1 kΩ, hold
time of output low level is
t = −30 pF × 1 kΩ × In(1 − 0.2VCC2/VCC2)
= 6.7 ns.
R01DS0032EJ0200 Rev.2.00 Page 84 of 88

Feb 07, 2011

(in 1 to 3 waits setting and when accessing external area)
Read timing
BCLK
CSi
tcyc
ADi
BHE
ALE
RD
tac2(RD-DB)
{(n+0.5) × tcyc -60}ns(max.)
Hi-Z
DBi
th(RD-DB)
tsu(DB-RD) 0ns(min.)
50ns(min.)
Write timing
BCLK
CSi
tcyc
ADi
BHE
(0.5 × t cyc-10)ns(min.)
ALE
WR, WRL,
WRH
td(BCLK-DB)
40ns(max.) th(BCLK-DB)
0ns(min.)
Hi-Z
DBi
td(DB-WR) th(WR-DB)
{(n-0.5) × tcyc -40}ns(min.) (0.5 × t cyc-10)ns(min.)
1
tcyc =
f(BCLK)
Measuring conditions n: 1 (when 1 wait)

y Input timing voltage: VIL = 0.6 V, VIH = 2.4 V 3 (when 3 waits)
R01DS0032EJ0200 Rev.2.00 Page 85 of 88

Feb 07, 2011
VCC1 = VCC2 = 3V
5.3.4.3 In 2 or 3 Waits Setting, and When Accessing External Area and Using
Multiplexed Bus
Table 5.57 Memory Expansion Mode and Microprocessor Mode (in 2 or 3 Waits Setting, and When
Accessing External Area and Using Multiplexed Bus) (5)
Measuring Standard
Condition Min. Max.
th(RD-AD) Address output hold time (in relation to RD) (Note 1) ns
th(RD-CS) Chip select output hold time (in relation to RD) (Note 1) ns
th(WR-CS) Chip select output hold time (in relation to WR) (Note 1) ns
td(BCLK-RD) RD signal output delay time 40 ns
See
Figure 5.27
th(BCLK-DB) Data output hold time (in relation to BCLK) 0 ns
th(WR-DB) Data output hold time (in relation to WR) (Note 1) ns
td(BCLK-ALE) ALE signal output delay time (in relation to BCLK) 25 ns
th(BCLK-ALE) ALE signal output hold time (in relation to BCLK) −4 ns
td(AD-ALE) ALE signal output delay time (in relation to Address) (Note 3) ns
th(AD-ALE) ALE signal output hold time (in relation to Address) (Note 4) ns
td(AD-RD) RD signal output delay from the end of address 0 ns
td(AD-WR) WR signal output delay from the end of address 0 ns
tdz(RD-AD) Address output floating start time 8 ns
Notes:
9
0.5 × 10
1. Calculated according to the BCLK frequency as follows: ---------------------- – 10 [ ns ]
f ( BCLK )
9
( n – 0.5 ) × 10 - – 50 [ ns ]
----------------------------------- n is 2 for 2 waits setting, 3 for 3 waits setting.
f ( BCLK )
9
3.
0.5 × 10
Calculated according to the BCLK frequency as follows: ---------------------- – 40 [ ns ]
f ( BCLK )
9
4.
0.5 × 10
Calculated according to the BCLK frequency as follows: ---------------------- – 15 [ ns ]
f ( BCLK )
5. When using multiplexed bus, set f(BCLK) 12.5 MHz or less.
R01DS0032EJ0200 Rev.2.00 Page 86 of 88

Feb 07, 2011

(in 2 or 3 waits setting, and when accessing external area and using multiplexed bus )
Read timing
BCLK th(BCLK-CS)
td(BCLK-CS) th(RD-CS) 0ns(min.)
50ns(max.) tcyc
(0.5 × t cyc-10)ns(min.)
CSi
td(AD-ALE) th(ALE-AD)
(0.5 × t cyc-40ns(min.) (0.5 × t cyc-15ns(min.)
ADi Address Data input Address

/DBi tdz(RD-AD)
8ns(max.) th(RD-DB)
tac3(RD-DB) tsu(DB-RD) 0ns(min.)
{(n-0.5) × tcyc -60}ns(max.) 50ns(min.)
td(AD-RD)
td(BCLK-AD) 0ns(min.)
50ns(max.) th(BCLK-AD)
0ns(min.)
ADi
BHE
25ns(max.) th(RD-AD)
-4ns(min.)
(0.5 × t cyc-10)ns(min.)
ALE
RD
Write timing
BCLK
td(BCLK-CS) tcyc th(BCLK-CS)
50ns(max.) th(WR-CS) 0ns(min.)
(0.5 × t cyc-10)ns(min.)
CSi
ADi Address Data output Address
/DBi
td(AD-ALE) td(DB-WR) th(WR-DB)
(0.5 × t cyc-40ns(min.) {(n-0.5) × tcyc -50}ns(min.) (0.5 × t cyc-10)ns(min.)
ADi
BHE
td(BCLK-ALE) th(BCLK-ALE) td(AD-WR)
th(WR-AD)
(0.5 × t cyc-10)ns(min.)
ALE
WR, WRL,
WRH
1
tcyc =
f(BCLK)
Measuring conditions n: 2 (when 2 waits)

R01DS0032EJ0200 Rev.2.00 Page 87 of 88

Feb 07, 2011
M16C/64A Group Appendix 1. Package Dimensions
Appendix 1. Package Dimensions

The information on the latest package dimensions or packaging may be obtained from “Packages“ on the
Renesas Electronics website.
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-QFP100-14x20-0.65 PRQP0100JD-B 100P6F-A 1.8g
HD
*1
D
80 51
81 50
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
HE
E
*2
Reference Dimension in Millimeters

ZE
Symbol
Min Nom Max
100
31
D 19.8 20.0 20.2
E 13.8 14.0 14.2
A2 2.8
1
ZD Index mark
30 c HD 22.5 22.8 23.1
F
HE 16.5 16.8 17.1
A2
A 3.05
A1 0 0.1 0.2
A
bp 0.25 0.3 0.4

A1
L c 0.13 0.15 0.2

e *3
bp 0° 10°
y x Detail F e 0.65
x 0.13
y 0.10
ZD 0.575
ZE 0.825
L 0.4 0.6 0.8
JEITA Package Code RENESAS Code Previous Code MASS[Typ.]

P-LQFP100-14x14-0.50 PLQP0100KB-A 100P6Q-A / FP-100U / FP-100UV 0.6g
HD
*1
D
75 51
NOTE)
1. DIMENSIONS "*1" AND "*2"
76 50 DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
bp
b1
HE
E
Reference Dimension in Millimeters

*2
c1
Symbol
c
Min Nom Max

D 13.9 14.0 14.1
E 13.9 14.0 14.1
Terminal cross section A2 1.4
HD 15.8 16.0 16.2
100 HE
26 15.8 16.0 16.2
ZE
A 1.7
1 25 A1 0.05 0.1 0.15
Index mark bp 0.15 0.20 0.25
ZD
F b1 0.18
c 0.09 0.145 0.20
c1 0.125
A2
A
0° 8°
c
e 0.5
y *3 x 0.08
A1
e bp L
x
L1 y 0.08
ZD 1.0
Detail F
ZE 1.0
L 0.35 0.5 0.65
L1 1.0
R01DS0032EJ0200 Rev.2.00 Page 88 of 88

Feb 07, 2011
REVISION HISTORY M16C/64A Group Datasheet
Description
Rev. Date
Page Summary
1.01 Feb 03, 2009 - First Edition issued.
1.10 Jul 15, 2009 - Watchdog Timer Reset Register → Watchdog Timer Refresh Register
3 Table 1.2 Specifications for the 100-Pin Package (2/2) partially modified
4 Table 1.3 Product List partially modified
5 Figure 1.2 Marking Diagram (Top View) partially modified
18 Figure 3.2 Memory Map 13800h → 13000h
20 Table 4.1 “SFR Information (1/16)” reset value in VCR1 modified
21 Table 4.2 “SFR Information (2/16)” partially modified
29 Table 4.10 “SFR Information (10/16)” reset value in S11 modified
37 Table 5.1 Absolute Maximum Ratings partially modified
38 Table 5.2 Recommended Operating Conditions (1/3) partially modified
39 Table 5.3 Recommended Operating Conditions (2/3) partially modified
40 Table 5.4 Recommended Operating Conditions (3/3) added
40 Figure 5.1 Ripple Waveform added
41 Table 5.5 A/D Conversion Characteristics (1/2) partially modified
41 Figure 5.2 A/D Accuracy Measure Circuit added
42 Table 5.6 A/D Conversion Characteristics (2/2) partially modified
44 Table 5.8 CPU Clock When Operating Flash Memory (f(BCLK)) partially modified
44 Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics notes modified
46 Table 5.11 Voltage Detector 0 Electrical Characteristics partially modified
47 Table 5.14 Power-On Reset Circuit partially modified
48 Figure 5.3 Power-On Reset Circuit Electrical Characteristics partially modified
50 Table 5.16 125 kHz On-Chip Oscillator Circuit Electrical Characteristics partially modified
53 Table 5.19 Electrical Characteristics (3) partially modified
55 5.2.2.1 Reset Input (RESET Input) added
73 5.3.2.1 Reset Input (RESET Input) added
Same modifications made to both 3 V and 5 V specifications.
2.00 Feb 07, 2011 Overall 001Ah Voltage Detector Operation Enable Register: Changed reset value from “000X
0000b”.
Overall 002Ah Voltage Monitor 0 Control Register: Changed reset value from “1100 XX10b”.
Overall 002Bh Voltage Monitor 1 Control Register: Changed reset value from “1000 1X10b”.
Overall 0324h Increment/Decrement Flag: Changed name from Up/Down Flag.
Overall 033Eh Timer B2 Special Mode Register: Changed reset value from “XX00 0000b”.
Overall 03A2h Open-Circuit Detection Assist Function Register: Changed reset value from “XXXX
XX00b”.
Overall 03DCh D/A Control Register: Changed reset value from “XXXX XX00b”.
Overall D08Ah to D08Bh PMC0 Counter Value Register: Deleted.
Overall D09Eh to D09Fh PMC1 Counter Value Register: Deleted.
Overall Changed “high-speed clock mode” to “fast-mode”.
Overview
3 Table 1.2 Specifications for the 100-Pin Package (2/2): Deleted note 1.
4 Table 1.3 Product List: Added the new part numbers.
5 Figure 1.1 Part No., with Memory Size and Package: Added “K” to the Memory capacity.
11 Table 1.6 Pin Functions for the 100-Pin Package (1/3): Changed the description of HOLD
pin.
A-1
REVISION HISTORY M16C/64A Group Datasheet
Description
Rev. Date
Page Summary
2.00 Feb 07, 2011 Address Space
18 Figure 3.2 Memory Map:
• Added the address of 384 KB version.
• Added note 1 and 3 to the reserved areas.
Special Function Registers (SFRs)
20 Table 4.1 SFR Information (1) (1):
• Deleted “the VCR1 register, the VCR2 register” from note 2.
• Deleted notes 5 to 6 and added note 5.
21 Table 4.2 SFR Information (2) (1): Deleted notes 2 to 7 and added note 2.
38 4.2.1 Register Settings: Added the description regarding read-modify-write instructions.
39 Table 4.20 Read-Modify-Write Instructions: Added.
Electrical Characteristics
40 Table 5.1 Absolute Maximum Ratings:
Added a row for the data area value to Topr (Flash program erase).
41 Table 5.2 Recommended Operating Conditions (1/3):
Added rows for the CEC value to VCC1, VCC2, VIH, and VIL.
45 Table 5.9 Flash Memory (Program ROM 1, 2) Electrical Characteristics:
Added a condition to the Read voltage row.
48 Table 5.14 Power-On Reset Circuit:
• Added the tw(por) row.
• Added the last line in note 1.
48 Figure 5.3 Power-On Reset Circuit Electrical Characteristics: Deleted note 2.
52 Table 5.18 Electrical Characteristics (2) (1): Added “ZP, IDU, IDV, IDW” to the VT+-VT- row.
54 Table 5.20 Electrical Characteristics (4): Added new part numbers above the table.
60, 78 Table 5.33 and Table 5.53 Multi-master I2C-bus: Added.
61 Table 5.34 Memory Expansion Mode and Microprocessor Mode:
Changed RDY input setup time from 30.
61 to 68, Table 5.34 to Table 5.37 and Table 5.54 to Table 5.57 Memory Expansion Mode and
79 to 86 Microprocessor Mode:
Deleted the following:
• HOLD input setup time
• HOLD input hold time
• HLDA output delay time
62, 80 Figure 5.13 and Figure 5.26 Timing Diagram:
Deleted lower figure (Common to wait state and no wait state settings).
70 Table 5.38 Electrical Characteristics (1) (1):
• Added rows for the CEC value to Leakage current in powered-off state, VT+-VT-, and
VOL.
• Added “ZP, IDU, IDV, IDW” to the VT+-VT- row.
71 Table 5.39 Electrical Characteristics (2): Changed “VCC1 = 5.0 V” to "VCC1 = 3.0 V" in the
During flash memory program and During flash memory erase rows.
72 Table 5.40 Electrical Characteristics (3):
• Added new part numbers above the table.
• Changed “VCC1 = 5.0 V” to "VCC1 = 3.0 V" in the During flash memory program and
During flash memory erase rows.
79 Table 5.54 Memory Expansion Mode and Microprocessor Mode:
Changed RDY input setup time from 40.
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HDMI and High-Definition Multimedia Interface are registered trademarks of HDMI Licensing, LLC.
A-2
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or
technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or
others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to
the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is
prohibited under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics
assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product
depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas
Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the
use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics.
The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.
"Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools;
personal electronic equipment; and industrial robots.
"High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically
designed for life support.
"Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical
implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage
range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the
use of Renesas Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and
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please evaluate the safety of the final products or system manufactured by you.
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(Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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Tel: +82-2-558-3737, Fax: +82-2-558-5141
© 2011 Renesas Electronics Corporation. All rights reserved.

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Datasheet

R01DS0032EJ0200 Rev.2.00 Page 1 of 88

Table 1.1 Specifications for the 100-Pin Package (1/2)

R01DS0032EJ0200 Rev.2.00 Page 2 of 88

Table 1.2 Specifications for the 100-Pin Package (2/2)

R01DS0032EJ0200 Rev.2.00 Page 3 of 88

1.3 Product List

Table 1.3 Product List As of December 2010

Previous package codes are as follows:

R01DS0032EJ0200 Rev.2.00 Page 4 of 88

M16C/64A Group (100 pins)

Figure 1.1 Part No., with Memory Size and Package

Week code (from 01 to 54)

Last digit of year

Figure 1.2 Marking Diagram (Top View)

R01DS0032EJ0200 Rev.2.00 Page 5 of 88

1.4 Block Diagram

Port P0 Port P1 Port P2 Port P3 Port P4 Port P5

Internal peripheral functions System clock generator

Three-phase motor control Multi-master I2C-bus interface

Real-time clock CRC calculator

Watchdog timer On-chip debugger

A/D converter M16C/60 Series CPU core Memory

Port P10 Port P9 Port P8 Port P7 Port P6

Figure 1.3 Block Diagram for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00 Page 6 of 88

1.5 Pin Assignments

P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]

P2_6/AN2_6/A6, [A6/D6], [A6/D5]

Figure 1.4 Pin Assignment for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00 Page 7 of 88

P2_4/INT6/AN2_4/A4, [A4/D4], [A4/D3]

P2_6/AN2_6/A6, [A6/D6], [A6/D5]

Figure 1.5 Pin Assignment for the 100-Pin Package

R01DS0032EJ0200 Rev.2.00 Page 8 of 88

Table 1.4 Pin Names for the 100-Pin Package (1/2)

R01DS0032EJ0200 Rev.2.00 Page 9 of 88

Table 1.5 Pin Names for the 100-Pin Package (2/2)

R01DS0032EJ0200 Rev.2.00 Page 10 of 88

1.6 Pin Functions

Table 1.6 Pin Functions for the 100-Pin Package (1/3)

R01DS0032EJ0200 Rev.2.00 Page 11 of 88

Table 1.7 Pin Functions for the 100-Pin Package (2/3)

BCLK output BCLK O VCC2 Outputs the BCLK signal.

R01DS0032EJ0200 Rev.2.00 Page 12 of 88

Table 1.8 Pin Functions for the 100-Pin Package (3/3)

Serial CLK3, CLK4 I/O VCC1 Transmit/receive clock I/O.

R01DS0032EJ0200 Rev.2.00 Page 13 of 88

2. Central Processing Unit (CPU)

R3 R1H (upper bits of R1) R1L (lower bits of R1)

INTBH is the 4 upper bits of the INTB register and INTBL

USP User stack pointer

Figure 2.1 CPU Registers

R01DS0032EJ0200 Rev.2.00 Page 14 of 88

2.1 Data Registers (R0, R1, R2, and R3)

2.2 Address Registers (A0 and A1)

2.3 Frame Base Register (FB)

2.4 Interrupt Table Register (INTB)

2.5 Program Counter (PC)