dsPIC33 DSCs

Digital Power Update

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MCU16 Business Unit

Silicon Roadmap
dsPIC® Digital Signal Controllers
dsPIC33 DSC Evolution
Increasing Performance and Integration with each generation

dsPIC33F dsPIC33E dsPIC33C dsPIC33A

• 40 MHz • 70 MHz • 100 MHz • 200 MHz

• 16-bit CPU • 16-bit CPU • 16-bit CPU • 32-bit CPU and 32/64-bit FPU

• Single core • Single core • Single/dual cores • Single/dual cores

• Flexible PWMs • Improved PWMs • Improved PWMs • Improved PWM resolution

• Multiple S/H 10-bit ADC • 300 Ksps 12-bit ADCs • 3.5 Msps 12-bit ADCs • 40 Msps 12-bit ADCs
• Integrated Op-Amps • 20 MHz Op Amps & PGAs • 100 MHz Op-Amps, more CMPs
• PWM resolution 250pS • PWM resolution down to 80pS
• Functional safety • Improved Functional Safety
• Integrated Security
• Up to 256KB Flash • Up to 512 KB Flash
• Up to 1MB Flash • Up to 4MB Flash

3
Microchip Proprietary and Confidential
 Concept Samples

dsPIC33 DSC Roadmap Development Production

dsPIC33AH4096MPS9
Dual-Core / MPU+PPU

dsPIC33AK4096MPS6
dsPIC33CK1024MP7 dsPIC33CH1024MP7 dsPIC33AK1024MPS6 1-4MB ECC Flash,
512KB - 1MB ECC Flash, 512 – 1MB + 128K ECC Flash 512KB - 1MB ECC Flash, 736KB ECC RAM BIST,
dsPIC33EP128GS8 64 - 128KB RAM BIST, 124K + 60KB RAM BIST 5x12-bit ADC, Op-Amps,I3C
256KB ECC RAM BIST, 3xCAN-
64 - 128KB Flash, Single Core, DACs, Dual Core, 2xCAN-FD, Safety, FD, Touch, Security, I3C, Eth HSM, Ethernet, 3xCAN-FD
8KB RAM Op-Amps, 2xCAN-FD SW-Touch, Boot, OTP T1S, ISO 26262 compliant, 64/100/128/144/176 pins
Live Update, PTG, CLC 48/64/80/100 pins 48/64/80/100/128 pins Safety,
DACs, PGAs, 2xCAN
64/80/100/128 pins
28/44/48/64/80 pins dsPIC33CK512MP6 dsPIC33CH512MP5
Features / Memory

256 - 512KB ECC Flash, 256 - 512KB ECC Flash, dsPIC33AK512MPS5

dsPIC33FJ64GS6 dsPIC33EP64GS5 32 - 64KB RAM BIST, 48K RAM, 72K PRAM BIST,
32 - 64KB Flash, 256 - 512KB ECC Flash, 64KB
16 - 64KB Flash, Single Core, DACs, Dual Core, Dual Motor DACs,
4 - 9KB RAM ECC RAM BIST, Safety, 2xCAN-
2 - 8KB RAM Op-Amps, 2xCAN-FD PGAs, 2xCAN-FD.
DAC, DMA, FDs, Touch, Security,
Live Update, 48/64/80 pins 48/64/80 pins
CAN ISO 26262 compliant,
DACs, PGAs,
64/80/100 pins 48/64/80/100/128 pins
28/44/48/64 pins dsPIC33CK256MPE506
EEPROM
dsPIC33FJ16GS5 dsPIC33AK256MPS3
6 - 16KB Flash dsPIC33CK256MP508 128 - 256KB ECC Flash
0.25 - 2KB RAM 256KB ECC Flash, 24KB RAM 64KB ECC RAM BIST
DAC BIST, ADCs, CAN-FD, SENT, Single Core, Crypto, I3C
18/28/44 pins OTP, Sec. Boot, Touch, Safety DACs, PGAs
28/36/48/64/80 pins 36/48/64 pins

dsPIC33FJ09GS3 dsPIC33EP32GS2 dsPIC33CK64MP105 dsPIC33CH128MP5 dsPIC33AK128MC1

6 - 9KB Flash 16 - 32KB Flash 32 - 64KB ECC Flash 64 - 128KB ECC Flash, 332 - 128KB ECC Flash
0.25 – 1KB RAM 2KB RAM PGAs 8KB RAM BIST 16K RAM, 24K PRAM BIST, 8 - 16KB ECC RAM BIST
DAC, 4x4mm package option ADC, SENT, LIN, OTP, Boot Dual Core, Dual Motor, DACs, OPAs, CMP/DAC, Safety,
40 MHz only 28 pins SW CVD-Touch, Safety PGAs, CAN-FD Sec. Boot,
18/20/28/36 pins 28/36/48 pins 28/36/48/64/80 pins 28/36/48/64 pins

100 MHz 200 MHz, 32-bit with Double Precision FPU

40 – 70 MHz Integration
dsPIC33CK Single Core / dsPIC33CH Dual Core dsPIC33AK Single Core / dsPIC33AH Dual Core

4
Microchip Proprietary and Confidential
dsPIC33 C Family Features
• DSC optimized for digital power and motor control applications
• High-speed 12-bit ADCs (285ns) and High-resolution PWMs (250ps)
• 40-bit accumulators for unprecedented intermediate precision
• Highly parallel CPU architecture: up to 8 operations per clock (per core)
• Sustainable 100 MMACS performance (per core)

• Single and Dual core versions

• 32 – 1MB Flash Memory
• 28 lead packages as small as 4x4mm
• Optimized for Telecom’s IPC-9592B second-level qualification requirements

• Up to 128 lead packages

dsPIC33C Family
Single Core dsPIC33CK Dual Core dsPIC33CH
64KB 48KB 16KB
512KB 512KB 72KB
Data DMA Data DMA DMA Data
Flash Flash PRAM
RAM RAM RAM

MEMORY BUS MEMORY BUS MEMORY BUS

PWMS PWMS PWMS

ADCs ADC Main Secondary ADCs

dsPIC33C

PERIPHERAL BUS
PERIPHERAL BUS
PERIPHERAL BUS

Comps Comp dsPIC33C dsPIC33C Comps

Core
OpAmps Core Core PGAs
100 MHz
I2C I2C 90 MHz 100 MHz I2C

CAN-FD CAN-FD SPI

Mailbox
Mailbox UART
SPIs SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs UARTs SCCP

SCCP SCCP M –> S FIFO Out Cmp

Timer Timer S –> M FIFO Timer

The dsPIC33CH Family
• Two dsPIC33 cores per device
• Increases overall performance
• Can be used to optimize control loop responsiveness
• Enables software partitioning
• Familiar programming model – both run same flexible instruction set

• Loosely-coupled asymmetric multiprocessing architecture

• Asymmetric performance (main core vs. secondary core)
• Private peripherals for each core
• Separate debug ports per core
• Autonomous operation of cores
dsPIC33CH512
Dual Digital Signal Controllers with Peripherals
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

CAN-FD SPI

SPIs UART

UARTs SCCP

SCCP Out Cmp

Timer Timer
dsPIC33CH512
Main / Secondary Interface (MSI)
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

CAN-FD SPI
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

Configurable direction for all 16 mailboxes

Configurable interrupt operation for mailboxes & FIFOs
dsPIC33CH512
Main / Secondary Interface (details)
Direct interrupt requests (MTSIRQ & STMIRQ)
Main Secondary
• ~ 11 cycles of latency from the initiator’s perspective
dsPIC33CH dsPIC33CH
Core Core
90 MHz 100 MHz
16 mailboxes each with configurable direction
• Configurable for interrupts to the other side upon write
• 4 cycles latency until data available on other side
• DMA transfer compatible
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes

Two 32-word unidirectional FIFOs

• Circular operation with empty and full status and interrupts
• Overflow/underflow detection with interrupts to each core
• 3 cycles latency until data available on other side
• DMA transfer compatible
M –> S FIFO

S –> M FIFO
dsPIC33CH512 MP Main Core Peripherals
Main Core’s Dedicated Peripherals
48KB 6 General DMA channels
512KB
Data DMA 2 CAN-FD (with 2 dedicated DMA channels)
Flash
RAM
2 SENT
MEMORY BUS 2 SPI with I2S support
2 I2C with PMBus support
Main 2 UARTs
PERIPHERAL BUS
dsPIC33CH 1 Peripheral Trigger Generator (PTG)
Core
4 Configurable Logic Cells (CLCs)
90 MHz
1 QEI (Quadrature Encoder Interface)
8 SCCPs - 32 bit-timer/Cap/Compare
1 CRC Module
1 12-bit ADC with up to 18 channels
1 Analog Comparator w/ 12-bit DAC
1 DAC output buffer (shared across cores)
8 PWM Generators
64 x 48 bits of OTP Flash
dsPIC33CH512 MP Secondary Core Peripherals
Secondary Core’s Dedicated Peripherals
3 12-bit ADCs w/ up to 18 channels 72KB
16KB
DMA Data
PRAM
3 Analog Comparators with 12-bit DACs RAM

3 PGAs (can share with main core) MEMORY BUS

8 PWM Generators
Secondary
4 Configurable Logic Cells (CLCs)

PERIPHERAL BUS
dsPIC33CH
1 QEI (Quadrature Encoder interfaces) Core
4 SCCPs - 32 bit-timer/Cap/Compare 100 MHz
1 16-bit Timer
2 Channel DMA
1 SPI with I2S support
1 UART
1 I2C with PMBus support
1 Deadman Timer
dsPIC33CH Family
Core vs Chip-wide Events
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

CAN-FD SPI
WDT & DMT WDT & DMT
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

Each core has its own WDT & DMT

BOR, POR, MCLR are chip-wide events
dsPIC33CH Family
Shared PGAs
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

CAN-FD SPI
WDT & DMT WDT & DMT
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

3 Programmable Gain Amplifiers configured by secondary core

Each can feed secondary or main core ADC or analog comparators
dsPIC33CH Family
Shared DACOUT DAC Output to an
external pin
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

CAN-FD SPI
WDT & DMT WDT & DMT
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

Any of the 4 DACs from the comparators or either of the

PGA outputs can drive the DAC output buffer to a pin
dsPIC33CH Family
Peripheral Pin Select
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

Peripheral Pin Select

Peripheral Pin Select

CAN-FD SPI
WDT & DMT WDT & DMT
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

Each core has its own peripheral pin select (PPS) mux to
select which peripherals connect the outside
dsPIC33CH Family
Pin Ownership Mux
48KB 16KB
512KB 72KB
Data DMA DMA Data
Flash PRAM
RAM RAM

MEMORY BUS MEMORY BUS

PWMS PWMS
ADC Main Secondary ADCs

PERIPHERAL BUS
PERIPHERAL BUS
Comp dsPIC33CH dsPIC33CH Comps

Core Core PGAs

I2C 90 MHz 100 MHz I2C

Peripheral Pin Select

Peripheral Pin Select

CAN-FD SPI
WDT & DMT WDT & DMT
Mailbox
Mailbox UART
SPIs Mailbox
Mailbox
Mailbox
Mailbox
Mailbox
Mailboxes
UARTs SCCP

SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

PIN OWNERSHIP MUX

dsPIC33C Family
C-Core CPU Enhancements

• Hardware context switch extended to include DSP accumulators and status

• Data limit instructions (single cycle clamping)
• Accumulator 32-bit data load/store instructions
• Accumulator normalization instruction
• Faster / more compiler-efficient divide instructions
• Bit field instructions
• Dual-core support instruction
dsPIC33C Family Working Registers
IPLz
Context-Selected Register Sets Main
IPLw
IPLx
W0
IPLy
W0
W0
W1
W0
W1
W0
W1
W2
W1 W2
W1 W2 W3
W2 W3
W2 W3 W4
W3 W4
• Enables nearly instantaneous context switches W3
W4
W4
W5
W4
W5
W5
W6
W5
W6
W5 W6 W7
W6 W7
W6 W7 W8
W7 W8
• Four additional register sets W7
W8
W8
W9
W8
W9
W9
W10
W9
W10
W9 W10 W11
• Each assigned to specific interrupt priority level W10
W11
W10
W11
W11
W12
W11
W12
W12
W13
W12 W13
• Persistent data from one interrupt service routine (ISR) W12
W13
W13
W13
W14
W14
W14
W14
invocation to the next Frame Ptr / W14
Stack Ptr / W15
• Reduces saving and restoring register contents Accumulators
AccA
IPLz
AccB
IPLy AccA
• Accelerates compensators up to 50% IPLx
AccB
AccA
AccB
AccA
• Significantly reduces control-loop latencies IPLw
AccB
AccA
Main
AccB
AD39 AD31 AD15 AD0
Status Register
IPLz
IPLy
IPLx
IPLw
Main
MSB context selected LSB stacked
dsPIC33C Family
12-Bit ADC
• 285ns latency
• 3.5 MSPS per SAR
• Up to 24 analog inputs each with a dedicated result register
• Multiple and flexible trigger options
• PWM Primary and Secondary Trigger
• Timer Period Match
• Output Compare event trigger
• PWM special event trigger
• PWM Current-Limit event trigger
• External trigger event from device pin
• Software trigger
• Four digital comparators with interrupts:
• Multiple comparison options
• Four oversampling filters with interrupts:
• Provides increased resolution
dsPIC33CH Family
Programmable Gain Amps
• Configured by secondary core
• Non-inverting amps with 8 selectable gains
• Output can be read by dedicated S&H circuits
• Output can be input to analog comparators
• Output can be routed to DACOUTx pin

Gain Typical Bandwidth (-3dB)

4x 10 MHz
6x 6.7 MHz
8x 5.0 MHz
12x 3.3 MHz
16x 2.5 MHz
24x 1.7 MHz
32x 1.3 MHz
48x 0.8 MHz
dsPIC33C Family
High Speed 12-bit DAC
• Generates reference voltage waveforms for analog comparators
• Can be used for slope compensation in peak current mode topologies
Inductor current sense

Programmable waveforms:

DAC

Control
• 2V Step Response Design Targets:
• Settle to ± 30 mV in 350 ns
• Settle to ± 3 mV in 500 ns Ref Peak Inductor
Current Ref Example
• Settle to ± 1 mV in 800 ns
• Waveform Generation: Duty Cycle
• Up to 1 MHz triangle or slope waveforms
dsPIC33C Family
Live Update
• Update firmware in an operating power converter
Live Update 2P2Z to 3P3Z Demo
while maintaining continuous regulation

• dsPIC33C Live Update Features:

• Dual Flash partitions (main) & dual RAM partitions (secondary)
• Update one partition while executing from the other
• Fast switchover between partitions
• Transparently fits between compensator updates to PWM
• Continuous analog comparator fault monitoring 2P2Z 3P3Z
Updated To
Compensator Compensator
• PWM output can be truncated due to detected fault in 15ns (typ)
regardless of stage in Live Update process
• Complete development tools support and example code
 dsPIC33 Bitfield Instructions

24
dsPIC33CH Family
Dual Core Debug

• MPLAB supports parallel debug sessions

• Main core programs secondary core, hosts image
• Debug is independent
• Changes to secondary core code are placed back into main core’s image
• Breakpoints on either core can be configured to halt the other core or leave it running
dsPIC33CH Performance
Compensator Code Running on Secondary Core
dsPIC33CH Performance Example
Digital Power 3P3Z Latency
ADC Trigger Overall Latency PWM Update
Net ISR:
43 ns
0.89 μs At 40% CPU for
ADC compensator:
300 ns Compensator Calculations sampling
dsPIC33EP’GS
543 ns frequencies of
70 MHz
ISR 500KHz are
> 50% achievable
Faster

Net ISR:
0 ns 0.57 μs At 40% CPU for
dsPIC33CH’MP ADC compensator:
Compensator sampling
100 MHz 285 ns Calculations frequencies of >1
ISR 280 ns MHz are
achievable

Latency
dsPIC33CH Performance Example
Digital Power 3P3Z Latency
ADC Trigger Overall Latency PWM Update
Net ISR:
43 ns
0.89 μs At 40% CPU for
ADC compensator:
300 ns Compensator Calculations sampling
dsPIC33EP’GS
543 ns frequencies of
70 MHz
ISR 500KHz are
achievable

Net ISR:
0 ns 0.57 μs At 70% of
dsPIC33CH’MP ADC Secondary CPU
Compensator sampling Ideal
100 MHz 285 ns Calculations for GaN
frequencies of
ISR 280 ns ~1.8 MHz are
achievable

Latency
dsPIC33C Family
Advanced PWM Key Features & Benefits
Key Feature Benefit
250ps Resolution Precise control of duty cycle, phase, period and
With No Calibration Required dead time for a broad range of applications
Automatic hardware response to external events
reduces control latency and software workload.
Configurable PWM Control Inputs
Configure state machines for sophisticated
core-independent control

Eases single-shunt FOC implementations and

Improved Center Aligned Mode
can provide better noise immunity

Create complex control signals from multiple PWMs.

Built-in Combinatorial Logic Simplifies functions such as sync rectification or LED
dimming. Supports combinatorial PWM triggering

Simplifies updates to PWM and allows quick

PWM Control Shadow Buffers
changing of PWM operating conditions
 dsPIC33C Packages
Pinouts Optimized for Analog Performance
Corner anchors ease IPC-9592B second-level
qual that requires withstanding fast
temperature cycling of greater than 700 cycles
of -40C / +125C on thick, high-layer-count PCBs
48-lead uQFN (M4)
6 x 6 x 0.5 mm
with corner anchors
Package Types

(Lead Pitch: 0.4 mm)

28-lead uQFN (2N) 36-lead uQFN (M5) 64-lead QFN (MR)

6 x 6 x 0.5 mm 9 x 9 x 0.5 mm
5 x 5 x 0.5 mm
with corner anchors (Lead Pitch: 0.5 mm)
with corner anchors
(Lead Pitch: 0.65 mm) (Lead Pitch: 0.4 mm)

48-lead TQFP (PT) 64-lead TQFP (PT) 80-lead TQFP (PT) 100-lead TQFP (PT) 128-lead TQFP (PT)
28-lead SSOP (SS)
7 x 7 x 1 mm 10 x 10 x 1 mm 12 x 12 x 1 mm 12 x 12 x 1 mm 14 x 14 x 1 mm
10.2 x 5.3 x 2 mm
(Lead Pitch: 0.5 mm) (Lead Pitch: 0.5 mm) (Lead Pitch: 0.5 mm) (Lead Pitch: 0.4 mm) (Lead Pitch: 0.4 mm)
(Lead Pitch: 0.65 mm)

28 to 128 pins

Microchip Proprietary and Confidential

 Concept Samples

dsPIC33 DSC Roadmap Development Production

dsPIC33AH4096MPS9
Dual-Core / MPU+PPU

dsPIC33AK4096MPS6
dsPIC33CK1024MP7 dsPIC33CH1024MP7 dsPIC33AK1024MPS6 1-4MB ECC Flash,
512KB - 1MB ECC Flash, 512 – 1MB + 128K ECC Flash 512KB - 1MB ECC Flash, 736KB ECC RAM BIST,
dsPIC33EP128GS8 64 - 128KB RAM BIST, 124K + 60KB RAM BIST 5x12-bit ADC, Op-Amps,I3C
256KB ECC RAM BIST, 3xCAN-
64 - 128KB Flash, Single Core, DACs, Dual Core, 2xCAN-FD, Safety, FD, Touch, Security, I3C, Eth HSM, Ethernet, 3xCAN-FD
8KB RAM Op-Amps, 2xCAN-FD SW-Touch, Boot, OTP T1S, ISO 26262 compliant, 64/100/128/144/176 pins
Live Update, PTG, CLC 48/64/80/100 pins 48/64/80/100/128 pins Safety,
DACs, PGAs, 2xCAN
64/80/100/128 pins
28/44/48/64/80 pins dsPIC33CK512MP6 dsPIC33CH512MP5
Features / Memory

256 - 512KB ECC Flash, 256 - 512KB ECC Flash, dsPIC33AK512MPS5

dsPIC33FJ64GS6 dsPIC33EP64GS5 32 - 64KB RAM BIST, 48K RAM, 72K PRAM BIST,
32 - 64KB Flash, 256 - 512KB ECC Flash, 64KB
16 - 64KB Flash, Single Core, DACs, Dual Core, Dual Motor DACs,
4 - 9KB RAM ECC RAM BIST, Safety, 2xCAN-
2 - 8KB RAM Op-Amps, 2xCAN-FD PGAs, 2xCAN-FD.
DAC, DMA, FDs, Touch, Security,
Live Update, 48/64/80 pins 48/64/80 pins
CAN ISO 26262 compliant,
DACs, PGAs,
64/80/100 pins 48/64/80/100/128 pins
28/44/48/64 pins dsPIC33CK256MPE506
EEPROM
dsPIC33FJ16GS5 dsPIC33AK256MPS3
6 - 16KB Flash dsPIC33CK256MP508 128 - 256KB ECC Flash
0.25 - 2KB RAM 256KB ECC Flash, 24KB RAM 64KB ECC RAM BIST
DAC BIST, ADCs, CAN-FD, SENT, Single Core, Crypto, I3C
18/28/44 pins OTP, Sec. Boot, Touch, Safety DACs, PGAs
28/36/48/64/80 pins 36/48/64 pins

dsPIC33FJ09GS3 dsPIC33EP32GS2 dsPIC33CK64MP105 dsPIC33CH128MP5 dsPIC33AK128MC1

6 - 9KB Flash 16 - 32KB Flash 32 - 64KB ECC Flash 64 - 128KB ECC Flash, 332 - 128KB ECC Flash
0.25 – 1KB RAM 2KB RAM PGAs 8KB RAM BIST 16K RAM, 24K PRAM BIST, 8 - 16KB ECC RAM BIST
DAC, 4x4mm package option ADC, SENT, LIN, OTP, Boot Dual Core, Dual Motor, DACs, OPAs, CMP/DAC, Safety,
40 MHz only 28 pins SW CVD-Touch, Safety PGAs, CAN-FD Sec. Boot,
18/20/28/36 pins 28/36/48 pins 28/36/48/64/80 pins 28/36/48/64 pins

100 MHz 200 MHz, 32-bit with Double Precision FPU

40 – 70 MHz Integration
dsPIC33CK Single Core / dsPIC33CH Dual Core dsPIC33AK Single Core / dsPIC33AH Dual Core

32
Microchip Proprietary and Confidential
dsPIC33CH1024 Family
Preview – 6 ADCs, 8 Analog Comparators, 12 PWM Pairs, 3 PGAs

124KB 1024KB 128KB 60KB

ECC 6ch ECC ECC 2ch ECC
Data DMA Dual panel Dual panel DMA Data
RAM Flash Flash RAM

MEMORY BUS MEMORY BUS

4ch PWMs PWMs 8ch
1x ADC Main Secondary ADCs 5x

PERIPHERAL BUS
2x Comps PERIPHERAL BUS dsPIC33C dsPIC33C Comps 6x
Core Core PGAs 3x
3x I2C 85 MHz 75 MHz I2C 2x
2x CAN-FD SPI 2x
Mailbox
Mailbox 2x
3x SPIs Mailbox
Mailbox
Mailbox
Mailbox
UART
Mailbox
Mailboxes
2x UARTs SCCP 4x
8x SCCP M –> S FIFO Out Cmp

Timer S –> M FIFO Timer

Microchip Proprietary and Confidential

dsPIC33CH1024 Family
Main Core Peripherals
6 General DMA channels
124KB 1024KB
ECC 6ch ECC 2 CAN-FD (with 2 dedicated DMA channels)
Data DMA Dual panel 2 SENT
RAM Flash
3 SPI with I2S support
3 I2C with PMBus support
MEMORY BUS
3 UARTS

Main 1 Peripheral Trigger Generator (PTG)

PERIPHERAL BUS dsPIC33CH 4 Configurable Logic Cells (CLCs)
Core 2 QEI (Quadrature Encoder Interface)
85 MHz 8 SCCPs - 32 bit-timer/Cap/Compare
1 CRC Module
1 12-bit ADC with up to 18 channels
2 Analog Comparators w/ 12-bit DACs
2 DAC output buffers
4 PWM Generators

Microchip Proprietary and Confidential

dsPIC33CH1024 Family
Secondary Core Peripherals
2 General DMA channels
128KB 60KB
5 12-bit ADCs w/ up to 18 channels ECC 2ch ECC
Dual panel DMA Data
6 Analog Comparators with 12-bit DACs Flash RAM

3 PGAs (sharable with main core)

8 PWM Generators MEMORY BUS

1 Peripheral Trigger Generator (PTG)

Secondary
4 Configurable Logic Cells (CLCs)

PERIPHERAL BUS
dsPIC33CH
1 CRC Module Core
2 QEI (Quadrature Encoder Interface) 75 MHz
4 SCCPs - 32 bit-timer/Cap/Compare
2 SENT
2 SPI with I2S support
2 UARTs
2 I2C with PMBus support

Microchip Proprietary and Confidential

dsPIC33CH1024 Family Device Part Number Pins
Main
Core
Flash
(KB)
Main
Core
RAM (KB)
Secondary
Core Flash
(KB)
Secondary
Core RAM
(KB)
Regulator CAN-FD

Part Numbers dsPIC33CH1024MP712

dsPIC33CH1024MP710
128
100
1024
1024
124
124
128
128
60
60
Buck
Buck
2
2
dsPIC33CH1024MP708 80 1024 124 128 60 Buck 2
dsPIC33CH1024MP706 64 1024 124 128 60 Buck 2

• LDO regulator on some versions (MP3xx & MP6xx)

dsPIC33CH1024MP705 48 1024 124 128 60 Buck 2
dsPIC33CH512MP712 128 512 124 128 60 Buck 2

• 3.3v Vdd input dsPIC33CH512MP710

dsPIC33CH512MP708
100
80
512
512
124
124
128
128
60
60
Buck
Buck
2
2

• Pin compatible with rest of the dsPIC33CH family dsPIC33CH512MP706 64 512 124 128 60 Buck 2
dsPIC33CH512MP705 48 512 124 128 60 Buck 2
• LDO version not available in 100 or 128 pin versions since dsPIC33CH1024MP608 80 1024 124 128 60 LDO 2

no need for footprint compatibility with previous variants dsPIC33CH1024MP606 64 1024 124 128 60 LDO 2
dsPIC33CH1024MP605 48 1024 124 128 60 LDO 2
dsPIC33CH512MP608 80 512 124 128 60 LDO 2

• On-die buck regulator (MP4xx & MP7xx) dsPIC33CH512MP606 64 512 124 128 60 LDO 2
dsPIC33CH512MP605 48 512 124 128 60 LDO 2
• 3.3v Vdd input dsPIC33CH1024MP412 128 1024 124 128 60 Buck 0

•
dsPIC33CH1024MP410 100 1024 124 128 60 Buck 0
Much lower Idd dsPIC33CH1024MP408 80 1024 124 128 60 Buck 0

• Some external components needed dsPIC33CH1024MP406 64 1024 124 128 60 Buck 0

dsPIC33CH1024MP405 48 1024 124 128 60 Buck 0
• Not pin compatible with LDO versions due to new pins dsPIC33CH512MP412 128 512 124 128 60 Buck 0
dsPIC33CH512MP410 100 512 124 128 60 Buck 0
dsPIC33CH512MP408 80 512 124 128 60 Buck 0
• Dual CAN-FD and non CAN-FD versions dsPIC33CH512MP406 64 512 124 128 60 Buck 0

• CAN-FD (MP6xx & MP7xx)

dsPIC33CH512MP405 48 512 124 128 60 Buck 0
dsPIC33CH1024MP308 80 1024 124 128 60 LDO 0

• Non CAN-FD (MP3xx & MP4xx) dsPIC33CH1024MP306

dsPIC33CH1024MP305
64
48
1024
1024
124
124
128
128
60
60
LDO
LDO
0
0
dsPIC33CH512MP308 80 512 124 128 60 LDO 0
dsPIC33CH512MP306 64 512 124 128 60 LDO 0
dsPIC33CH512MP305 48 512 124 128 60 LDO 0

Microchip Proprietary and Confidential

dsPIC33CH1024 Family
Packages
Corner anchors ease IPC-9592B second-level
qual that requires withstanding fast
temperature cycling of greater than 700 cycles
of -40C / +125C on thick, high-layer-count PCBs
48-lead uQFN (M4)
6 x 6 x 0.5 mm
with corner anchors
(Lead Pitch: 0.4 mm)
Package Types

64-lead QFN (MR)

9 x 9 x 0.9 mm
(Lead Pitch: 0.5 mm)

48-lead TQFP (PT) 64-lead TQFP (PT) 80-lead TQFP (PT) 100-lead TQFP (PT) 128-lead TQFP (PT)
7 x 7 x 1 mm 10 x 10 x 1 mm 12 x 12 x 1 mm 12 x 12 x 1 mm 14 x 14 x 1 mm
(Lead Pitch: 0.5 mm) (Lead Pitch: 0.5 mm) (Lead Pitch: 0.5 mm) (Lead Pitch: 0.4 mm) (Lead Pitch: 0.4 mm)

48 to 128 pins
 Concept Samples

dsPIC33 DSC Roadmap Development Production

dsPIC33AH4096MPS9
Dual-Core / MPU+PPU

dsPIC33AK4096MPS6
dsPIC33CK1024MP7 dsPIC33CH1024MP7 dsPIC33AK1024MPS6 1-4MB ECC Flash,
512KB - 1MB ECC Flash, 512 – 1MB + 128K ECC Flash 512KB - 1MB ECC Flash, 736KB ECC RAM BIST,
dsPIC33EP128GS8 64 - 128KB RAM BIST, 124K + 60KB RAM BIST 5x12-bit ADC, Op-Amps,I3C
256KB ECC RAM BIST, 3xCAN-
64 - 128KB Flash, Single Core, DACs, Dual Core, 2xCAN-FD, Safety, FD, Touch, Security, I3C, Eth HSM, Ethernet, 3xCAN-FD
8KB RAM Op-Amps, 2xCAN-FD SW-Touch, Boot, OTP T1S, ISO 26262 compliant, 64/100/128/144/176 pins
Live Update, PTG, CLC 48/64/80/100 pins 48/64/80/100/128 pins Safety,
DACs, PGAs, 2xCAN
64/80/100/128 pins
28/44/48/64/80 pins dsPIC33CK512MP6 dsPIC33CH512MP5
Features / Memory

256 - 512KB ECC Flash, 256 - 512KB ECC Flash, dsPIC33AK512MPS5

dsPIC33FJ64GS6 dsPIC33EP64GS5 32 - 64KB RAM BIST, 48K RAM, 72K PRAM BIST,
32 - 64KB Flash, 256 - 512KB ECC Flash, 64KB
16 - 64KB Flash, Single Core, DACs, Dual Core, Dual Motor DACs,
4 - 9KB RAM ECC RAM BIST, Safety, 2xCAN-
2 - 8KB RAM Op-Amps, 2xCAN-FD PGAs, 2xCAN-FD.
DAC, DMA, FDs, Touch, Security,
Live Update, 48/64/80 pins 48/64/80 pins
CAN ISO 26262 compliant,
DACs, PGAs,
64/80/100 pins 48/64/80/100/128 pins
28/44/48/64 pins dsPIC33CK256MPE506
EEPROM
dsPIC33FJ16GS5 dsPIC33AK256MPS3
6 - 16KB Flash dsPIC33CK256MP508 128 - 256KB ECC Flash
0.25 - 2KB RAM 256KB ECC Flash, 24KB RAM 64KB ECC RAM BIST
DAC BIST, ADCs, CAN-FD, SENT, Single Core, Crypto, I3C
18/28/44 pins OTP, Sec. Boot, Touch, Safety DACs, PGAs
28/36/48/64/80 pins 36/48/64 pins

dsPIC33FJ09GS3 dsPIC33EP32GS2 dsPIC33CK64MP105 dsPIC33CH128MP5 dsPIC33AK128MC1

6 - 9KB Flash 16 - 32KB Flash 32 - 64KB ECC Flash 64 - 128KB ECC Flash, 332 - 128KB ECC Flash
0.25 – 1KB RAM 2KB RAM PGAs 8KB RAM BIST 16K RAM, 24K PRAM BIST, 8 - 16KB ECC RAM BIST
DAC, 4x4mm package option ADC, SENT, LIN, OTP, Boot Dual Core, Dual Motor, DACs, OPAs, CMP/DAC, Safety,
40 MHz only 28 pins SW CVD-Touch, Safety PGAs, CAN-FD Sec. Boot,
18/20/28/36 pins 28/36/48 pins 28/36/48/64/80 pins 28/36/48/64 pins

100 MHz 200 MHz, 32-bit with Double Precision FPU

40 – 70 MHz Integration
dsPIC33CK Single Core / dsPIC33CH Dual Core dsPIC33AK Single Core / dsPIC33AH Dual Core

38
Microchip Proprietary and Confidential
dsPIC33C Family
Single Core Devices: dsPIC33CK
SMPS PWM - 24 Channels (12 pairs) 250ps Resolution
dsPIC33 Core 100 MIPS
Context Selected Regs 12-bit ADCs - 5 (Up to 24 Channels) 285 ns Latency
16x16 Barrel Analog Comp – 6 (with 12-bit DACs) 15 ns Response
16-Bit ALU
Registers Shifter
Operational Amplifiers - 3 15 MHz BW

PERIPHERAL BUS
17x17 JTAG & Address
MPY EMU Generation

I2C - 3 with PMBus Support

Peripheral Pin Select (PPS)

MEMORY BUS SPI / I2S - 3

UART - 3
64 – 1024KB 8 - 128KB
DMA - 8 SCCP - 8
Flash RAM
MCCP - 1
dsPIC33CK512MP Additions:
• 2x flash memory (up to 512KB)
16-bit Timers - 1
• 40KB more RAM (64KB total)
• 2 more 12-bit ADCs (5 total) CAN FD - 2
• 2 more analog comps with DACs (6 total)
• 1 more CAN FD (2 total)
• 4 more DMA
Peripheral Trigger Generator (PTG)
dsPIC33CK1024MP Additions:
• 2x flash memory (up to 1MB) Configurable Logic Cells (CLC) - 8
• 64KB more RAM (128KB total)
• 100 pin packages
• 4 more PWM pairs (in 100 pin package)
• 4 more CLCs (8 total)
 Hardware Features – dsPIC33C DSCs Flash Memory
CodeGuard Flash Security Boot Segment

• Partitions Flash into ‘Boot’ and ‘General’ segments Write / Erase Protect
for Immutability
which are user configurable

Configurable Size
• Simplifies Secure Boot implementation (for Secure Boot code)

• Boot segment for Immutable Secure Boot and

Bootloader for firmware upgrades
General Segment
• General segment for user application code (for user application)

• Dual Partition Flash for Live Update

• Firmware update in real-time
40
 Hardware Features – dsPIC33C DSCs
Flash OTP by ICSP Write Inhibit
• Prevents Flash memory modification similar to One-Time-Programmable memory (OTP) using
external programmer/debuggers

• Once activated, cannot be disabled Security Requirement from GM

• Supports memory updates via Bootloader

• Disable entry into debug mode

Use Cases:
Immutable
IP Protection *
Secure Boot **

* Flash OTP by ICSP Write Inhibit works together with Read/Write Protect and FICD Config register setting
** Flash OTP by ICSP Write Inhibit works together with CodeGuard Flash Security
41
 Released
dsPIC33CK512MPT608
dsPIC33CK Secure DSC dsPIC33C Core & Secure Subsystem
Integrated Off-Die HSM
Peripherals
• dsPIC33C DSC Security Features Crypto Engine
ECC / RSA / SHA / AES
• CodeGuard Protection for Immutable Secure Boot CodeGuard Protection +
OTP Flash
• Flash configurable as One Time Programmable (OTP) memory SPI Key Mgmt.

• Debug disable Dual Partition for Live

Firmware Upgrades Tamper Hardened
• No code execution from RAM Unique Serial Number
120-bit
• Offer protection against remote digital attacks UDID
User OTP
High Quality RNG
• Secure Subsystem (Integrated Off-Die HSM) Features CAN-FD Monotonic Counter
• EVITA Full compliant
• X.509 certificate validation and storage
• Secure Private/Secret Key Storage
• RSA & ECC Signature Generation & Verification, key agreement
• ECDSA sign, SHA256 HMAC, RSA/ECC/AES/SHA Authentication,
AES/ECC Key Generation
• High quality RNG, NIST SP800-90 A/B/C

• “High” JIL Resistance rated Secure Subsystem Functional Safety

Support
• FIPS 140-2 level 2 with Physical Security Level 3 certified Secure Subsystem module
• ISO 21434 certification for dsPIC33CK MPT Secure DSC is in progress
42
 dsPIC33C DSC Family – Security Overview
Security Feature dsPIC33CK-MP/MC DSC dsPIC33CK-MPT Secure DSC
CodeGuard Security for Immutable Secure Boot ✓ ✓
ICSP Write Inhibit for Flash configurable as OTP memory ✓ ✓
Unique ID ✓ ✓
Debug Disable ✓ ✓
Chip Erase Lock ✓ ✓
Boot Protect Lock ✓ ✓
Immutable Secure Boot Segment ✓ ✓
User configurable Secure Boot Segment ✓ ✓
Secure Update (OTA Update) ✓ + External HSM/TA100 ✓
Secure Subsystem (HSM) External HSM/TA100 ✓
Secure Key Storage External HSM/TA100 ✓ (Secure Subsystem)
Crypto Acceleration External HSM/TA100 ✓ (Secure Subsystem)
TRNG External HSM/TA100 ✓ (Secure Subsystem)
Anti-RollBack ✓ ✓
SPA/DPA Countermeasures External HSM/TA100 ✓ (Secure Subsystem)
Monotonic Counters External HSM/TA100 ✓ (Secure Subsystem)
Environmental Monitors External HSM/TA100 ✓ (Secure Subsystem)
Intrusive Physical Attack Protection External HSM/TA100 ✓ (Secure Subsystem)

43
dsPIC33 A-Core Preview
32-Bit Arithmetic Extensions and DP FPU
dsPIC33 A-Core
Design Objectives
Improve the dsPIC33 Architecture …

• Extend ISA to include 32-bit integer & 32-bit fixed-point operations

• Improves operand resolution
• Allows unified linear address map
• Add double precision floating point hardware
• Accelerates some algorithms
• Extract maximum performance from advanced process technologies
• Five stage pipeline allows fast instruction execution
• Targeting 200 MHz operation for first products

… while maintaining some backward source code compatibility

Microchip Proprietary and Confidential

dsPIC33 Performance Evolution
Digital Power 3P3Z Example
ADC Trigger Overall Latency PWM Update

dsPIC33FJ ADC ISR Compensator Calculations

50 MHz 600 ns 100 ns
1140 ns
1.84 μs

ADC Compensator
dsPIC33EP
300 ns Calculations
70 MHz
ISR 543 ns 0.89 μs

ADC Compensator
dsPIC33C 285 ns
100 MHz Calculations
ISR 280 ns
0.57 μs

dsPIC33A ADC
16- or 32-bit fixed point:
200 MHz 150 ns
ISR 0.19 μs (estimate)
(Target)

Latency
Microchip Proprietary and Confidential
 dsPIC33AK DSC Family Block Diagram Sampling
dsPIC33A CPU High Resolution PWM – 12 pairs (78ps Res.)
DMA 200 MHz
Up to 8 Channels
3x QEI and 1x Master BiSS
8 sets of Context DP FPU
Registers 5x 40 Msps 12-bit ADC – up to 28 Channels
CAN-FD
Up to 2
Integrated Touch Controller(ITC), 32 inputs
Cryptographic System Bus
Acceleration 8x 12-bit DAC/CMP

Peripheral Pin Select (PPS)

Module (CAM)
3x Op-Amp
Device Locking 128KB to 512KB 16KB to 64KB

Peripheral Bus
ECC Flash ECC RAM 16x virtual re-mappable pins
Immutable Root of
Trust / Secure Boot
2kB Cache 3x UART, 4x SPI, 2x SENT
IP Protection
Security Access
BOR WWDT Up to 16x IO Monitor - FuSa
Control DMT
IRT Secure Key Storage
I2C – 3
Dual Panel Flash Clock Backup Buck
Live Update Monitor OSC Regulator
8x SCCP/1xMCCP

Up to 3x Timers and RTCC

Package: Up to 128-pins Hardware TRACE / Secure Debug
Configurable Logic Cells (CLCs) – 10
Operating Temperature: -40°C to 150°C

ASIL B Compliant Design Target AEC-Q100 Grade 0 Qualification Peripheral Trigger Generator (PTG) - 1

47
Microchip Proprietary and Confidential
Security Features of dsPIC33 DSC Family
dsPIC33CK- dsPIC33CK-MPT dsPIC33A
Security Feature
MP/MC DSC Secure DSC MPS/GMS DSC
Immutable Secure Boot/Immutable Root of
✓ ✓ ✓
Trust
ICSP Write Inhibit for Flash configurable
✓ ✓ ✓
as OTP memory
Unique ID ✓ ✓ ✓
Disable Entry Into Debug Mode ✓ ✓ ✓
Secure Debug Entry - - ✓
Chip Erase Lock ✓ ✓ ✓
Boot Protect Lock ✓ ✓ ✓
User configurable Secure Boot Segment ✓ ✓ ✓
Secure Firmware Update (OTA Update) ✓ + ECC608/TA100 ✓ ✓
Secure Key Storage Pair with ECC608/TA100 ✓ (Secure Subsystem) IRT Keys
Crypto Acceleration Pair with ECC608/TA100 ✓ (Secure Subsystem) ✓
TRNG Pair with ECC608/TA100 ✓ (Secure Subsystem) ✓
Anti-RollBack ✓ ✓ ✓
Environmental Monitors in Secure
Pair with ECC608/TA100 ✓ (Secure Subsystem) Pair with ECC608/TA100
Subsystem
Intrusive Physical Attack Protection in
Pair with ECC608/TA100 ✓ (Secure Subsystem) Pair with ECC608/TA100
Secure Subsystem

Microchip Proprietary and Confidential

 dsPIC33A Robust Security
• Device Locking
• Code Protect, ICSP Write Inhibit, Secure Debug
• Immutable Root of Trust (IRT)
• Secure boot, secure debug, device attestation …
• Cryptographic Acceleration Module (CAM)
• AES, SHA, RSA, ECC
• TRNG
• Firmware IP Protection
• Execute only OTP flash memory
• Secure Debug
• External access requires authorization by IRT firmware
• Access granted temporarily
• Option to permanently disable debug entry
• Device Unique ID
• 128-bit Universally Unique ID (UUID)

49
Microchip Proprietary and Confidential
 Cryptographic Acceleration Module (CAM)
• AES-128, AES-192, AES-256
• ECB, CBC, CFB, OFB, CTR, GCM, CCM, XTS, CMAC

• SHA-1, SHA-224, SHA-256, SHA-384, SHA-512

• HMAC

• RSA, DSA, DH
• Up to 4096 bit

• ECDH, ECDSA, EdDSA

• P-256, P-384, 25519, custom

• J-PAKE, SRP

• DPA Countermeasures

• TRNG
• NIST 800-90A/B/C

• HASH of the memory (or part of the memory) to be shared via debug interface

50
Microchip Proprietary and Confidential
Digital Power Development
Design Tools
PowerSmart Development Suite
The Fast Way to a Working Power Supply
• Create MPLAB X project
• Select device, compiler version, etc.

• Configure device using MCC GUI

• Adds main.c to project, setup clocks and dividers
• Configure ADC channel, pins, trigger source, interrupts
• Configure PWMs including when to trigger ADC

• Add example code snippets

• State machine, timing loop and soft start

• Create P-Term loop measurement code using PowerSmart DCLD

• Use GUI to configure source code such as anti-windup clamping

• Measure poles & zeros of plant

• Use PowerSmart DCLD to generate final compensator assembly code
MPLAB® Code Configurator (MCC) MPLAB X IDE
Use with PowerSmart Development Suite MPLAB
MPLAB Code
Configurator

Graphical programming environment that Code MCC

generates easy-to-understand code Code

Examples
DCLD

• Automatic configuration of peripherals

Digital Compensator Library Designer
• Reduces overall design effort Resource Area Composer Area Pin Manager Area

• Minimizes references to product datasheet

• Intuitive interface for quick start

Digital Power Design Examples
Speed Development / Reduce Risk Digital Compensator Design Tool

DCDT
MPLAB Code
Configurator

Royalty-free microcontroller and application-specific Examples MCC

LIB
Working Design

hardware and software designs Examples

Compensator
Libraries

• Starter kits
• Development boards / EVBs
• Reference designs
• Code examples
• Application notes
 dsPIC33 Model-based Tools
For Digital Power Design
• PLECS - Dedicated power electronics simulation platform
• Electrical, magnetic and thermal domains
• Time, frequency and spectrum domain analysis
• Powerful analysis tools
• Simulation scripts
• PLECS Coder generates generic ANSI-C code from a PLECS Blockset or PLECS
Standalone model

• MATLAB / Simulink
• MPLAB Device Blocks for Simulink
• Library blocks configure peripherals and inserts code in the MathWorks generated
code by embedded coder
• More comprehensive dsPIC33 solution for motor control development (as of today)

55
 PLECS
Different Simulation Use-Cases
• Strict Circuit Simulation
• Circuit analysis using PECS models and blockset
• Simulation scripts describe non-linear behavior

• Processor in the Loop (PIL)

• Code executed on dsPIC33 including real CPU behavior (e.g. interrupt latency)
• Allows parallel debugging in target device IDE (e.g. MPLAB X IDE)
• CPU independent peripherals are simulated by models in simulation model

• RT Box Simulations
• Simulation controls signal generation hardware (RT Box)
• Target device peripherals are stimulated by analog and digital signals
• Full enclosure of target device CPU and peripheral dependencies in simulation

56
 PLECS Virtual Power Supply Development Environment
Using Processor In the Loop (PIL)

Power Stage

Controller Design &

Code Generation
VCP Interface
dsPIC®
Digital Signal
Controller

Software execution Peripheral Simulation

on target device in PLECS
57
dsPIC33 Digital Power
Evaluation Boards and Reference Designs
Digital Power Development Tool Roadmap
Power Board Visualizer GUI

Four-Switch Buck-Boost Development Board (4SBB)

EV44M28A

Low Voltage ILLC Development Board

EV84C64A

Low Voltage PFC Development Board

DV330101

dsPIC33EP128GS808 dsPIC33CK256MP508 dsPIC33CH512MP508 dsPIC33AK128MC106

Digital Power PIM Digital Power PIM Digital Power PIM Digital Power PIM
MA330043 MA330048 MA330049 EV67K87A

Digital Power Starter dsPIC33C Digital

Kit Power Starter Kit
DPSK-2 DM330017-3
DM330017-2
dsPIC33EP128GS808 dsPIC33CK Curiosity dsPIC33CH Curiosity dsPIC33AK Curiosity
Development Digital Power PIM Development Board Development Board Development Board
Production MA330043 DM330030 DM330028-2 EV74H48A

dsPIC33EP ‘GS dsPIC33CK ‘MP dsPIC33CH ‘MP dsPIC33AK

Microchip Proprietary and Confidential
 Digital Power Reference Design Roadmap
Development
Production

OCP Compliant Server Power

15W Multi-Coil Wireless 15W Multi-Coil Wireless Power 15W Multi-Coil Wireless
Qi 1.3 MPA13 Topology
Wireless

Power 300W Wireless Power

Power

Power
Qi 1.3 MPA22 Topology 15W Wireless Power MPA9 Topology
Qi 2.0 MPP + EPP Topology

Interleaved PFC 11kW 3-Phase Totem-pole PFC

30kW 3-Phase Vienna PFC

PFC

EPC9148 – 3L Sync. Buck

EPC9143 - 300W 1/16th Brick
1kW Totem Pole PFC
EPC9151 - 300 W Bi-Dir. 1/16th Brick
+ Panasonic GaN
EPC9137 - 1.5 kW Bi-Dir. Module Future Electronics
Interleaved PFC Semi-bridgeless PFC
in 720W AC/DC (Platinum in 750W AC/DC
EPC9149 - 1KW LLC 1/8th Brick
EPC9153 - 250 W Thin Module

Quarter Brick DC/DC Bi-directional DC/DC Bus 11kW DAB DC/DC Converter
Converter USB Power Delivery
w/ UPD350
DC/DC

Two-switch Forward Peak Current ZVS FB 4KW LV DC/DC Converter

in 720W AC/DC in 750W AC/DC
Peak Current ZVS PSFB 22kW CLLC DC/DC Converter
200W LLC 200W LLC in 750W AC/DC

720W AC/DC (Platinum) 750W AC/DC

AC/DC

Interleaved PFC Semi-bridgeless PFC

Two-switch Forward DC/DC Peak Current ZVS FB DC/DC

dsPIC33FJ ‘GS dsPIC33EP ‘GS dsPIC33CK ‘MP dsPIC33CH ‘MP Fixed Function Devices
60
Microchip Proprietary and Confidential
 E-Mobility Power Ref Designs
Concept
Development
Production

PFC
30 kW L3 Charger Totem Pole PFC Design Complete
(Off Board Charger) DC-DC Hardware CQ2’24
Design by CIRCE Series series resonant Future add dsPIC33
converter

LV PFC HV PFC Single phase max power CQ2’24

11kW On Board Totem Pole PFC Totem Pole PFC Three phase max power CQ3’24
Charger
DC-DC
Design by MCU16 Dual Active Bridge CQ2’24

22kW On Board PFC

Charger Totem Pole PFC
Starting development now
MCU16 & 3rd party DC-DC
Andrew Ferenz CLLC

LV DC-DC Converter DC-DC

Schematic design complete
Design by MCU16 PSFB

61 Microchip Proprietary and Confidential

MPLAB® Starter Kit for Digital Power -3
Features:
• dsPIC33CK256MP based
• Independent buck and boost DC/DC converters
• LCD display, status LEDs, temperature sensors
• Configurable resistive loads
• PKOB-4 On-board debugging / programming via USB

Package Contents:
• Board (~ 5” x 2.5”)
• Mini USB cable
• 9V Power Supply
• Info Sheet with schematic

$199.99
Order # DM330017-3
Digital Power PIMs
• Building blocks for Microchip’s digital power development boards
• Controller easily swapped out for evaluation of various dsPIC33 family members

• Flexibility for prototyping with PCBs that use this standardized DP PIM connector

• Features
• ICSP programming header
• On-board LDO with Power Good (PG) function
• Micro USB connector
• MCP2221A USB to UART/I2C serial converter
• Edge connection for analog inputs/outputs, PWM outputs and GPIO ports
• Test point loop for DAC output

Available DP PIMs Part Number

dsPIC33EP128GS808 MA330043
Available today @ $49 each
dsPIC33CK256MP508 MA330048
dsPIC33CH512MP508 MA330049
Digital Power Development Board
• Uses new Digital Power PIMs
• Micro Elektronika mikro BUS Socket
• PWM & GPIO Test pins
• Analog Input test pins
• BNC Connector
• Analog potentiometers
• Push button
• Solder pad- Scope ground connection
• Prototyping field (2.54mm raster)

Part Number: DM330029 $112

LV PFC Development Board
• Low Voltage PFC
• Vin: 12 - 24V AC
• Vout: 31 - 42V DC
• ~50W Max
• Topology
• Single phase or
Interleaved dual phase
• Firmware for:
• Continuous Conduction Mode
• Critical Conduction Mode (a.k.a. Transition Mode or Boundary Mode)

• Uses DP PIM controller modules

• Companion DC/DC Interleaved LLC Development Board Available Soon
• Part # DV330101 $375
LV ILLC Development Board
• Input working voltage range: 38 - 42 VDC
• Max. Output Power: 30W per phase
• Maximum Switching Frequency: 1000 kHz
• Test Points for outer loop measurements
• Protection circuitry
• HMI Interface (Push buttons and two LEDs)
• AUX Connector
• Supports UART communication, GPIO, Analog input,
DAC signal output and 3.3V analog AUX supply
• Uses DP PIM controller modules
• Companion LV PFC Development Board also available
• Part # EV84C64A
Four-Switch Buck-Boost Development Board
• Input Working Voltage Range: 8 - 18 VDC
• Max. Output Power: 20W
• Four-switch power converter with gate drivers:
• Left Leg-Buck, Right Leg-Boost

• Output current shunt amplifier

• Test points for outer loop measurements
• HMI interface (push buttons and two LEDs)
• dsPIC33-DSC DP-PIM socket with test points at the
edge of the board
• Input filter, overvoltage protection, output filter
• Uses DP PIM controller modules
• Part # EV44M28A
Royalty-Free* Reference Designs
Available Today
• 750W AC/DC Supply
• Semi-Bridgeless PFC
• Zero Voltage Switching Full-Bridge with Peak Current Mode Control using Digital Slope
Compensation and Synchronous Rectification
• 720W Platinum-rated AC/DC Supply
• IPFC + interleaved 2-switch forward conv with SR
• Adaptive algorithms to achieve > 94% efficiency
• Enhanced Solar Micro Inverter
• 250W panel input, grid-tied output
• MPPT to achieve 94.5% efficiency (peak)
• 1KW Pure Sine Wave UPS
• Offline UPS system
• Push-pull converter & full-bridge inverter
• Interleaved Power Factor Correction
• Two phase interleaved PFC
• Up to 400VDC output, 350W sustained
• DC/DC LLC Resonant Converter
• Zero Voltage Switching on half-bridge conv
• Zero Current Switching on synch rectifier. >95% eff
• Quarter Brick DC/DC Converter
• Phase-shifted full-bridge topology
• Planar magnetics and non-linear control for efficiency

*Royalty-free when used in accordance with Microchip’s licensing agreement

ZVS FB Peak Current Mode 750W AC/DC Ref Design
• Topology
• Semi-Bridgeless PFC
• Zero Voltage Switching Full-Bridge with Peak Current Mode Control using Slope Compensation and Synchronous Rectification
• Advanced algorithms
• Variable bulk voltage
• Variable switching frequency
• Non-linear control
• PWM frequency jitter routine to improve EMI
• Active inrush control
• Live Update
• Communication (UART, I2C)
Output Power: 750W
(12V @ 62.5A)

• dsPIC33CK-based Phase-shift full bridge with peak current

mode control version of this design is in development
Automotive Bidirectional DC/DC Bus Converter
1600 Watts
12V Battery
Regenerative braking
systems 48V Battery

48V Generator
/ Starter 48V Li-Ion
Battery

48V Power
Bi-directional Bi-directional
48V-based Options: Supporting
Rail A
Conversion Stage Rail B
- Turbo Drives
- Dampers Power Plant
48V dsPIC33 Control and
12V
Monitoring
System System-level
Management Monitoring &
MCU Housekeeping /
Communication
(AUTOSAR)

CAN Bus
 Automotive Digital Power Applications
Microchip Components:
DC – DC Bus Converter Digital Signal Controllers
FET Driver Dual Non-inverting
Buck Buck 2V to 15V
dsPIC33EP64GS506
MIC4104YM
MCP16301T-E/CH
Buck Buck 2V to 24V MCP16331T-E/CH
1600W DC-DC Bus Converter 48V <-> 12V VREF 2.5V MCP1525T-I/TT
LDO 5V MCP1804T-5002I/OT
• Four-phase synchronous buck topology FET Driver Single-Non-Inverting MCP1402T-E/OT
Temperature Sensor MCP9700T-E/TT
• Non isolated DC/DC converter OpAmp 1-Ch 2.8MHz MCP601T-I/OT
• Controllers: 2 x dsPIC33EP64GS506
• Switching frequency equivalent: 348kHz
• Reverse bias protection on both rails
• Dimensions: 188 x 127 x 40mm
12V
Battery
48V Li-Ion
48V Battery
Generator
/ Starter

48V Mechanisms:
- Turbo
- Dampers
 Totem-pole PFC Development System
Level 2 Onboard Charger Power Factor Correction
11kW Totem-pole PFC Features:
⚫ Single- or 3-phase AC source
⚫ Level 2: 11kW from 3-phase source
⚫ Up to 3.6kW from single-phase
⚫ Bidirectional operation

⚫ Uses dsPIC33 DP PIMs and new FET PIMs

for SiC power MOSFETs
⚫ AEC-Q100 qual’ed components (when available)
⚫ Galvanically isolated CAN interface
⚫ Forced-air cooled
⚫ Low-voltage Dev Board to be sold
⚫ Swap voltage divider resistors, connect
appropriate bulk caps at output and
update firmware to get full 11kW
Matching 11kW Battery Charger in Development
Microchip Confidential & Proprietary
Totem-pole PFC Development System
Prototype Hardware

Microchip Confidential & Proprietary

Totem-pole PFC Development System
Power Board without Heatsink – Modular Design for Flexibility

New FET PIM DP PIM

AC Acquisition
Board

Microchip Confidential & Proprietary

Totem-pole PFC Development System
AC Acquisition Board – Evaluate Different Sense Techniques
For high voltage:
L1 sense = V(L1 in)*Vsense_gain + Vsense_offset
• OpAmps scale AC line voltages to dsPIC33 Vsense_gain = 3.771mV/V
L2 sense = V(L2 in)*Vsense_gain + Vsense_offset
L3 sense = V(L3 in)*Vsense_gain + Vsense_offset
• dsPIC33CK For low voltage:
Vsense_gain = 37.585mV/V

• Digitize phase voltages via on-board 12-bit ADCs L1 in

L1 sense Opto-
RA0
• Process each sample Vsense_offset isolator

• Transmit post-processed data to dsPIC33CH on the RB14 SPI Clock

L2 in L2 sense
main PFC power board via SPI every 50us Vsense_offset
RA2
To
• 2 isolated digital outputs for SPI interface dsPIC33CK32MC102 Opto-
isolator
dsPIC33CH

• Chip-select not needed since only source L3 in L3 sense

RA4 RB12 SPI Data
Vsense_offset

N
Vsense_offset RB2

Microchip Confidential & Proprietary

Totem-pole PFC Development System
SiC FET PIMs

• First model uses two SiC MSC025SMA120B4

in standard Half Bridge configuration
• MIC4120 gate drivers with +15V & -5V
• Open-loop HF push-pull stage generates
galvanic isolated voltages for gate drivers
• PIC16 drives push-pull stage, provides Vaux,
temperature measurements, drives LEDs
and provides I2C communication
• PWM signals to drive HB stage isolated with
opto-couplers
Microchip Confidential & Proprietary
Totem-pole PFC Development System
Bidirectional Low-Voltage Single-Phase Demo Setup

DC → AC / Reverse Current

PC1_PFC
Basic Load
CAN-ID
0x202/0x203

CAN Bus
PC2_
230Vac Inverter
AC → DC / Forward Current CAN-ID
0x302/0x303

23Vac
Microchip Confidential & Proprietary
Totem-pole PFC Development System
Hardware and Software Setup

2 PFC boards stacked.

FT GUI connected to PEAK dongle and
Board on buttom is 1Ph PFC mode.
handles 2 ID‘s:
Board on top is 1Ph reverse avgcm.
ID 0x20x for 1Ph PFC mode
AC input on both boards at Vin. Vout connected where PFC board delivers PoBo connected to PEAK dongle and handles
ID 0x30x for 1Ph reverse avgcm
Vout as input to Reverse board. only ID 0x20x for 1Ph PFC mode
At Vout a 100Ω load resistor as basic load

Microchip Confidential & Proprietary

 DC/DC Development System
Level 2 OBC Battery Charger - Preview
11kW DC/DC Features:
⚫ 700VDC - 900VDC input
⚫ Uses dsPIC33 DP PIMs and new FET
PIMs for SiC power MOSFETs
⚫ Sense lines for bidirectional power
⚫ Switching frequency target: 100kHz
⚫ Hot-plug at the output for battery
⚫ Galvanically isolated CAN interface
⚫ AEC-Q100 qual’ed components (when available)
⚫ Remote On/Off (galvanic isolated)
⚫ Forced-air cooled
⚫ Low-voltage Dev Board to be sold
⚫ Swap a few components and
update firmware to get full 11kW
Microchip Confidential & Proprietary
Vienna PFC Reference Design
The primary stage of a High-speed EV Charger
• 30 kW Vienna rectifier topology
• 98.5 % peak efficiency
• 3-phase 380/400 VAC, 50 Hz/60 Hz input voltage
• <5 % current THD at half and full loads
• Microchip 700 V, 15 mOhm SiC MOSFETs mounted on
AVVID MaxClip heat sinks to reduce communication
loop inductance and voltage spikes across devices
• PCB design according to IEC standards, with
consideration for safety, current stress, mechanical
stress, and noise immunity Matching 30kW LLC
• dsPIC33CH controller with verified open-source charger in development
software using 3-level modulation for digital control
Vienna Rectifier
Web Page and Components
DC Output +

Line 1

Line 2
EMI
Line 3 Filter

PE

DC Output -
SiC SBDs & MOSFETs (per phase)
MSC050SDA120B x 2
MSC015SMA070B x 4
Op Amps
MCP6021T-E
MCP6V51T-E Gate Bias
Drivers Supplies

Op Amp
Op Amp
MCP6021T-E Digital Signal MCP6021T-E
Controller
dsPIC33CH512MP506
CAN Bus
CAN
ATA6561-GAWQ-N

LDO +3.3V Precharge /

MIC39100-3.3WS Inrush Control
Automotive Digital Power Applications
Qi Wireless Charging Qi Spec dsPIC
Notes Coils Status
Rev 33C
Microchip’s Value Proposition: Board avail for
Fixed frequency Dual
MPA9 1.2.4 3 customer
• Automotive-grade controllers with optional CAN-FD topology Core
engagement

• Flexible firmware-based solutions that minimize external BOM MPA13

Fixed frequency
with optimized 1.2.4 3
Single
Board avail for
customer
Core
• Communication and FOD implemented with minimal components EMI/EMC engagement

• Qi 1.2.4 certified reference design available MPA13

Fixed frequency
with optimized 1.3 3
Single
Board for sale
targeted for
Core
EMI/EMC CQ3'21
• Microchip support for Qi 1.3 which includes Third party joint
USB-PD + Qi stack 1.2.4,
security/authentication MPA22 integrated in one then 1
Single
Core
promotions
planned starting
• Partnering with SPG for field training and customer dsPIC33 1.3
CQ2'21
engagement Customer-driven
Single Designer
Class-D 1.3 3 /Dual engaging their
• Bundle pricing initiative for reference solution underway custom topology
Core customers

• Hardware prototypes currently support Qi 1.2.4 Class-E

Third-party
partner custom
1.2.4
3
Single
Third-party joint
promotions
and 1.3 Core
topology planned
• Qi 1.3 prototypes Available Now

MCU16 Confidential and Proprietary

Automotive Digital Power Applications
USB Power Delivery Ground Shift Compensation
• USB PD up to 100W/ch today (going to 200W ?!?)
• Efficiency and thermal management critical

• dsPIC33 ideal for multiport implementations

• Single DSC integrates PD stack + power control • Patented solution eliminates the need for heavy
• Dual-channel PD source-side ref design copper ground wire
• Designed for automotive, 2 channels @ 45 Watts each • USB-PD hubs draw high current that causes ground
• Based on dsPIC33CK128MP505 shift at the hub resulting in USB data errors
• Scalability ≥4 ports is key benefit over other solutions • WPGSC controller cheaper than copper ☺
• TSS : UPD350, MCP14700, MCP6C02, MIC5060, MCP16331 • Fixed-function device based on dsPIC33CK
• Reference design nearly ready
• Developing dsPIC33-based USB PD powered Qi
Transmitter design • TSS : WPGSC, USB2xxxP,
• dsPIC33 integrates PD stack + Qi transmitter stack MCP1755, MCP16331,
• TSS : UPD350, MCP14700, MCP6C02, MIC5060, MCP16331 MCP14700

Microchip Proprietary and Confidential

Automotive Digital Power Applications
Higher Wattage Wireless Power
MCHP Components
• Example Automotive Use Cases: WP300TX
WP300RX
• Reduce expense and weight of wiring harnesses to seats TCN75AVUA713
• Recover additional cargo space in self-driving vehicles by making MCP16311
it easy to remove seats MCP1754S
MCP2200
MIC5281
• Productizing WP300 Tx/Rx fixed-function digital controllers MIC2104
• Evaluation board and App Note available today
• WP300 family is priced with royalty included
• MCU16 manages royalty payments with technology partner

• Working with partner to add customer requested features

MCU16 Confidential and Proprietary

EPC / Microchip Reference Designs
GaN-based Digital Power
EPC’s 300W 1/16th Brick IBC Converter
Reference Design Features
• Microchip dsPIC33CK digital signal controller
• EPC GaN FETs with 3.2 mΩ RDS(on)
• Two-phase synchronous buck topology
• 48 V in -> 12 V out
• Power density: 730 W/in3
• Output power: 300 W
• Peak efficiency: 95.8%
• Size: 1.3 x 0.9 x 0.4”
EPC’s 300W 1/16th Brick IBC Converter
dsPIC33C Gets the Most out of the Hardware

• Reference design firmware includes 2 modes of operation

• Multiloop controller: single voltage loop provides the same current reference IREF to two independent
inner current loops or
• Single voltage loop with enforced cycle-by-cycle PWM steering to automatically create balanced phase
currents

• 0.25ns PWM resolution for duty cycle and dead times

• Allows precision adjustment of dead times to fully harness the high performance of GaN FETs
EPC’s 300W 1/16th Brick IBC Converter
dsPIC33C Firmware Control Loop Example
• Single voltage loop with enforced cycle-by-cycle PWM steering
• Automatically creates balanced phase currents in multiphase powertrain

• Additional balancing used only to compensate component tolerances is run at a lower frequency
• Reduces current feedback bandwidth requirements thereby lowering BOM cost

• Enhanced feed-forward control scheme used to stabilize the loop gain across changing input and
output voltages
• Stabilizes the output impedance and allows output impedance tuning to optimize PDN decoupling

• Digital Type IV (4P4Z) voltage mode controller implemented to increase control bandwidth
• Roughly 15 times faster than a conventional multi-loop approach
• Reduces voltage deviations during transients
• Minimizes required PDN decoupling capacity
Backup Slides
dsPIC33 for Digital Power Conversion
Performance For More Sophisticated Algorithms
• Adaptive algorithms
• For improved efficiency over widely varying load conditions
• Implement phase shedding, real-time dead-time adjustment, variable switching frequency and
variable bulk voltage

• Predictive and non-linear algorithms

• For improved dynamic response to transient conditions

• Higher switching frequencies

• Smaller inductors and capacitors - save cost and space, improve power density

• Performance headroom
• For additional independent control loops or more outputs
• Run-time diagnostics, communications, predictive maintenance
Predictive and Non-linear Algorithms
Improve Dynamic Responsiveness
• Predictive Algorithms – e.g. bypass damping of control loops
• Non-linear Algorithms – e.g. real-time coefficient scaling

Decay / Boost
=60°
Modify compensator output by
non-linear factor(s)
=30°
 represents a vector:
Sum of the absolute value of Steady State
3 error samples vs 0 degree Linear compensator such as 3P3Z
vector representing errors
averaging zero =-30° Attack
Override compensator results
=- 60°
with min/max values for a
limited number of cycles
 dsPIC33 Automotive Ecosystem
Bootloaders
• MCC Bootloader
AUTOSAR BSW and OS support • Production Ready Bootloader – Simma SW and iHr
from 3rd party partners
MCAL Drivers from Microchip motorBench® Development Suite
GUI-based software tool for FOC motor control
MPLAB® X IDE, XC, MCC Integrated with MPLAB X IDE (MCC Library)
• Single IDE for all controllers
• Functional Safety XC Compiler
• Intuitive graphical programming tool MATLAB® and Simulink® for Motor Control
• Code Coverage plugin Development
Allows you to compile and flash a Simulink model
CAN BUS Solutions of a motor control system into a dsPIC33 DSC
High-speed CAN networking
solutions from our 3rd party partners PowerSmart Development Suite
Graphically design discrete compensation filters
LIN BUS Solutions Integrated with MPLAB X IDE (MCC Library)
LIN-compliant drivers from our
3rd party partners
Trace32 dsPIC33 debugger
10BASE-T1S- Single Pair Ethernet Full high-level and assembly
Expand the ethernet to edge nodes of OT networks debugger from Lauterbach

96
 AUTOSAR-Ready DSCs: Off-the-Shelf Support

AUTOSAR BSW AUTOSAR OS Configurator MCAL Drivers

(MICROSAR BSW) (KSAR OSEK) (EB Tresos Studio) (ASPICE and ASIL B compliant)

ASPICE/ASIL B compliant MCAL Drivers ADC DIO GPT SPI PWM

ICU MCU PORT FLS WDG
CRC CAN-FD* LIN* I2C**
Crypto Driver support for Secure Subsystem in dsPIC33CK Secure DSC or External TA100

Tools Chain

97 *CAN-FD and LIN drivers from Vector

** QM MCAL Driver for I2C
Low Power Wireless - Qi
Industry Standard Cell Phone Charging 5 – 15W
• MCHP is an active WPC member
• We have implemented Qi 1.2.4
• Qi Certification nearly complete
• Qi 1.3 development in progress (expect Spec release CQ3’20)
• Benefits of dsPIC33-based Qi Solutions
• Flexibility – Customers add their own differentiating features
• Multiple power conversion stages controlled by single DSC
• CAN and LIN interfaces and support
• AEC-Q100 Qual’ed Silicon
• E-temp (125C) and H-temp (150C) solutions
• CPNs that include IP royalties to MPEGLA available
• Three eval boards available
• Single and 3-coil, MPA9 and MPA13 topologies
Medium Power Wireless
Wirelessly Transmit 60 – 300W
• New Automotive Applications for Wireless Power
• Example: Wireless seats (no wiring harnesses for position motors)
• Easy seat removal and installation – multipurpose vehicles
• Potential weight reduction

• Family of fixed-function devices sampling now

• WP300TX01-E/ML001 and WP300RX01-E/ML001
• Features advanced FOD for safety
• Eval board available

• Customer Engagements
 ISO 26262 Functional Safety Packages

dsPIC33 DSC Functional Safety Basic Functional Safety Functional Safety

ISO 26262 Functional Safety Package Starter Package Advanced Package

FMEDA and Safety Manual ✓ ✓ ✓

Safety Reference Application ✓ ✓

✓ (Starter Package + Additional
TÜV Rheinland-certified Diagnostic Libraries ✓ (Select Modules*)
Modules*)

Safety Analysis Reports ✓

IP Protection NDA NDA and License Agreement NDA and License Agreement

*The complete list of supported modules and diagnostic functions offered within the libraries in ISO 26262 functional safety starter and advanced packages are shared under NDA.
100
Functional Safety Collateral
• Quantifies the device • Blueprint of how the
FIT rates, fault modes, device should be used
and corresponding including a description
detection methods to of hardware features Microchip eases
help create a coverage against dependent and Functional Safety
plan systematic failures
compliance with:
Safety • FMEDA
FMEDA
Manual • Safety Manual
• Diagnostic Software
• AEC-Q100 Qual Silicon
• Provides a starting • Benchmarking • Technical Support
point for achieving Software and • 3rd Party Tool Access
fault coverage for the Compliance
hardware device Management Tools • “Functional Safety Ready”
(LDRA) Products

Diagnostic Development
Software Tools