research-article

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs

Authors:

Sotirios Xydis,

Kiamal Pekmestzi,

Dimitrios Soudris,

George EconomakosAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 18, Issue 1

Article No.: 11, Pages 1 - 35

https://doi.org/10.1145/2390191.2390202

Published: 16 January 2013 Publication History

Abstract

Design space exploration during high-level synthesis targets the computation of those design solutions which form optimal trade-off points. This quest for optimal trade-offs has been focused on studying the impact of various architectural-level parameters during high-level synthesis algorithms, silently neglecting the trade-offs produced from the combined impact of behavioral-level together with architectural-level parameters. We propose a novel design space, exploration methodology that studies an extended instance of the solution space considering the effects of combining compiler- and architectural-level transformations. It is shown that exploring the design space in a global manner reveals new trade-off points, thus shifting towards higher quality design solutions. We use a combination of upper-bounding conditions together with gradient-based heuristic pruning to efficiently traverse the extended search space. Our exploration framework delivers significant quality improvements without compromising the optimality (Pareto accuracy) of the discovered solutions, together with significant runtime reductions compared to exploring exhaustively the solution space at every allocation scenario.

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Cited By

Ustun EYu CZhang Z(2023)Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247948(1-2)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247948
Reyes Fernandez de Bulnes DMaldonado YTrujillo L(2020)Development of Multiobjective High-Level Synthesis for FPGAsScientific Programming10.1155/2020/70950482020Online publication date: 1-Jan-2020
https://dl.acm.org/doi/10.1155/2020/7095048
Sengupta ABhadauria SMohanty S(2017)Low‐cost security aware HLS methodologyIET Computers & Digital Techniques10.1049/iet-cdt.2016.001411:2(68-79)Online publication date: 10-Jan-2017
https://doi.org/10.1049/iet-cdt.2016.0014
Show More Cited By

Index Terms

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 18, Issue 1

Special section on adaptive power management for energy and temperature-aware computing systems

January 2013

319 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2390191

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 16 January 2013

Accepted: 01 July 2012

Revised: 01 October 2011

Received: 01 February 2011

Published in TODAES Volume 18, Issue 1

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Cited By

Ustun EYu CZhang Z(2023)Equality Saturation for Datapath Synthesis: A Pathway to Pareto Optimality2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247948(1-2)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247948
Reyes Fernandez de Bulnes DMaldonado YTrujillo L(2020)Development of Multiobjective High-Level Synthesis for FPGAsScientific Programming10.1155/2020/70950482020Online publication date: 1-Jan-2020
https://dl.acm.org/doi/10.1155/2020/7095048
Sengupta ABhadauria SMohanty S(2017)Low‐cost security aware HLS methodologyIET Computers & Digital Techniques10.1049/iet-cdt.2016.001411:2(68-79)Online publication date: 10-Jan-2017
https://doi.org/10.1049/iet-cdt.2016.0014
Tsoutsouras VKoliogeorgi KXydis SSoudris D(2017)An Exploration Framework for Efficient High-Level Synthesis of Support Vector MachinesJournal of Signal Processing Systems10.1007/s11265-017-1230-188:2(127-147)Online publication date: 1-Aug-2017
https://dl.acm.org/doi/10.1007/s11265-017-1230-1
Xydis SPalermo GZaccaria VSilvano C(2015)SPIRIT: Spectral-Aware Pareto Iterative Refinement Optimization for Supervised High-Level SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.236339234:1(155-159)Online publication date: Jan-2015
https://doi.org/10.1109/TCAD.2014.2363392
Soudris DXydis SBaloukas CHadzidimitriou AChouvarda IStamatopoulos KMaglaveras NChang JRaptopoulos AManset DPierscionek BKayyali RPhillip NBecker TVaporidi KKondili EGeorgopoulos DSutton LRosenquist RScarfo LGhia P(2015)AEGLE: A big bio-data analytics framework for integrated health-care services2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2015.7363682(246-253)Online publication date: Jul-2015
https://doi.org/10.1109/SAMOS.2015.7363682
Farahini NHemani ASohofi HLi S(2015)Physical design aware system level synthesis of hardware2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)10.1109/SAMOS.2015.7363669(141-148)Online publication date: Jul-2015
https://doi.org/10.1109/SAMOS.2015.7363669
Raptopoulos AXydis SSoudris D(2015)Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE ApproachApplied Reconfigurable Computing10.1007/978-3-319-16214-0_49(531-541)Online publication date: 31-Mar-2015
https://doi.org/10.1007/978-3-319-16214-0_49

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