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Layout-driven RTL binding techniques for high-level synthesis using accurate estimators

Editor: C. L. Liu Authors:

Fadi J. KurdahiAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 2, Issue 4

Pages 312 - 343

https://doi.org/10.1145/268424.268425

Published: 01 October 1997 Publication History

Abstract

The importance of effective and efficient accounting of layout effects is well established in High-Level Synthesis (HLS), since it allows more realistic exploration of the design space and the generation of solutions with predictable metrics. This feature is highly desirable in order to avoid unnecessary iterations through the design process. In this article, we address the problem of layout-driven register-transfer-level (RTL) binding as this step has a direct relevance to the final performance of the design. By producing not only an RTL design but also an approximate physical topology of the chip-level implementation, we ensure that the solution will perform at the predicted metric once implemented, thus avoiding unnecessary delays in the design process.

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Cited By

Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
https://dl.acm.org/doi/10.1145/3609335
Guo LChi YWang JLau JQiao WUstun EZhang ZCong JShannon LAdler M(2021)AutoBridgeThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439289(81-92)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439289
Zheng HGurumani SRupnow KChen DBetz VConstantinides G(2014)Fast and effective placement and routing directed high-level synthesis for FPGAsProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554775(1-10)Online publication date: 26-Feb-2014
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Index Terms

Layout-driven RTL binding techniques for high-level synthesis using accurate estimators
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Physical design (EDA)
      1. Partitioning and floorplanning
  2. Very large scale integration design
    1. Application-specific VLSI designs

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Copyright © 1997 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 01 October 1997

Published in TODAES Volume 2, Issue 4

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Cited By

Guo LChi YLau JSong LTian XKhatti MQiao WWang JUstun EFang ZZhang ZCong J(2023)TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical DesignACM Transactions on Reconfigurable Technology and Systems10.1145/360933516:4(1-31)Online publication date: 5-Dec-2023
https://dl.acm.org/doi/10.1145/3609335
Guo LChi YWang JLau JQiao WUstun EZhang ZCong JShannon LAdler M(2021)AutoBridgeThe 2021 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3431920.3439289(81-92)Online publication date: 17-Feb-2021
https://dl.acm.org/doi/10.1145/3431920.3439289
Zheng HGurumani SRupnow KChen DBetz VConstantinides G(2014)Fast and effective placement and routing directed high-level synthesis for FPGAsProceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays10.1145/2554688.2554775(1-10)Online publication date: 26-Feb-2014
https://dl.acm.org/doi/10.1145/2554688.2554775
HAMADA NSAITO H(2012)Integration of Behavioral Synthesis and Floorplanning for Asynchronous Circuits with Bundled-Data ImplementationIEICE Transactions on Electronics10.1587/transele.E95.C.506E95-C:4(506-515)Online publication date: 2012
https://doi.org/10.1587/transele.E95.C.506
Cong JLiu BLuo GPrabhakar RHu JKoh C(2012)Towards layout-friendly high-level synthesisProceedings of the 2012 ACM international symposium on International Symposium on Physical Design10.1145/2160916.2160952(165-172)Online publication date: 25-Mar-2012
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Hamada NSaito HAtienza DXie YAyala JStevens K(2011)Integration of behavioral synthesis and floorplanning for asynchronous circuits with bundled-data implementationProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973042(157-162)Online publication date: 2-May-2011
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Xing XJong C(2009)Floorplan-driven multivoltage high-level synthesisVLSI Design10.1155/2009/1567512009(1-10)Online publication date: 1-Jan-2009
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Mukherjee RMemik S(2006)An integrated approach to thermal management in high-level synthesisIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2006.88640814:11(1165-1174)Online publication date: 1-Nov-2006
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Krishnan VKatkoori S(2006)Design Space Exploration of RTL Datapaths Using Rent Parameter based Stochastic Wirelength EstimationProceedings of the 7th International Symposium on Quality Electronic Design10.1109/ISQED.2006.48(364-369)Online publication date: 27-Mar-2006
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