research-article

Timing Path-Driven Cycle Cutting for Sequential Controllers

Authors:

Kenneth S. StevensAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 4

Article No.: 64, Pages 1 - 25

https://doi.org/10.1145/2893473

Published: 22 June 2016 Publication History

Abstract

Power and performance optimization of integrated circuits is performed by timing-driven algorithms that operate on directed acyclic graphs. Sequential circuits and circuits with topological feedback contain cycles. Cyclic circuits must be represented as directed acyclic graphs to be optimized and evaluated using static timing analysis. Algorithms in commercial electronic design automation tools generate the required acyclic graphs by cutting cycles without considering timing paths. This work reports on a method for generating directed acyclic circuit graphs that do not cut the specified timing paths. The algorithm is applied to over 125 benchmark designs and asynchronous handshake controllers. The runtime is less than 1 second, even for even the largest published controllers. Circuit timing graphs generated using this method retain the necessary timing paths, which enables circuit validation and optimization employing the commercial tools. Additional benefits show these designs are on an average a third in size, operate 33.3% faster, and consume one-fourth the energy.

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Cited By

Wibbels MChauviere BStevens K(2023)Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC58294.2023.10239605(60-70)Online publication date: 16-Jul-2023
https://doi.org/10.1109/ASYNC58294.2023.10239605

Index Terms

Timing Path-Driven Cycle Cutting for Sequential Controllers
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific integrated circuits

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 4

September 2016

423 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2939671

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

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Copyright © 2016 ACM.

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Association for Computing Machinery

New York, NY, United States

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 22 June 2016

Accepted: 01 February 2016

Revised: 01 January 2016

Received: 01 September 2015

Published in TODAES Volume 21, Issue 4

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Cited By

Wibbels MChauviere BStevens K(2023)Cyclic Timing Path Evaluation Using Commercial Static Timing Analysis Algorithms2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)10.1109/ASYNC58294.2023.10239605(60-70)Online publication date: 16-Jul-2023
https://doi.org/10.1109/ASYNC58294.2023.10239605

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