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TEI-power: Temperature Effect Inversion--Aware Dynamic Thermal Management

Published: 21 April 2017 Publication History

Abstract

FinFETs have emerged as a promising replacement for planar CMOS devices in sub-20nm technology nodes. However, based on the temperature effect inversion (TEI) phenomenon observed in FinFET devices, the delay characteristics of FinFET circuits in sub-, near-, and superthreshold voltage regimes may be fundamentally different from those of CMOS circuits with nominal voltage operation. For example, FinFET circuits may run faster in higher temperatures. Therefore, the existing CMOS-based and TEI-unaware dynamic power and thermal management techniques would not be applicable. In this article, we present TEI-power, a dynamic voltage and frequency scaling--based dynamic thermal management technique that considers the TEI phenomenon and also the superlinear dependencies of power consumption components on the temperature and outlines a real-time trade-off between delay and power consumption as a function of the chip temperature to provide significant energy savings, with no performance penalty—namely, up to 42% energy savings for small circuits where the logic cell delay is dominant and up to 36% energy savings for larger circuits where the interconnect delay is considerable.

References

[1]
V. Adler and E. G. Friedman. 1998. Repeater design to reduce delay and power in resistive interconnect. IEEE Transactions on Circuits and Systems II 45, 5, 607--616.
[2]
A. H. Ajami, K. Banerjee, and M. Pedram. 2005. Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 6, 849--861.
[3]
C. Alpert and A. Devgan. 1997. Wire segmenting for improved buffer insertion. In Proceedings of the Design Automation Conference. 588--593.
[4]
M. Ashoueil, H. Luijmes, J. Stuijt, and J. Huisken. 2010. Novel wide voltage range level shifter for near-threshold designs. In Proceedings of the International Conference on Electronics, Circuits, and Systems. 285--288.
[5]
H. B. Bakoglu. 1990. Circuits, Interconnections and Packaging for VLSI. Addison-Wesley.
[6]
K. Banerjee and A. Mehrotra. 2002. A power-optimal repeater insertion methodology for global interconnects in nanometer designs. IEEE Transactions on Electron Devices 49, 11, 2001--2007.
[7]
A. Bansal, M. Meterelliyoz, S. Singh, J. H. Choi, J. Murthy, and K. Roy. 2006. Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. In Proceedings of the Asia South Pacific Conference on Design Automation. 237--242.
[8]
D. Brooks and M. Martonosi. 2001. Dynamic thermal management for high performance microprocessors. In Proceedings of the Conference on High-Performance Computer Architecture. 171--182.
[9]
E. Cai and D. Marculescu. 2015. TEI-Turbo: Temperature effect inversion-Aware turbo boost for FinFET-based multi-core systems. In Proceedings of the International Conference on Computer-Aided Design. 500--507.
[10]
A. Calimera, E. Macii, M. Poncino, and R. I. Bahar. 2008a. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. In Proceedings of the International Symposium on Low Power Electronics and Design. 217--220.
[11]
A. Calimera, E. Macii, M. Poncino, and R. I. Bahar. 2008b. Temperature-insensitive synthesis using multi-Vt libraries. In Proceedings of the 18th Great Lakes Symposium on VLSI (GLSVLSI’08). 5--10.
[12]
M.-H. Chang, S.-Y. Lin, P.-C. Wu, O. Zakoretska, C.-T. Chuang, K.-N. Chen, C.-C. Wang, et al. 2013. Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. In Proceedings of the International Symposium on Circuits and Systems. 133--136.
[13]
F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, and G. Groeseneken. 2012. Understanding the basic advantages of bulk FinFETs for sub- and near-threshold logic circuits from device measurements. IEEE Transactions on Circuits and Systems II 59, 7, 439--442.
[14]
T. Cui, Y. Wang, S. Nazarian, and M. Pedram. 2015. Layout characterization and power density analysis for shorted-gate and independent-gate 7nm FinFET standard cells. In Proceedings of the ACM Great Lakes Symposium on VLSI.
[15]
S. Dhar and M. A. Franklin. 1991. Optimum buffer circuits for driving long uniform lines. IEEE Journal of Solid-State Circuits 26, 1, 32--40.
[16]
R. G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, and T. Mudge. 2010. Near-threshold computing: Reclaiming Moore’s law through energy efficient integrated circuits. Proceedings of the IEEE 98, 2, 253--266.
[17]
I. M. Filanovsky and A. Allam. 2001. Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits. IEEE Transactions on Circuits and Systems I 20, 48, 876--884.
[18]
M. Hansen, H. Yalcin, and J. P. Hayes. 1999. Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering. IEEE Design and Test 16, 3, 72--80.
[19]
R. Ho. 2003. On-Chip Wires: Scaling and Efficiency. Ph.D. Dissertation. Stanford University, Stanford, CA.
[20]
Y. Hu, K. H. Tam, T. T. Jing, and L. He. 2007. Fast dual-Vdd buffering based on interconnect prediction and sampling. In Proceedings of the Workshop on System Level Interconnect Prediction. 95--102.
[21]
X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, et al. 2001. Sub-50 nm P-channel FinFET. IEEE Transactions on Electron Devices 48, 5, 880--886.
[22]
ITRS. 2013. International Technology Roadmap for Semiconductors. Available at http://www.itrs2.net/2013-itrs.html.
[23]
S. Jain, S. Khare, S. Yada, V. Ambili, P. Salihundam, S. Ramani, S. Muthukumar, et al. 2012. A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference. 66--68.
[24]
R. Jayaseelan and T. Mitra. 2008. Temperature aware task sequencing and voltage scaling. In Proceedings of the International Conference on Computer-Aided Design. 818--623.
[25]
R. Jayaseelan and T. Mitra. 2009. Dynamic thermal management via architectural adaptation. In Proceedings of the Design Automation Conference. 484--489.
[26]
H. Jung, P. Rong, and M. Pedram. 2008. Stochastic modeling of a thermally-managed multi-core system. In Proceedings of the Design Automation Conference. 728--733.
[27]
S. O. Kasap. 2006. Principles of Electronic Materials and Devices (3rd ed.). Mc-Graw-Hill.
[28]
N. Kim, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandermir, et al. 2003. Leakage current: Moore’s law meets static power. IEEE Computer 36, 12, 68--75.
[29]
S.-Y. Kim, Y. M. Kim, K.-H. Baek, B.-K. Choi, K.-R. Han, K.-H. Park, and J.-H. Lee. 2007. Temperature dependence of substrate and drain-currents in bulk FinFETs. IEEE Transactions on Electron Devices 54, 5, 1259--1264.
[30]
C.-Y. Lee and N. K. Jha. 2013. FinCANON: A PVT-aware integrated delay and power modeling framework for FinFET-based caches and on-chip networks. IEEE Transactions on Very Large Scale (VLSI) Systems 22, 5, 1150--1163.
[31]
W. Lee, Y. Wang, T. Cui, S. Nazarian, and M. Pedram. 2014. Dynamic thermal management for FinFET-based circuits exploiting the temperature effect inversion phenomenon. In Proceedings of the International Conference on Low Power Electronics and Design. 105--110.
[32]
W. Lee, Y. Wang, and M. Pedram. 2015. Optimizing a reconfigurable power distribution network in a multicore platform. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, 7, 1110--1123.
[33]
W. Liao, L. He, and K. M. Lepak. 2005. Temperature and supply voltage aware performance and power modeling at micro architecture level. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 7, 1042--1053.
[34]
J. Lilis, C.-K. Cheng, and T.-T. Y. Lin. 1996. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE Journal of Solid-State Circuits 31, 3, 437--447.
[35]
Y. Liu, R. Dick, L. Shang, and H. Yang. 2007. Accurate temperature-dependent integrated circuit leakage power estimation is easy. In Proceedings of the International Conference on Design Automation and Test in Europe. 1--6.
[36]
A. Muttreja, P. Mishra, and N. K. Jha. 2008. Threshold voltage control through multiple supply voltages for power-efficient FinFET interconnects. In Proceedings of the International Conference on VLSI Design. 220--227.
[37]
A. Nalamalpu and W. Burleson. 2001. A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power. In Proceedings of the International ASIC/SOC Conference. 152--156.
[38]
E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri. 2004. Turning silicon on its edge. IEEE Circuits and Devices Magazine 20, 1, 20--31.
[39]
PTM. 2011. Predictive Technology Model. Available at http://ptm.asu.edu.
[40]
Yu Pu, X. Zhang, J. Huang, A. Muramatsu, M. Nomura, K. Hirairi, H. Takata, et al. 2010. Misleading energy and performance claims in sub/near threshold digital systems. In Proceedings of the International Conference on Computer-Aided Design. 625--631.
[41]
T. Sairam, W. Zhao, and Y. Cao. 2007. Optimizing FinFET technology for high-speed and low-power design. In Proceedings of the 17th ACM Great Lakes Symposium on VLSI (GLSVLSI’07). 73--77.
[42]
D. Shin, S. W. Chung, E. Chung, and N. Chang. 2010. Energy-optimal dynamic thermal management: Computation and cooling power co-optimization. IEEE Transactions on Industrial Informatics 6, 3, 340--351.
[43]
S. Soleimani, A. Afzali-Kusha, and B. Forouzandeh. 2008. Temperature dependence of propagation delay characteristic in FinFET circuits. In Proceedings of the International Conference on Microelectronics. 276--279.
[44]
K. H. Tam and L. He. 2005. Power optimal dual-Vdd buffered tree considering buffer stations and blockages. In Proceedings of the Design Automation Conference. 497--502.
[45]
L. P. P. P van Ginneken. 1990. Buffer placement in distributed RC-tree networks for minimal Elore delay. In Proceedings of the International Symposium on Circuits and Systems. 865--868.
[46]
X. Wang, A. Brown, B. Cheng, and A. Asenov. 2011. Statistical variability and reliability in nanoscale FinFETs. In Proceedings of the IEEE International Electron Devices Meeting. 541--544.
[47]
N. Weste and D. Harris. 2010. CMOSVLSI Design: A Circuits and Systems Perspective (4th ed.). Addison-Wesley.
[48]
Q. Xie, J. Kim, Y. Wang, D. Shin, N. Chang, and M. Pedram. 2013. Dynamic thermal management in mobile devices considering the thermal coupling between battery and application processor. In Proceedings of the International Conference on Computer-Aided Design. 242--247.
[49]
Y. Yang and N. K. Jha. 2013. FinPrin: FinFET logic circuit analysis and optimization under PVT variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22, 12, 2462--2475.
[50]
B. Zhai, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, et al. 2009. Energy-efficient subthreshold processor design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, 8, 1127--1137.

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  • (2024)TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based MulticoresACM Transactions on Embedded Computing Systems10.1145/3665276Online publication date: 16-May-2024
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Published In

cover image ACM Transactions on Design Automation of Electronic Systems
ACM Transactions on Design Automation of Electronic Systems  Volume 22, Issue 3
July 2017
440 pages
ISSN:1084-4309
EISSN:1557-7309
DOI:10.1145/3062395
  • Editor:
  • Naehyuck Chang
Issue’s Table of Contents
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 21 April 2017
Accepted: 01 November 2016
Revised: 01 November 2016
Received: 01 June 2016
Published in TODAES Volume 22, Issue 3

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Author Tags

  1. FinFET
  2. Ultralow power design
  3. interconnect delay
  4. near-threshold voltage
  5. temperature effect inversion
  6. ultralow voltage

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  • Research-article
  • Research
  • Refereed

Funding Sources

  • IT R&D Program of MSIP/IITP [16ZS1200:Near-Zero-Voltage Micro-Grain Architecture for Ultra-Low-Energy Processor]
  • the software-hardware foundations program of the CISE Directorate of the National Science Foundation

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Cited By

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  • (2024)TREAFET: Temperature-Aware Real-Time Task Scheduling for FinFET based MulticoresACM Transactions on Embedded Computing Systems10.1145/3665276Online publication date: 16-May-2024
  • (2024)Development of a Low-Power Touch-Based Lifelogging ProcessorIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2024.336841071:8(3910-3914)Online publication date: Aug-2024
  • (2022)Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-ChipsEnergies10.3390/en1518678015:18(6780)Online publication date: 16-Sep-2022
  • (2022)μAFLProceedings of the 44th International Conference on Software Engineering10.1145/3510003.3510208(1-12)Online publication date: 21-May-2022
  • (2022)RvDfi: A RISC-V Architecture With Security Enforcement by High Performance Complete Data-Flow IntegrityIEEE Transactions on Computers10.1109/TC.2021.313370171:10(2499-2512)Online publication date: 1-Oct-2022
  • (2022)Speed and Power Tradeoff Based on FinFET Structure, Voltage Changing and Circuit Layout2022 IEEE 5th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE)10.1109/AUTEEE56487.2022.9994548(465-470)Online publication date: 18-Nov-2022
  • (2021)TEI-DTA: Optimizing a Vehicular Sensor Network Operating with Ultra-Low Power System-on-ChipsElectronics10.3390/electronics1015178910:15(1789)Online publication date: 26-Jul-2021
  • (2021)Developing TEI-Aware Ultralow-Power SoC Platforms for IoT End NodesIEEE Internet of Things Journal10.1109/JIOT.2020.30274798:6(4642-4656)Online publication date: 15-Mar-2021
  • (2020)Design of a DC–DC Converter Customized for Ultra-Low Voltage Operating IoT PlatformsEnergies10.3390/en1302046113:2(461)Online publication date: 17-Jan-2020
  • (2020)Dynamic differential signaling based logic families for robust ultra-low power near-threshold computingMicroelectronics Journal10.1016/j.mejo.2020.104801102(104801)Online publication date: Aug-2020
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