research-article

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability

Authors:

David Z. PanAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 14, Issue 2

Article No.: 32, Pages 1 - 21

https://doi.org/10.1145/1497561.1497575

Published: 07 April 2009 Publication History

Abstract

In this article, we present BoxRouter 2.0, and discuss its architecture and implementation. As high-performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose a global router which has a strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is extended from BoxRouter 1.0, but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: node shifting for congestion-aware Steiner tree and robust negotiation-based A* search for routing stability. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) the widely used ISPD98 benchmark for the first time in the literature with the shortest wirelength. We further generate a set of harder ISPD98 benchmarks to push the limit of BoxRouter 2.0, and propose the hardened ISPD98 benchmarks to map state-of-the-art solutions for future routing research.

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Cited By

Liu GZhu YZhuang ZPei ZGan MHuang XGuo W(2024)A Robust Multilayer X-Architecture Global Routing System Based on Particle Swarm OptimizationIEEE Transactions on Systems, Man, and Cybernetics: Systems10.1109/TSMC.2024.340796054:9(5627-5640)Online publication date: Sep-2024
https://doi.org/10.1109/TSMC.2024.3407960
Siddiqi USait S(2024)A Deterministic Concurrent-Routing Algorithm to Improve Wire Selection in FPGA Routing2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV)10.1109/ICDV61346.2024.10616485(160-165)Online publication date: 6-Jun-2024
https://doi.org/10.1109/ICDV61346.2024.10616485
Wang RXu NZhang J(2024)A Global Router with Topology Optimization on Hanan Grid2024 13th International Conference on Communications, Circuits and Systems (ICCCAS)10.1109/ICCCAS62034.2024.10652868(358-363)Online publication date: 10-May-2024
https://doi.org/10.1109/ICCCAS62034.2024.10652868
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Index Terms

BoxRouter 2.0: A hybrid and robust global router with layer assignment for routability
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 14, Issue 2

March 2009

384 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/1497561

Issue’s Table of Contents

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 07 April 2009

Accepted: 01 November 2008

Revised: 01 March 2008

Received: 01 July 2007

Published in TODAES Volume 14, Issue 2

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Cited By

Liu GZhu YZhuang ZPei ZGan MHuang XGuo W(2024)A Robust Multilayer X-Architecture Global Routing System Based on Particle Swarm OptimizationIEEE Transactions on Systems, Man, and Cybernetics: Systems10.1109/TSMC.2024.340796054:9(5627-5640)Online publication date: Sep-2024
https://doi.org/10.1109/TSMC.2024.3407960
Siddiqi USait S(2024)A Deterministic Concurrent-Routing Algorithm to Improve Wire Selection in FPGA Routing2024 9th International Conference on Integrated Circuits, Design, and Verification (ICDV)10.1109/ICDV61346.2024.10616485(160-165)Online publication date: 6-Jun-2024
https://doi.org/10.1109/ICDV61346.2024.10616485
Wang RXu NZhang J(2024)A Global Router with Topology Optimization on Hanan Grid2024 13th International Conference on Communications, Circuits and Systems (ICCCAS)10.1109/ICCCAS62034.2024.10652868(358-363)Online publication date: 10-May-2024
https://doi.org/10.1109/ICCCAS62034.2024.10652868
Kundu SRoy SMukherjee S(2022)Congestion-Aware Rectilinear Steiner Tree Construction Using PB-SATJournal of Circuits, Systems and Computers10.1142/S021812662250165131:09Online publication date: 5-Mar-2022
https://doi.org/10.1142/S0218126622501651
Saha KPaul SBanerjee PSur-Kolay S(2022)Stitch-avoiding Global Routing for Multiple E-Beam Lithography2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID)10.1109/VLSID2022.2022.00037(138-143)Online publication date: Feb-2022
https://doi.org/10.1109/VLSID2022.2022.00037
Ju XZhu KLin YZhang L(2021)Asynchronous Multi-Nets Detailed Routing in VLSI using Multi-Agent Reinforcement Learning2021 7th IEEE International Conference on Network Intelligence and Digital Content (IC-NIDC)10.1109/IC-NIDC54101.2021.9660569(250-254)Online publication date: 17-Nov-2021
https://doi.org/10.1109/IC-NIDC54101.2021.9660569
Pandiaraj KSivakumar PPrakash K(2021)Machine learning based effective linear regression model for TSV layer assignment in 3DICMicroprocessors & Microsystems10.1016/j.micpro.2021.10395383:COnline publication date: 1-Jun-2021
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Chen GPui CLi HYoung E(2020)Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path SearchIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.292754239:9(1902-1915)Online publication date: Sep-2020
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Tang HLiu GChen XXiong N(2020)A Survey on Steiner Tree Construction and Global Routing for VLSI DesignIEEE Access10.1109/ACCESS.2020.29861388(68593-68622)Online publication date: 2020
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Chen XLiu GXiong NSu YChen G(2020)A Survey of Swarm Intelligence Techniques in VLSI Routing ProblemsIEEE Access10.1109/ACCESS.2020.29715748(26266-26292)Online publication date: 2020
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