Repeater

In large chips, the propagation delay of the data and clock signals can limit performance due to long resistive interconnect. The insertion of repeaters alleviates the quadratic increase in propagation delay with interconnect length while decreasing power dissipation by reducing short-circuit current, In order to develop a repeater design methodology, a timing model characterizing a complementary metal-oxide-semiconductor (CMOS) inverter driving a resistance-capacitance (RC) load is presented. The model is based on the Sakurai short-channel α-power law model of transistor operation. The inverter model is applied to the problem of repeaters to produce design expressions for determining the optimum number of uniformly sized repeaters to be inserted along a resistive interconnect line for reduced delay. For a wide variety of typical RC loads, this analytical repeater model exhibits a maximum error of 16% as compared to a dynamic circuit simulator (SPICE). The advantage of uniformly sized repeaters versus tapered-buffer repeaters is also investigated using the repeater model presented in this paper. It is shown that uniform repeaters remain advantageous over tapered buffers and tapered-buffer repeaters even with relatively small resistive RC loads. An expression for the short-circuit power dissipation of a repeater driving an RC load is presented, A comparison of the short-circuit power dissipation to the dynamic power dissipation in repeater chains and related power/delay tradeoffs are made

In system-on-chip (SoC) integration, silicon intellectual properities (IPs) are blockages for long inter connection. With this stipulation,conventional plans are complled to place those repeaters that drive long inter connection and more power canbe used in ip.It permits the cross-IP interconnection to be steered over the IP utilizing,the Repeaters Implanted within the IP and also On-chip bias generation will be implanted.Design was improve power consumption Outcomes show that suggested style doesn’t just create the bottom plan with soc simpler,however will also improve the power consumption of the long interconnection circuits.

A model for delay evaluation and minimization in logic paths with gates and RC wires is presented. The method, Unified Logical Effort (ULE), provides closed-form conditions for timing optimization while overcoming the breakdown of standard logical effort (LE) rules in the presence of interconnect. The ULE delay model and optimization unifies the problems of gate sizing and repeater insertion: In