THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

THE MYTH OF GROUND BOUNCE APPLICATION

MEASUREMENTS AND NOTE
AN-147
COMPARISONS
Integrated Device Technology, Inc.

By Stanley Hronik

INTRODUCTION GROUND BOUNCE DESCRIPTION

Ground Bounce is one of the primary causes of false Ground Bounce is a voltage oscillation between the ground
switching in high speed components and is a major cause of pin on a component package and the ground reference level
poor signal quality. While ground bounce is easily measured on the component die. Essentially it is caused by a current
on CMOS components, an accurate measurement is some- surge passing through the lead inductance of the package.
what elusive on bipolar or BiCMOS components. For compo- The effect is most pronounced when all outputs switch simul-
nents with a bipolar or BiCMOS output structure, any reading taneously, (hence the alternate name, Simultaneous Switch-
obtained through standard ground bounce tests will be sev- ing Noise). While the inductance is the combined effect of the
eral hundred milivolts low. This is due to the inability of these package lead, the package lead frame, the bond wire and the
components to hold a solid logic low level with low impedance. inductance in the die pad, most of the inductance is caused by
The accompanying characteristic of Vcc bounce is less the bond wire.
troublesome than ground bounce, but will have a greater Figure 1 shows a typical waveform for a high speed CMOS
influence as Vcc levels drop to 3.3V, 2.5V and lower. Vcc component with TTL level outputs. Shown directly above the
bounce is easily measured only on components that have a signal waveform on the same time scale is the voltage seen on
CMOS rail swing output. Since there is no direct connection the ground of the die relative to the external ground. Directly
to Vcc in any component except components with CMOS rail above that is the voltage seen on the die Vcc relative to the
swing outputs, the measurement of Vcc bounce is not directly external Vcc on the board.
6
possible in many standard logic families.
5.5
TABLE OF CONTENTS Vcc voltage level on the die Vohp
Volts

5
GROUND BOUNCE DESCRIPTION .............................. 89
The Ground Bounce Effect in CMOS .......................... 90 4.5 Vohv
The Ground Bounce Effect in BiCMOS ...................... 90
PROBLEMS CREATED BY BOUNCE ........................... 91 4
False Switching ........................................................... 91 1
Volp
Poor Signal Quality ..................................................... 93 0.5
BOUNCE MEASUREMENTS ......................................... 93 Die Ground voltage
Volts

Traditional Ground Bounce Measurements ................ 93 0

Accurate Ground Bounce Measurements .................. 93 Volv

-0.5
Measuring Vcc Bounce ............................................... 94
-1
BOUNCE INFLUENCES ................................................ 94
3.5
Drive Level Effect on Ground Bounce ......................... 94
Fast Edge Rates ......................................................... 95 3
Crossover Current ....................................................... 95 2.5
Package Effect on Ground Bounce ............................. 96
Voltage (Volts)

Double Density Packaging .......................................... 96 2

Octal Packaging .......................................................... 96 1.5

Load Effect on Ground Bounce ................................... 96 1
DESIGN CONSIDERATIONS ........................................ 96
Choose the Right Driver .............................................. 96 0.5

Avoid Pull Up Resistors on BiCMOS ........................... 97 0

OE with Clock HIGH .................................................... 97
-0.5
Slow Clock Edges ....................................................... 97
Bus Inverting Components .......................................... 97 -1
-1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Use Bus-hold .............................................................. 97 Time (ns)
Avoid Ground Bounce in Memory Arrays ................... 98 Figure 1, Ground Bounce
CONCLUSION ............................................................... 98
As shown in Figure 1, ground bounce and Vcc bounce
cause signal degradation in the output waveform of the
device. This consists of an undershoot and overshoot on
both the rising and falling edges of the waveform.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.

©1996 Integrated Device Technology, Inc. 3574/-

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THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

There are four parameters for measuring ground bounce 140

and Vcc bounce which are identified in Figure 1. In the order
120
of significance they are:
100

Output Current (mA)

Volp — peak voltage of the ground bounce, 80
Volv — valley voltage of the die ground during bounce
60
Vohv — negative voltage change in Vcc during bounce
Vohp — peak voltage change in Vcc during bounce 40

20
When reading specifications for ground bounce, the pa-
0
rameter most often used to identify the ground bounce level is
Volp. In statements such as “Ground Bounce = XX volts”, this -20
is the parameter being referenced. -40
Ground Bounce levels are typically more pronounced than -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Volts
Vcc Bounce levels because of the HIGH to LOW transition is
trying to quickly bring a HIGH signal down to a narrow window Figure 3, FCT Output VI Curve for Vol
of <400mV for a logic LOW. A low output impedance is
required to complete the transition quickly. In the LOW to As a CMOS component makes a transition from a HIGH to
HIGH, the only requirement is that the output be above 2.4V. a LOW as shown in Figure 4, the pull down FET will lock (6.5Ω
5V is available as a driving voltage. A much lower pull up impedance) the device output to Die GND in Figure 2. To
impedance is required to make the transition quickly. accomplish this task, the pull down FET will be required to
discharge the internal capacitances of the die. This causes a
The Ground Bounce Effect in CMOS
sudden surge of current from the Die GND to the Board GND.
The output structure for a CMOS component with TTL level The current surge then causes a voltage drop across the
outputs is shown in Figure 2. In addition to the structure ground lead inductance. If all device outputs switch simulta-
shown, the output contains resistors in most components neously, the instantaneous current through the ground lead
which will dampen the output waveforms and reduce the inductance can be significant.
effects of ground bounce and Vcc bounce. In order to simplify
the drawings and discussion, these have been eliminated
4
from the drawing.
DIE Boundary Package
Boundary 3

2
Output Voltage

1
Inductive Ringing
Output
0

-1

-2
-1 0 1 2 3 4 5 6 7 8 9 10
Time (ns)

Die GND Board GND Figure 4, Undershoot in CMOS from Ground Bounce

Figure 2, CMOS Device Output Structure Figure 4 shows the waveform visible to the outside world
from a HIGH to LOW transition. The transition is clean from
There is a clamp diode between the device output and the the Voh level to zero, but the lead inductance continues to
Die GND on all CMOS components. In ground bounce cause ringing. With an N-Channel FET pull down, the output
discussions, this clamp diode can be ignored. During HIGH to will be tied closely to the Die GND regardless of whether the
LOW transitions, the pull down FET will be at a very low Die GND is above or below the Board GND.
impedance from drain to source. Transitions of the Output
below ground will be caused by a voltage drop across the lead The Ground Bounce Effect in BiCMOS
inductance and will not forward bias the clamp diode. BiCMOS components have a different output structure
Figure 3 shows the VI curve for a typical FCT High Drive than CMOS components and have significantly higher ground
CMOS component with TTL output levels. The curve is very bounce than CMOS due to a much faster edge rate, lower
flat at 6.5Ω throughout the operating region around zero volts. output impedance, and the lack of a control on signals that
This flatness continues below zero until the effect of the clamp overshoot. As a result the noise generated has different
diode to Die GND takes effect at about -0.7V. effects than CMOS components.

90
THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

4
DIE Boundary Package
Boundary 3

Output Waveform (Volts)

2

0
Vo = 0.75V
250mV
-1
+ -
-2

10
-1

-0

9
2

8
Volp = 0.5V Time (ns)
Die GND Figure 7, Undershoot in BiCMOS
Board GND

Figure 5, Output Structure of BiCMOS Figure 8 shows how the same component as in Figure 7
would respond if the 500Ω load was significantly reduced
Figure 5 shows the output structure for a BiCMOS compo- (higher resistance value). When the output of a component
nent with a darlington pull up and a bipolar NPN pull down. such as ABT or LVT is tied to a device with a CMOS or
The VI curve for the pull down is shown in Figure 6. Unlike the BiCMOS input, the input clamp diode will draw the undershoot
very linear characteristics of CMOS (Figure 3), the NPN pull of the BiCMOS quickly back close to zero, giving a quick
down of BiCMOS will pull the output to a minimum of about 200 undershoot blip and then a steady state at -0.7V.
to 250 mV and then shut off. If the output transitions below this
4
value, no current will flow into or out of the device output.
Because of this, the lowest that a BiCMOS component can
3
guarantee pulling a very light load is about 250mV. This
causes a lack of noise immunity in high speed circuits.
2
Output Voltage

140

120 1

100
0
Output Current (mA)

80

60 -1

40
-2
20

10
-1

-0

9
2

8
0 Time (ns)

-20 Figure 8, BiCMOS response, low resistive load

2Ω
-40
-0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 PROBLEMS CREATED BY BOUNCE
Volts at the Output The problems created by ground bounce fall into two
Figure 6, ABT Output V/I for Vol
related categories, namely false switching and poor signal
quality. Both of these problems are the result of the die ground
Another characteristic of BiCMOS is the steepness of the moving relative to the external device ground.
VI curve once it passes the 200mV output level. In order for
False Switching
a component like ABT to guarantee 64mA current at 0.55V,
the slope of the VI curve goes to about 2Ω above 300mV. This False switching may occur when the die ground or die Vcc
very low output impedance causes extremely fast edge rates reference voltage bounces enough to cause the input toggle
and significant line termination problems. point of the die to shift enough to pass through a guaranteed
As shown in Figure 7 a BiCMOS component has a strong logic threshold.
negative undershoot caused by the inductive kick of the For 5 volt components, the toggle point is about 1.5V and
package. Unlike CMOS components there is no recovery the guaranteed thresholds are 800mV and 2.0V for a logic
from the negative undershoot and the output does not try to LOW and HIGH. As shown in the following examples, it is fairly
pull back to zero. The plot of Figure 7 is into a standard 50pF/ easy for violate a threshold with Ground Bounce. The Vcc
500Ω load and it is the 500Ω to GND that causes the signal to level of 5V is not close to the toggle point of 1.5V and
return to ground.

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THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

proportional shifting of the toggle point relative to Vcc has a

minimal effect on false switching. Therefore for 5V compo- DIE Boundary
Package
Boundary
nents, Ground Bounce has a distinct possibility of causing
false switching where Vcc Bounce is much less of a problem.
For 3.3V components that can operate with voltages as low Vin = 0.8V
as 2.7V, Vcc is much closer and has more influence in output
and input levels. In 3.3V components Vcc bounce can
become a significant factor. 1.5V = Toggle
BiCMOS components such as ABT which have a high + -
internal bounce due to a very fast output edge rate are very
likely to false switch unless the input signals are maintained Volv = 0.7V
with HIGHs well above the threshold and LOWs near GND. Board GND Die GND
Special caution must be taken with driving BiCMOS with
BiCMOS because BiCMOS cannot maintain a solid LOW near Figure 10, Volv = 0.7V can cause false switching
zero and BiCMOS requires an input low which is near zero to
avoid false switching. DIE Boundary Package
Figure 9 demonstrates how a ground bounce level as low Boundary
as 0.5V can cause device upset. If the input voltage is sitting
at the minimum guaranteed high of 2.0V, and the input toggle
point is at the nominal 1.5V point, and the die bounces 0.5V,
the combined bounce and toggle point voltages equal the
input voltage and could cause the device to toggle. Obviously, Vo = 0.5V
as the ground bounce increases, the input voltage will have to 0.0V
increase in equal amounts to avoid toggling due to ground + -
bounce.
Volp = 0.5V
Package DIE Boundary Die GND Board GND
Boundary
Figure 11, Output Problems with Volp on CMOS
Vin = 2.0V
Figure 11 shows how 0.5V Volp can cause the output to rise
an equal amount. A situation like this may be significant if the
output is attempting to hold a clock signal at a quiet steady
1.5V = Toggle
state voltage. The problem is compounded with BiCMOS as
- + shown in Figure 12 where the BiCMOS is not capable of
holding the output at the Die GND level. In this case, the
Volp = 0.5V output voltage can easily rise above the guaranteed output
Board GND Die GND
LOW level of 0.55V. Increasing levels of Volp could easily
Figure 9, How 1/2 Volt GB can cause upset take the output voltage above 800mV (logic LOW level).

Figure 10 demonstrates a similar problem, this time caused

by Volv. As shown in the figure, if Volv is 0.7V and the toggle
point is still 1.5V, the combination of the two can bring the input DIE Boundary Package
Boundary
threshold below the guaranteed low point of 0.8V on the input.
Increasing Volv lowers the point at which a logic low will cause
false switching. Guaranteeing a lower input voltage provides
more forgiveness to high Volv levels.

Vo = 0.75V
250mV

+ -

Volp = 0.5V
Die GND
Board GND

Figure 12, Output Problems with Volp on BiCMOS

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THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

Poor Signal Quality

The first effect that a designer will see from a component
with high ground bounce is poor signal quality as shown in 50pF
Figure 1. In CMOS components, the output is tied directly to 500Ω
the Die GND through the pull down FET. If the die is bouncing
and ringing, this noise will extend directly to the device output
and into the signal path. The effect of the Ground Bounce will 50pF
500Ω
be enhanced if the transmission line is inductive and the
inductive kick extends the peaks and valleys of the noise..
In BiCMOS components, the bouncing die will have less 50pF
influence on the output signal because the pull down will be in 500Ω
a high impedance state as the output approaches and goes
below zero. The effect seen will be the BiCMOS component
50pF
pulling the output very low (typically around -2.0V for ABT) and
500Ω
then going into a high impedance state, allowing the line to
control the rebound if any. It is not uncommon to see ABT with
severe Ground Bounce driving a bus with a clean waveform, 50pF
except the Vol is running at a voltage below zero because ABT 500Ω
cannot rebound.
50pF
BOUNCE MEASUREMENTS 500Ω
There is a traditional method for measuring both Ground
Bounce and Vcc Bounce on a component without changing
the test setup between the two tests. While this test is fairly 50pF
500Ω
accurate for measuring Ground Bounce on CMOS type com-
ponents, the results are up to several hundred milivolts low for
BiCMOS devices. The Vcc Bounce measurements are im-
properly taken and do not reflect Vcc Bounce, but rather
another phenomena that will be discussed when discussing
Vcc Bounce measurements. Figure 13, Standard Ground Bounce Measurement

Traditional Ground Bounce Measurements Since there is little switching current in the “quiet” output,
The traditional method of measuring ground bounce is the lead inductance for that output should have very little
shown in Figure 13. All outputs are connected to a standard voltage drop and not significantly affect the measurement.
load of 50pF/500Ω. The plan is to force all outputs except one This becomes less true as the ground bounce level increases.
to toggle from a logic HIGH to a logic LOW simultaneously The lead inductance in each of the loaded outputs that are
causing ground bounce to occur. The remaining one output switching has only a small effect on the die voltage. The
is solidly held at a logic LOW. The philosophy is that the output common ground pin must pass the combined currents from all
help at a logic LOW has a low impedance path to the Die GND of the switching outputs and therefore will exhibit the greatest
and therefore will accurately show the voltage swings of the voltage drop.
Die GND relative to the ground level on the external pin. Improvements in the measuring technique for CMOS could
be accomplished by using the standard set up, but removing
the output load on the “quiet” output. This would reduce the
damping factor of the load. When using a high impedance fast
oscilloscope, these ground bounce measurements should be
fairly accurate.
This measurement technique is fairly accurate for compo-
nents with FET output drivers such as FCT and ACT.
BiCMOS components with bipolar NPN output drivers have
a very high impedance when the output is held near zero. For
BiCMOS the stabilizing effect of the load on the output will kill
the accuracy of the test, even if the load is only the test fixture
and scope probe. The BiCMOS high impedance output will
not track the Die GND until the bounce has exceeded approxi-
mately 300mV.
Accurate Ground Bounce Measurements
While there is no proven technique for measuring ground

93
THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

bounce in BiCMOS, there needs to be a common test that can BOUNCE INFLUENCES
be used for component comparison regardless of whether the When designing with high speed logic, there are several
component is CMOS or BiCMOS. items that have an influence on the bounce levels seen in high
One possibility is a threshold toggle test. This could use the speed circuits. By considering these items during design,
present test set up. With all outputs quiet, a single input would many of the bounce problems can be avoided.
be slowly raised from zero through the threshold to determine
the toggle point. Once the toggle point is determined, stan- Drive Level Effect on Ground Bounce
dard ground bounce testing takes place except the quiet input The ringing seen on the HIGH to LOW transition of a CMOS
would be slowly raised to identify the point of switching again. component is the ringing of the lead inductance caused by
Approaching the toggle point from both the HIGH and LOW internal current surges caused by the switching of internal
and then multiplying the results by the scale factor of Figure 14 capacitances. The impedance of the pull down FET will
would give an approximation for Volv and Volp. dampen the switching action and lower the peak on the initial
surge. The amount of damping is directly related to the
5V
Scale Factor = = 1.43 impedance in the pull down stage and more damping lowers
3.5V the Ground Bounce.
Vcc Vcc Vcc
Figure 14, Scale Factor For Ground Bounce Threshold Test
28Ω 28Ω 40Ω
This test would identify the false switching levels caused by
ground bounce and may actually be of more interest to the
designer than the traditional ground bounce numbers. Output Output Output
An additional possibility for testing BiCMOS would be to
simply add the offset voltage of 200 or 300mV to the under- 6Ω 12.5Ω 32Ω
shoot of one of the switching outputs from the traditional test
to arrive at Volv. This cannot be added to the low going blip
on the quiet pin because of the turn on time of the pull down FCT16xxxT FCT162xxxT FCT166xxxT
transistor (CMOS is always “on”, bipolar shuts off). There is Figure 16, Double Density Output Structures
no way to use this method to identify Volp because the output
is completely shut off during Volp and cannot be used to drive Figure 16 shows the output structures for IDT’s Double
any signal. Density logic families. Each contains an impedance in the pull
down structure of the device. In addition to the line driving and
Measuring Vcc Bounce termination benefits of these resistors, they also help control
Vcc Bounce is the reverse of Ground Bounce and is the ground bounce. Placing these in the source of the FET, any
amount the die Vcc fluctuates relative to the external Vcc currents caused by the FET switching internal capacitances
when all outputs switch from a logic LOW to a logic HIGH must be through these resistors.
simultaneously. Vcc bounce is directly measurable only in Vcc Vcc
CMOS rail swing components which have a fairly strong pull
up structure. Vcc bounce cannot be directly measured in any 28Ω 28 Ω
TTL level CMOS or BiCMOS components.
Output Output
The traditional Vcc Bounce measurement is done with the
same test set up as Ground Bounce in Figure 13, Except the
“quiet” output is held HIGH. The theory is that the quiet output 6Ω
will be held to die Vcc by the output structure in the component 6Ω
and any movement in Die Vcc will be reflected in this measure-
ment. This is true only for rail swing CMOS components that
have the P-Channel pull up. Any TTL level component will Poor Design Better Design
have a high impedance as the output approaches Vcc, killing Figure 17, Lowering Device Ground Bounce
the results of the test. CMOS rail swing components that have
Power-off Disable or 5V tolerant 3V outputs will also have a If the pull down FET is tied directly to the Die GND as shown
high impedance state above Vcc, killing the Vcc test. in Figure 17, when the FET switches, the charge from internal
5V capacitances is dumped more directly into the Die GND
Scale Factor = = 3.33 without passing through the resistor. This will increase the
1.5V device ground bounce. Therefore of the components shown
Figure 15, Scale Factor for Vcc Bounce Threshold Test
in Figure 16, the FCT16xxxT will have the highest ground
bounce of the three and the FCT166xxxT will have the lowest.
There is no accurate test for Vcc bounce used that exists as
Approximate values of ground bounce for these devices are:
a standard in the industry today. The threshold test that was
FCT166xxxT = 200mV
described for Ground Bounce could also be used to estimate
FCT162xxxT = 600mV
Vcc bounce when used with a different scale factor as shown
FCT16xxxT = 900mV
in Figure 15.

94
THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

When looking at BiCMOS components as shown in Figure ground bounce level than one with a 32Ω output impedance
18, the drive level is non linear, but is extremely strong once (solid fact).
the 250mV threshold is exceeded for a LOW. This low
Crossover Current
impedance causes significant levels of bounce. For an ABT
type component, the impedance is close to infinite until the In order for high speed logic to achieve the fastest possible
250mV threshold is crossed. Once the threshold is crossed, speeds, it is necessary for the internal stages of the compo-
the impedance drops to about 2Ω. nent to respond as fast as possible to a transition. To
accomplish this, high speed components are designed to
Vcc
respond early and quickly to changes on the input. This
results in a brief internal contention as the component is
attempting to pull itself both up and down at the same time. As
both pull up and pull down stages are active, a leakage from
Output
Vcc to GND through the component will result as shown in
Figure 20. ∆Icc is a measure of the input crossover current
and Iccd is a measure of the total crossover current during
Non Linear switching. Both parameters are specified in the Logic Data
Impedance book. IDT FCT logic has the lowest crossover currents in the
industry.
Vcc

Figure 18, BiCMOS Output Structure

Output
The darlington pull up has very high gain until the output
voltage exceeds the Voh level. A rising edge will see a low I
impedance from the darlington and rise quickly until the pull up
driver shuts off and goes into a high impedance mode. This
sudden change in drive current will cause an overshoot and
recovery on a LOW to HIGH transition. The N-Channel pull up
of CMOS has a very linear impedance which is higher than Figure 20, The Path of Crossover Currents
BiCMOS and will arrive at the correct Voh with far less
overshoot. Crossover currents will add slightly to the Ground Bounce
Fast Edge Rates and Vcc Bounce of a component. There is no effective test to
Ground Bounce is caused primarily by the lead inductance identify the bounce caused by crossover currents for a HIGH
of the ground pin of the component package. The Ground to LOW transition, but for the LOW to HIGH, the standard
Bounce is the voltage drop across this inductance. The Ground Bounce test for CMOS is effective for CMOS. During
voltage equation for an inductor is shown in Figure 19. the HIGH to LOW transition of the test, the “quiet” output will
exhibit Ground Bounce while the LOW to HIGH transition will
di
V= L exhibit bounce due to crossover currents. As a logic transition
dt occurs, the crossover current will begin to short the Vcc and
Figure 19, Equation for the Voltage across an inductor
GND on the die. This will be seen as a bounce on the Die GND
during the transition.
Basically the equation states that the Ground Bounce
1
Bounce Due to Crossover

voltage (voltage on the Die GND) is a direct result of the surge

in current in the lead inductance between the die and external 0.75
ground. To avoid the surge in current, the edge rate of the
logic level change should be held to a minimum. From Ohms 0.5
law we see V=RI. Modifying the equation for dynamic condi- Input Stage
0.25 Crossover
tions and grossly simplifying the situation we arrive at:
∆V = R∆I 0
From this we can see that the edge rate ∆V is proportional -0.25
to the change in current ∆I. Using TTL level components as Output Stage
an example, the change in voltage is set at about 3.2V -0.5 Crossover
(simplified). The surge in current ∆I is controlled by the -0.75
attenuation of R (simplified). Since R is the output impedance
of the component, the ground bounce is directly proportional -1
-0.5

0.5

1.5

2.5
-1

to the output impedance (simplified). Therefore a component

with 2Ω output impedance will have a significantly higher Time (ns)
Figure 21, Crossover Bounce

95
THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

Low crossover currents will help reduce noise from bounce. Octal Packaging
Most manufactures are fairly loose with their specifications for Figure 22 shows a greatly simplified package diagram for
Iccd and ∆Icc to prevent failing during final test due to these an octal component with a huge overgrown die. The com-
parameters. As a result the best place for a designer to find bined effect of the pin, leadframe and bond wire are shown as
actual values is in application notes such as IDT’s Application an inductor for the Vcc and GND pins. In DIP type compo-
Note 146 for Double Density. nents, the die is a small piece of silicon in the center of the
Package Effect on Ground Bounce package. The power and ground must be brought from the
corner of the package into the die near the center. This long
When scientists and engineers designed the packaging
path increases the inductance on the corner pins and ampli-
concept for standard eight bit components, they chose the
fies the ground bounce of the component. Smaller packages
worst case arrangement for the power and ground pins when
such as QSOP avoid such long distances and reduce the lead
they selected the corner pins. Fortunately, by the time 16 bit
inductance.
Double Density components were developed, the designers
were keenly aware of the ground bounce problems. Double Density Packaging
Double Density components have multiple GND and Vcc
pins distributed evenly on both sides of the package. With the
close proximity to the center of the die, these multiple paths
significantly reduce the combined lead inductances of the
GND and Vcc paths. It is the device outputs that switch and
cause current surges. Because of this, the output pins are
positioned near the ground and Vcc pins on Double Density.
The corner pins in the package are reserved for control signals
which act as inputs only. Components such as the FCT162344T
which has 32 outputs take special care to utilize all sides of the
package and avoid piling up the outputs in one area.
Load Effect on Ground Bounce
The load capacitance on a component must be dis-
charged through the output structure of the die to complete
Figure 22, Typical Octal Package Arrangement a logic transition. This current must be passed through the
lead inductance of the die and will cause additional ground
Traditional DIP logic packages contain several distinct bounce as the load increases. There is an upper limit on the
pieces. The external package holds the pins and makes saturation current of the output driver which will put a top limit
contact with the outside world. An internal leadframe brings the effect that load will have on Ground Bounce.
the contact from the external pin to a point very near the die.
A bond wire is then attached from the leadframe to the die, DESIGN CONSIDERATIONS
completing the contact from the outside pin to the silicon. There are rules which should be followed to avoid problems
Unfortunately, each of the package contact components with ground bounce in high speed circuit designs. By following
has a small amount of inductance (especially the bond wire) these rules, most false switching and line noise problems can
which accumulates to create an inductance for the package. be cured or significantly reduced.
Each package type has its own lead inductance and each pin
Choose the Right Driver
has a lead inductance depending upon where it is located on
the die. These values can be found in the SPICE models for Choose components with the highest output impedance
each component and fall in a range around 3nh. that will drive the circuit. High drive components such as
While this inductance has an influence on all pins, the pin FCT16xxxT should not be used in applications where
of greatest concern is the GND because all internal circuits FCT166xxxT components are optimum. The noise and ground
switch their currents through the GND pin, possibly simulta- bounce add nothing to the design.
neously. These combined currents cause the ground bounce BiCMOS components such as ABT16xxx have a lower
effect. output impedance than FCT16xxxT and should be reserved
The optimum packages for low ground bounce are the for applications where undershoot is not a concern. An
smallest SSOP and QSOP while large packages such as side example of an application where ABT is not appropriate is
braze and large DIPs will be noisier. Components with driving memory arrays. Memory upset and data loss can be
multiple grounds and Vcc pins such as Double Density (16 bit caused by undershoot. These would be transient errors that
logic) will give significantly better low noise performance occur only when the driving component is making an address
because of the multiple current paths reducing the inductance boundary change and undergoing Ground Bounce. An ex-
of the package. In the equation in Figure 19, if the inductance ample would be an address change from 0FFFFH to 10000H
of the package lead (L) is reduced the voltage drop across the for a Widebus, or 0FFFFH to 0FF00H for an octal component.
inductance will be reduce, meaning Ground Bounce is re- In addition, some memories and some high speed processors
duced. may be damaged by excessive undershoot.

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THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

Double Density components such as FCT16xxxT have Slow Clock Edges

better packaging and lower ground bounce than components Clock inputs should have fast edge rates on all high speed
like FCTxxxT. The multiple ground and Vcc pins of Double circuits which have ground bounce. Double clocking will
Density reduce the ground lead inductance on the die and probably occur if the input clock is allowed to slowly rise
reduce ground bounce. through the input threshold as shown in Figure 24. Since the
input threshold is a direct ratio between Die Vcc and Die GND,
Avoid Pull Up Resistors on BiCMOS
as the Die GND level fluctuates, the input threshold will also
BiCMOS components cannot hold a logic LOW near zero
fluctuate.
volts. It takes 200 to 250mV for BiCMOS to begin sinking
3
current in a logic LOW state. Adding a pull up resistor will draw
this level up beyond the 250mV level as shown in Figure 23.
2.5
This reduces the input noise immunity on the input of the next
component and may allow false switching if the next compo-
2
nent should undergo ground bounce. If BiCMOS components Input Threshold
are used, only pull down resistors should be used.

Voltage
Affected by Bounce
1.5
DIE Boundary Package Vcc
Boundary 1
1KΩ
0.5
Slow Rising Input
Signal
Vo ≈ 300mV 0

-3.5

-2.5

-1.5

-0.5

0.5

1.5

2.5

3.5
-4

-3

-2

-1

4
Time (ns)
Figure 24, Fluctuations in Input Threshold

Die GND Board GND This problem can be avoided by insuring fast rising edges
on all clocks. If clock lines need to be terminated, they should
Figure 23, BiCMOS with Pull Up Resistors be terminated with an AC termination or some other end of the
line termination rather than series termination.
CMOS components will pull a logic LOW to zero volts and
do not suffer from the same problem as BiCMOS. Therefore Bus Inverting Components
CMOS is compatible with either pull up or pull down resistors. Bus inverting components have the same problem as the
OE with Clock HIGH slow clock of Figure 24. If all bus inputs rise simultaneously,
it is highly likely that the subsequent switching of the output
This scenario combines the worst of all situations and can
from all HIGH to all LOW will raise the input threshold suffi-
easily cause false clock triggering unless the designer takes
ciently to cause the input to retoggle the threshold. This may
precautions. The setup is as follows:
cause a slight oscillation on the device output until the input
1. A clocked register (e.g. ‘374) has its outputs tied to an
level is well past the toggle point.
inactive bus.
2. The bus is pulled up to Vcc through pull up Use Bus-hold
resistors(not pull down). Pull up and pull down resistors pull the bus one direction
3. The internal state of the register is all LOW. only. For a logic LOW state, a pull up resistor will draw current
4. Clock input is stable HIGH at a marginal level (e.g. from the LOW state, raising the Vol level reducing the noise
2.4V) immunity of the logic LOW, For a logic HIGH state, a pull down
5. The output enable OE is disabled. resistor will reduce the Voh of the logic HIGH.
Disaster may happen when OE is suddenly enabled. At this In addition, a pull up resistor will pull the bus to Vcc when
point all of the outputs switch from the Vcc rail to a logic LOW the bus is HIGH. The subsequent transition to LOW then has
simultaneously causing ground bounce. The situation de- a 5V transition instead of the normal 3.2V from Voh and will
picted in Figure 9 occurs relative to the CLK input pin and the cause higher than normal Ground Bounce.
clock will transition from a HIGH to LOW to HIGH, causing the Bus-hold will pull LOWs to 0V (CMOS) and HIGHs to Voh
register to toggle. (≈3.2V for TTL). This avoids the erosion of noise immunity by
Things that can be done to reduce the likelihood of register trying to pull the opposite state through the middle voltages.
upset include Bus-hold retains the last state on the bus. Holding the last
1. Never do an OE with the clock input HIGH. state significantly reduces simultaneous switching on the bus.
2. If the CLK must be HIGH during OE, pull it very HIGH. As an example, an address bus that is pulled HIGH with pull
3. Avoid pulling the bus to Vcc with resistors. up resistors, but operating in addresses near zero would
toggle all outputs each cycle. The driver would output almost
all zeros, then release the bus which would float HIGH. The

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THE MYTH OF GROUND BOUNCE MEASUREMENTS AND COMPARISONS APPLICATION NOTE AN-147

next address would pull it to LOWs again, causing switching CONCLUSION

noise. This would continue each cycle until the bus addresses
Ground Bounce and Vcc Bounce are very real phenomena
were no longer near zero.
but the testing techniques used to measure bounce are not
Bus-hold would retain the last random state on the bus and
accurate. If a component has a BiCMOS output structure, the
not attempt to pull the bus to a uniform direction. If the next
measuring technique of observing a stable output will give a
data driven onto the bus was similar to the last data, there
reading that has no correlation to actual bounce levels.
would be almost no switching and hence almost no switching
Ground bounce is caused primarily by the inductance in the
noise.
component package lead of the ground and Vcc pins during
Avoid Ground Bounce in Memory Arrays switching. Faster edge rates and lower output impedances
Memory arrays are some of the most sensitive devices in will create higher levels of ground bounce. Advanced BiCMOS
common usage. With a high speed memory array, under- components have the fastest edge rates and lowest output
shoot on input signals is very likely to cause data loss at impedances in the industry. This creates high levels of ground
random times when crossing address boundaries. If the bounce in these components.
undershoot is excessive, some memory components may be
permanently damaged by undershoot.
When driving memories, use drivers with low undershoot
and low ground bounce. Examples of these would be a BD-
Lite FCT166244T for loads of less than 100pF. For larger
loads, an FCT162244T would maintain the required speed
with very low ground bounce. The Balanced Drive FCT162244T
is very effective over a load range from 50pF to 250pF.
Components like FCT16244T and ABT16244 should be
avoided unless the load exceeds 250pF. An effective address
driver for fannout is the FCT162344T.
Ground bounce is not the only cause of overshoot and
undershoot, especially when driving a capacitive load with an
inductive line. When undershoot is seen in these applications,
another area of investigation should be proper line termination
and matching the driver to the load. The Balanced Drive and
BD-Lite components are very effective in reducing transmis-
sion line problems.

98