Ce 419
Ce 419
Ce 419
:___________________
RK UNIVERSITY
B.TECH./SEM-III/SUPPLEMENTARY/DEC.-2019
Instructions:
1. Attempt all questions.
2. Make suitable assumptions wherever necessary.
3. Figures to the right indicate full marks.
4. Programmable calculator is not permissible.
SECTION – I
Q.1 (a) Select the most appropriate option: (Each of one mark) 06
1. Which registers can interact with the secondary storage?
a. MAR
b. PC
c. R0
d. IR
2. Match each of the high level language statements given on the left
hand side with the most natural addressing mode from those listed
on the right hand side.
Q.2 (a) Draw flowchart for instruction cycle and explain it. 06
(b) State the differences between RISC and CISC. 05
(c) How addressing mode is significant for referring memory? List 05
addressing modes and explain any four of them.
OR
Q.2 (a) What is register stack? Explain push and pop micro-operations. 06
(b) Draw the block diagram of Control unit of basic computer and 05
explain it.
(c) Create assembly program to add 10 numbers from memory. 05
Q.3 (a) List out and explain all the resisters of Common Bus System. 06
(b) Convert decimal number into IEEE 754 standard floating number 06
using single precision and double precision format.
(185.125)10
(c) Describe microprogrammed control organization in detail. 06
OR
Q.3 (a) What is an Assembler? With clear flowchart of second pass, explain 06
its working.
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(b) Write a program to evaluate the following arithmetic statement 06
X= A*B + C*D
(i) using a general register computer with three-address instructions,
(ii) using an accumulator type computer with one-address
instructions, (iii) using a stack organized computer with zero-address
operation instructions.
(c) Explain Microprogram Sequencer with diagram. 06
SECTION – II
Q.4 (a) Select the most appropriate option: (Each of one mark) 06
1. To reduce the memory access time we generally make use of _____
a. Heaps
b. Higher capacity RAM’s
c. SDRAM’s
d. Cache’s
2. The decoded instruction is stored in ______
a. IR
b. PC
c. Registers
d. MDR
3. The DMA controller has _______ registers
a. 4
b. 2
c. 3
d. 1
4. The CISC stands for ___________
a. Computer Instruction Set Compliment
b. Complete Instruction Set Compliment
c. Computer Indexed Set Components
d. Complex Instruction set computer
5. The VLIW architecture follows _____ approach to achieve
parallelism.
a. MISD
b. SISD
c. SIMD
d. MIMD
6. When dealing with multiple devices interrupts, which mechanism is
easy to implement?
a. Polling method
b. Vectored interrupts
c. Interrupt nesting
d. None of the mentioned
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(b) Answer following questions: (Each of two mark) 10
1. Differentiate I/O and Memory Bus.
2. Compare SIMD and MIMD.
3. What is a bootstrap loader?
4. Why subtraction is generally carried out by 2’s complement?
5. What characteristic of RAM memory makes it not suitable for
permanent storage?
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