AN SY8063 Silergy
AN SY8063 Silergy
AN SY8063 Silergy
Figure 1
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Pinout (top view)
Top Mark: ECxyz (device code: EC, x=year code, y=week code, z= lot number code)
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Electrical Characteristics
(VIN = 5V, VOUT = 2.5V, L = 2.2uH, COUT = 10uF, TA = 25°C, IMAX = 1A unless otherwise specified)
Note 1: Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may remain possibility to affect device reliability.
Note 2: θ JA is measured in the natural convection at TA = 25°C on a low effective single layer thermal conductivity
test board of JEDEC 51-3 thermal measurement standard. Paddle of DFN3X3-10 packages is the case position for θ
JC measurement.Test condition: Device mounted on 2” x 2” FR-4 substrate PCB, 2oz copper, with minimum
recommended pad on top layer and thermal vias to bottom layer ground plane.
Note 3: The device is not guaranteed to function outside its operating conditions.
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Function Block
IN
EN
1.5V
PWM Control LX
FB & Protect Logic
0.6V
Internal SST
GND
PG Thermal
Protection
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Efficiency (%)
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VIN 2V/div
VO (1V/div)
Time (400us/div)
VIN 2V/div
VIN 2V/div
VO 1V/div
VO 1V/div
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Tc(oC)
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desirable to choose an inductor with DCR<20mohm Layout Design:
to achieve a good overall efficiency. The layout design of SY8063 regulator is relatively
simple. For the best efficiency and minimum noise
problems, we should place the following components
Enable Operation close to the IC: CIN, L, R1 and R2.
Pulling the EN pin low (<0.4V) will shut down the
device. During shutmode, the SY8036 shutdown 1) It is desirable to maximize the PCB copper area
current drops to lower than 0.1uA. Driving the EN pin connecting to GND pin to achieve the best thermal and
high (>1.5V) will turn on the IC again. noise performance. The center pad of SY8063 is used as
the GND, so it is desirable to make a ground plane layer
Soft-start on a multi-layer board. Resonable vias are suggested to
The SY8063 has a built-in soft-start to control the rise be placed underneath the ground pad to enhance the
rate of the output voltage and limit the input current soldering quality and thermal performance.
surge during IC start-up. The typical soft-start time is
1ms. 2) CIN must be close to Pins IN and GND. The loop
area formed by CIN and GND must be minimized.
PG (Power Good):
The power good is an open-drain output. Connect an 3) The PCB copper area associated with LX pin must be
above 100k pull up resistor to VIN to obtain an output minimized to avoid the potential noise problem.
voltage. The power good will output high immediately
after the output voltage within 90% of normal putput 4) The components R1 and R2, and the trace
voltage. connecting to the FB pin must NOT be adjacent to the
LX net on the PCB layout to avoid the noise problem.
Load Transient Considerations:
The SY8063 regulator IC integrates the compensation 5) If the system chip interfacing with the EN pin has a
components to achieve good stability and fast transient high impedance state at shutdown mode and the IN pin is
responses. In some applications, adding a 22pF~220pF connected directly to a power source such as a LiIon
ceramic capacitor in parallel with R1 may further speed battery, it is desirable to add a pull down 1Mohm resistor
up the load transient responses and is thus recommended between the EN and GND pins to prevent the noise from
for applications with large load transient step falsely turning on the regulator at shutdown mode.
requirements.
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Design Specifications
Input Voltage (V) Output Current (A) Output Voltage (V) Test conditions
2.7~5.5V 0~3.5A 1.8V K close
EVB Schematic
1. Connect the output load to Vout and GND output connectors. Preset the load current to between 0A and 3.5A.
2. Preset the input supply to a voltage between 2.7V and 5.5V. Turn the supply off. Connect the input supply to
VIN and GND input connectors.
3. Turn on the input supply and measure the output voltage.
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PCB Layout
(a) (b)
Figure 4. PCB Layout Plots: (a) top layer, (b) bottom layer
BOM List
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DFN3X3-10 Package outline
Side View
Detail A
Pin1 identifier: two options
Bottom View
Notes: All dimensions are in millimeters and exclude mold flash & metal burr.
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Taping & Reel Specification
11.7/12.3
Feeding direction
Reel
Size
Package Tape width Pocket Reel size Reel Trailer Leader length Qty per
types (mm) pitch(mm) (Inch) width(mm) length(mm) (mm) reel
3. Others: NA
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