Ucc27324 (Mosfet Gate Driver)

UCC27323, UCC27324, UCC27325, UCC37323, UCC37324, UCC37325
SLUS492K – JUNE 2001 – REVISED NOVEMBER 2023
UCCx732x Dual 4-A Peak High-Speed Low-Side Power-MOSFET Drivers
1 Features 3 Description
• Bi-CMOS Output Architecture The UCC2732x and UCC3732x family of high-speed
• ±4 A Drive Current at the Miller Plateau Region dual-MOSFET Drivers deliver 4-A source and 4-A sink
• Constant-Current Even at Low Supply Voltages peak current to effectively drive MOSFETs where it is
• Outputs Paralleled for Higher Drive Current needed most at the Miller Plateau Region. A unique
• Available in MSOP- PowerPAD™ Package BiPolar and MOSFET hybrid output stage in parallel
• TTL/CMOS Inputs Independent of Supply Voltage also allows efficient current sourcing and sinking at
• Industry-Standard Pin-Out low supply voltages. Three standard logic options are
offered — dual-inverting, dual-noninverting, and one-
2 Applications inverting and one-noninverting driver. Input thresholds
• Switch-Mode Power Supplies are based on TTL and CMOS and independent of
• DC-DC Converters supply voltage and feature wide input hysteresis
• Solar Inverters, Motor Control, UPS offering excellent noise immunity. The UCC2732x
and UCC3732x family is available in the standard
SOIC-8 (D) as well as the thermally enhanced
-8pin PowerPAD MSOP package (DGN), drastically
lowering thermal resistance to improve long term
reliability.
Device Information
DEVICE(1) KEY SPECS PACKAGE
-40C <= Temp <= SOIC (8): 4.90 mm ×
125C 3.91 mm
4.5V <= VDD<= 15V
UCCx732x 20ns/15ns - Rise/Fall MSOP-PowerPAD
times @ 1.8nF load (8): 3.00 mm × 3.00
35ns/25ns Rise/Fall mm
Prop Delay
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
UCCx732x
1 N/C N/C 8
INA 2 INA OUTA 7
3 GND VDD 6
INB 4 INB OUTB 5
0.1 μF
1.0 μF
Copyright © 2016, Texas Instruments Incorporated
Simplified Application Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLUS492K – JUNE 2001 – REVISED NOVEMBER 2023 www.ti.com
Table of Contents
1 Features............................................................................1 8.1 Application Information..............................................11
2 Applications..................................................................... 1 8.2 Typical Application.................................................... 12
3 Description.......................................................................1 9 Power Supply Recommendations................................16
4 Device Comparison Table...............................................3 10 Layout...........................................................................17
5 Pin Configuration and Functions...................................4 10.1 Layout Guidelines................................................... 17
6 Specifications.................................................................. 5 10.2 Layout Example...................................................... 17
6.1 Absolute Maximum Ratings........................................ 5 10.3 Thermal Considerations..........................................18
6.2 ESD Ratings............................................................... 5 11 Device and Documentation Support..........................19
6.3 Recommended Operating Conditions.........................5 11.1 Device Support........................................................19
6.4 Thermal Information....................................................5 11.2 Documentation Support.......................................... 19
6.5 Electrical Characteristics.............................................6 11.3 Receiving Notification of Documentation Updates.. 19
6.6 Switching Characteristics............................................6 11.4 Support Resources................................................. 19
6.7 Typical Characteristics................................................ 8 11.5 Trademarks............................................................. 19
7 Detailed Description........................................................9 11.6 Electrostatic Discharge Caution.............................. 19
7.1 Overview..................................................................... 9 11.7 Glossary.................................................................. 19
7.2 Functional Block Diagram........................................... 9 12 Revision History.......................................................... 20
7.3 Feature Description.....................................................9 13 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes..........................................10 Information.................................................................... 20
8 Application and Implementation.................................. 11
2 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated
Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

www.ti.com SLUS492K – JUNE 2001 – REVISED NOVEMBER 2023
4 Device Comparison Table

TEMPERATURE PACKAGED DEVICES(1)
OUTPUT CONFIGURATION RANGE MSOP-8 PowerPAD (DGN)
TA = TJ SOIC-8 (D) (2) PDIP-8 (P)
–40°C to +125°C UCC27323D UCC27323DGN UCC27323P

Dual inverting
0°C to +70°C UCC37323D UCC37323DGN UCC37323P
Dual noninverting
One inverting, one noninverting
(1) D (SOIC-8) and DGN (PowerPAD-MSOP) packages are available taped and reeled. Add R suffix to device type (for example
UCC27323DR, UCC27324DGNR) to order quantities of 2,500 devices per reel for D or 1,000 devices per reel for DGN package.
(2) The PowerPAD is not directly connected to any leads of the package. However, the PowerPAD is electrically and thermally connected
to the substrate which is the ground of the device.
Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 3

5 Pin Configuration and Functions
Figure 5-1. D, DGN Package 8-Pin SOIC, MSOP With PowerPAD Top View
Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME NO.
Common ground: This ground should be connected very closely to the source of the power MOSFET
GND 3 —
which the driver is driving.
Input A: Input signal of the A driver which has logic compatible threshold and hysteresis. If not used,
INA 2 I
this input must be tied to either VDD or GND; it must not be left floating.
Input B: Input signal of the A driver which has logic compatible threshold and hysteresis. If not used,
INB 4 I
this input must be tied to either VDD or GND; it must not be left floating.
N/C 1 — No Internal Connection
N/C 8 — No Internal Connection
Driver output A: The output stage is capable of providing 4-A drive current to the gate of a power
OUTA 7 O
MOSFET.
Driver output B: The output stage is capable of providing 4-A drive current to the gate of a power
OUTB 5 O
MOSFET.
VDD 6 I Supply: Supply voltage and the power input connection for this device.

6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
Analog input voltage (INA, INB) –0.3 to VDD + 0.3 V not to exceed 16 V
Output body diode DC current (OUTA, OUTB) 0.2
IOUT_DC DC 0.2 A
Output current (OUTA, OUTB)
IOUT_PULSED Pulsed (0.5 µs) 4.5
Output voltage (OUTA, OUTB) 16 V
VDD Supply voltage –0.3 16 V
TJ Junction operating temperature –55 150
°C
Tstg Storage temperature –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
1000
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage 4.5 15 V
Input voltage 0 15 V
UCC2732x –40 125 °C
Operating junction temperature
UCC3732x 0 70 °C
6.4 Thermal Information

UCCx732x
DGN
D P
THERMAL METRIC(1) (MSOP With UNIT
(SOIC) (PDIP)
PowerPAD)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 107.3 56.6 55.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.2 52.8 45.3 °C/W
RθJB Junction-to-board thermal resistance 47.3 32.6 32.6 °C/W
ψJT Junction-to-top characterization parameter 10.2 1.8 23 °C/W
ψJB Junction-to-board characterization parameter 46.8 32.3 32.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 5.9 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

VDD = 4.5 to 15 V, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT (INA, INB)
VIN_H Logic 1 input threshold 1.6 2.2 2.5
V
VIN_L Logic 0 input threshold 0.8 1.2 1.5
Input current 0 V ← VIN ← VDD –10 10 µA
OUTPUT (OUTA, OUTB)
Output current VDD = 14 V(1) 4 A
ROH Output resistance high IOUT = –10 mA, (2) 0.6 1.5
Ω
ROL Output resistance low IOUT = 10 mA, (2) 0.4 1
OVERALL
INA = 0 V, INB = 0 V 300 450
INA = 0 V, INB = HIGH 300 450
UCCx7323
INA = HIGH, INB = 0 V 300 450
INA = HIGH, INB = HIGH 300 450
INA = 0 V, INB = 0 V 2 50
Static Operating INA = 0 V, INB = HIGH 300 450

IDD UCCx7324 µA
Current INA = HIGH, INB = 0 V 300 450
INA = 0 V, INB = 0 V 150 300
INA = 0 V, INB = HIGH 450 600
UCCx7325
INA = HIGH, INB = 0 V 150 300
(1) Parameter not tested in production

(2) Output pullup resistance is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.
6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TR Rise time (OUTA, OUTB) CLOAD = 1.8 nF, see Figure 6-1 20 40
TF Fall time (OUTA, OUTB) CLOAD = 1.8 nF, see Figure 6-1 15 40
ns
TD1 Delay, IN rising (IN to OUT) CLOAD = 1.8 nF, see Figure 6-1 25 40
TD2 Delay, IN falling (IN to OUT) CLOAD = 1.8 nF, see Figure 6-1 35 35

(a) (b)
+5V
90% 90%
INPUT INPUT
10% 10%
0V
t D1 tF t D2 tR tF
tR
16V
90% 90% 90%
t D1
OUTPUT OUTPUT t D2
10% 10%
0V
Figure 6-1. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver

6.7 Typical Characteristics

30 38
28 36
10 nF
26 10 nF 34
tD1 - Delay Time - ns
24 32
tD2 - Delay Time - ns

4.7 nF
22 4.7 nF 30
20 28
18 26 2.2 nF
2.2 nF
16 24 470 pF
1 nF
470 pF 22
14
1 nF
12 20
4 6 8 10 12 14 16 4 6 8 10 12 14 16
VDD - Supply Voltage - V VDD - Supply Voltage - V
Figure 6-2. Delay Time (tD1) vs Supply Voltage Figure 6-3. Delay Time (tD2) vs Supply Voltage
Figure 6-4. Input Threshold vs Supply Voltage

7 Detailed Description
7.1 Overview
The UCC2732x and UCC3732x family of high-speed dual MOSFET drivers can deliver large peak currents into
capacitive loads. Three standard logic options are offered – dual-inverting, dual-noninverting and one-inverting
and one-noninverting driver. Using a design that inherently minimizes shoot-through current, these drivers
deliver 4A of current where it is needed most at the Miller plateau region during the MOSFET switching
transition. A unique Bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing
and sinking at low supply voltages.
7.2 Functional Block Diagram
INVERTING
N/C 1 8 N/C
7 OUTA
INA 2 NON-INVERTING
GND 3
INVERTING 6 VDD
5 OUTB
INB 4 NON-INVERTING
7.3 Feature Description

7.3.1 Input Stage
The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltage; yet it is equally compatible
with 0 V to VDD signals.
The inputs of UCC2732x and UCC3732x family of drivers are designed to withstand 500-mA reverse current
without either damage to the IC for logic upset. The input stage of each driver must be driven by a signal with
a short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals
are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the
drivers function as a digital gate, and are not intended for applications where a slow-changing input voltage is
used to generate a switching output when the logic threshold of the input section is reached. While this may not
be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.
Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal
at the output. If limited rise or fall times to the power device is desired, an external resistance can be added
between the output of the driver and the load device, which is generally a power MOSFET gate. The external
resistor may also help remove power dissipation from the device package, as discussed in (see Section 10.3).
Importantly, input signal of the two channels, INA and INB, which has logic compatible threshold and hysteresis.
If not used, INA and INB must be tied to either VDD or GND; it must not be left floating.
7.3.2 Output Stage
Inverting outputs of the UCCx7323 and OUTA of the UCCx7325 are intended to drive external P-channel
MOSFETs. Noninverting outputs of the UCCx7324 and OUTB of the UCCx7325 are intended to drive external
N-Channel MOSFETs.
Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND.
The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel.

The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output
resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the
saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot
and undershoot due to the body diode of the external MOSFET.
This means that in many cases, external-Schottky-clamp diodes are not required. The UCCx732x family delivers
4 A of gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region
– providing improved efficiency gains. A unique Bipolar and MOSFET hybrid output stage in parallel also allows
efficient current sourcing at low supply voltages.
7.4 Device Functional Modes
With VDD power supply in the range of 4.5 V to 15 V, the output stage is dependent on the states of the HI and
LI pins. Table 7-1 shows the UCCx732x truth table.
Table 7-1. Input and Output Table
INPUTS (VIN_L, VIN_H) UCC37323x UCC37324x UCC37325x
INA INB OUTA OUTB OUTA OUTB OUTA OUTB
L L H H L L H L
L H H L L H H H
H L L H H L L L
H H L L H H L H
Importantly, if INA and INB are not used, they must be tied to either VDD or GND; it must not be left floating.

8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

High-frequency power supplies often require high-speed, high-current drivers such as the UCCx732x family. A
leading application is the needed to provide a high-power buffer stage between the PWM output of the control IC
and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is used to
drive the power-device gates through a drive transformer. Synchronous rectification supplies are also needed to
simultaneously drive multiple devices which presents an extremely large load to the control circuitry.
Driver ICs are used when having the primary PWM regulator IC directly drive the switching devices for one or
more reasons is not feasible. The PWMIC does not have the brute drive capability required for the intended
switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire
to minimize the effect of high-frequency switching noise by placing the high current driver physically close to the
load. Also, newer ICs that target the highest operating frequencies do not incorporate onboard gate drivers at
all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCCx732x.
Finally, the control IC is under thermal stress due to power dissipation, and an external driver helps by moving
the heat from the controller to an external package.

8.2 Typical Application

UCCx732x
1 N/C N/C 8
INA 2 INA OUTA 7
3 GND VDD 6
INB 4 INB OUTB 5
0.1 μF
1.0 μF
Figure 8-1. UCCx732x Driving Two Independent MOSFETs
8.2.1 Design Requirements

To select proper device from UCCx732x family, TI recommends first checking the appropriate logic for the
outputs. UCCx7323 has dual inverting outputs; UCCx7324 has dual noninverting outputs; UCCx7325 have
inverting channel A and noninverting channel B. Moreover, some design considerations must be evaluated first
in order to make the most appropriate selection. Among these considerations are VDD, drive current, and power
dissipation.
8.2.2 Detailed Design Procedure
8.2.2.1 Source/Sink Capabilities During Miller Plateau
Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable
operation. The UCCx732x drivers have been optimized to provide maximum drive to a power MOSFET during
the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging
between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate
capacitance with current supplied or removed by the driver device [1].
Two circuits are used to test the current capabilities of the UCCx732x driver. In each case external circuitry
is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250
ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a
transient period where the current peaked up and then settled down to a steady-state value. The noted current
measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. [1]
The first circuit in Figure 8-2 is used to verify the current sink capability when the output of the driver is clamped
around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCCx7323 is found to
sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V.

UCCx7323
VDD
1 N/C N/C 8
DSCHOTTKY 10 Ω
INA OUTA
2 7
VADJ
3 GND VDD 6
100 µF 5.5V
1µ F CER
AL EL
Signal INB OUTB
4 5
Generator VSNS
producing
250 ns wide
RSNS
pulse 0.1 Ω
1 µF CER
100 µF
AL EL
Figure 8-2. Current Sink Capability Test
The circuit shown in Figure 8-3 is used to test the current source capability with the output clamped to around 5
V with a string of Zener diodes. The UCCx7323 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12
V.
UCCx7323
VDD
1 N/C N/C 8
DSCHOTTKY 10 Ω
INA OUTA
2 7
3 GND VDD 6
100 µF 4.5V
1 µF CER
AL EL
INB OUTB
Signal 4 5
Generator VSNS
producing
250 ns wide
pulse RSNS
0.1 Ω
1 µF CER
100 µF
AL EL
Copywright © 2016, Texas Instruments Incorporated
Figure 8-3. Current Source Capability Test
8.2.2.2 Parallel Outputs

The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together as close
to the IC as possible, and the OUTA/OUTB outputs ties together if the external gate drive resistor is not used. In
some cases where the external gate drive resistor is used, Ti recommends that the resistor can be equally split
in OUTA and OUTB respectively to reduce the parasitic inductance induce unbalance between two channels, as
show in Figure 8-4.

UCCx7323/4
1 N/C N/C 8
RG
IN 2 INA OUTA 7
3 GND VDD 6
RG
4 INB OUTB 5
0.1 F
1.0 F
Figure 8-4. Parallel Operation of UCCx7323 and UCCx7324
Important consideration about paralleling two channels for UCCx7323/4 include: 1) INA and INB should be
shorted in PCB layout as close to the device as possible, as well as for OUTA and OUTB, in which condition
PCB layout parasitic mismatching between two channels could be minimized. 2) INA/B input slope signal should
be fast enough to avoid mismatched VIN_H/VIN_L, td1/td2 between channel-A and channel-B. TI recommends
having input signal slope faster than 20 V/us.
8.2.2.3 VDD
Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB
current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated using Equation 1.
IOUT = Qg × f (1)
where
• f is frequency
For the best high-speed circuit performance, two VDD bypass capacitors are recommended to prevent noise
problems. The use of surface mount components is highly recommended. A 0.1-µF ceramic capacitor should be
located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1 µF and above) with
relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel
combination of capacitors should present a low impedance characteristic for the expected current levels in the
driver application.
8.2.2.4 Driver Current and Power Requirements
The UCCx732x family of drivers is capable of delivering 4 A of current to a MOSFET gate for a period of tens
of nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the
driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the
power device. A MOSFET is used in this discussion because it is the most common type of switching device
used in high-frequency power conversion equipment.
Reference [1] and reference [2] discuss the current required to drive a power MOSFET and other capacitive-
input switching devices. Reference [2] includes information on the previous generation of bipolar IC gate drivers.

When a driver IC is tested with a discrete, capacitive load, it is a fairly simple matter to calculate the power that is
required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor
is given by Equation 2.
E = ½CV2 (2)
where
• C is the load capacitor
• V is the bias voltage feeding the driver
There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a
power loss given by Equation 3.
P = CV2 × f (3)
where
• f is the switching frequency
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the
driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor
is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the
conditions of the previous gate drive waveform should help clarify this.
With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as Equation 4.
P = 10 nF × (12 V)2 × (300 kHz) = 0.432 W (4)
With a 12-V supply, this equates to a current of (see Equation 5):
I = P/V = 0.432 W /12 V = 36 mA (5)
The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the
IDD current that is due to the IC internal consumption should be considered. With no load the IC current draw
is 0.0027 A. Under this condition the output rise and fall times are faster than with a load. This could lead
to an almost insignificant, yet measurable current due to cross-conduction in the output stages of the driver.
However, these small current differences are buried in the high frequency switching spikes, and are beyond the
measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to that
expected.
The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining
the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus
the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers
provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under
specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when
charging a capacitor. This is done by using the equivalence Qg = Ceff × V to provide Equation 6 for power:
P = C × V2 × f = V × Qg × f (6)
Equation 6 allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a
specific bias voltage and a specific switching frequency.
8.2.3 Application Curves
Figure 8-5 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF
load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform.
Note the linear rise and fall edges of the switching waveforms which is due to the constant output current

characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate
drivers.
Sink and source currents of the driver are dependent upon the VDD value and the output capacitive load. The
larger the VDD value, the higher the current capability; also, the larger the capacitive load, the higher the current
sink and source capability.
Trace resistance and inductance, including wires and cables for testing, slows down the rise and fall times of the
outputs; thus reducing the current capabilities of the driver.
To achieve higher current results, reduce resistance and inductance on the board as much as possible and
increase the capacitive load value in order to swamp out the effect of inductance values.
CL = 10 nF, CL = 10 nF, VDD = 12 V
Figure 8-5. Rising and Falling Time of UCCx732x
9 Power Supply Recommendations

The recommended bias supply voltage range for UCCx732x is from 4.5 V to 15 V. The upper end of this range is
driven by the 16 V absolute maximum voltage rating of the VDD. TI recommends keeping proper margin to allow
for transient voltage spikes.
A local bypass capacitor must be placed between the VDD and GND pins. And this capacitor must be placed as
close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. TI recommends
using 2 capacitors across VDD and GND: a 100-nF ceramic surface-mount capacitor for high frequency filtering
placed very close to VDD and GND pin, and another surface-mount capacitor, 220 nF to
10 µF, for IC bias requirements.

10 Layout
10.1 Layout Guidelines
Optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations
during circuit board layout. The following points are emphasized:
1) Low ESR/ESL capacitors must be connected close to the IC between VDD and GND pins to support high
peak currents drawn from VDD during the turn-on of the external MOSFETs.
2) Grounding considerations:
• The first priority in designing grounding connections is to confine the high peak currents that charge and
discharge the MOSFET gates to a minimal physical area. This will decrease the loop inductance and
minimize noise issues on the gate terminals of the MOSFETs. The gate driver must be placed as close
as possible to the MOSFETs.
• Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND
of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM
controller at one, single point. The connected paths must be as short as possible to reduce inductance and
be as wide as possible to reduce resistance.
• Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground
plane must be connected to the star-point with one single trace to establish the ground potential. In addition
to noise shielding, the ground plane can help in power dissipation as well.
3) In noisy environments, tying inputs of an unused channel of the UCC2742x device to VDD or GND using short
traces in order to ensure that the output is enabled and to prevent noise from causing malfunction in the output
may be necessary.
4) Separate power traces and signal traces, such as output and input signals.
10.2 Layout Example
Ground plane
UCCx732x
(Bottom Layer)
Ext. Gate Resistance
(Ch-A)
INA OUTA
To Ch-A
GND VDD Load
INB OUTB
To Ch-B
Load
Bypassing Cap, 0.1 F Ext. Gate Resistance
(Ch-B)
Bypassing Cap, 1.0 F
Figure 10-1. Recommended PCB Layout for UCCx732x

10.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the IC package. In order for a power driver to be useful over a particular temperature range,
the package must allow for the efficient removal of the heat produced while keeping the junction temperature
within rated limits. The UCCx732x family of drivers is available in three different packages to cover a range of
application requirements.
The MSOP PowerPAD-8 (DGN) package significantly relieves this concern by offering an effective means of
removing the heat from the semiconductor junction. As illustrated in reference [3], the PowerPAD packages offer
a lead-frame die pad that is exposed at the base of the package. This pad is soldered to the copper on the PC
board directly underneath the IC package, reducing the θJC down to 4.7°C/W. Data is presented in reference
[3] to show that the power dissipation can be quadrupled in the PowerPAD configuration when compared to
the standard packages. The PC board must be designed with thermal lands and thermal vias to complete the
heat removal subsystem, as summarized in reference [4]. This design allows a significant improvement in heat
sinking over that which is available in the D or P packages, and is shown to more than double the power
capability of the D and P packages.
Note
The PowerPAD is not directly connected to any leads of the package. However, the PowerPad is
electrically and thermally connected to the substrate which is the ground of the device.

11 Device and Documentation Support

11.1 Device Support
11.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
See the following for related documentation:
1. Power Supply Seminar SEM-1400 Topic 2, Design And Application Guide For High Speed MOSFET Gate
Drive Circuits (SLUP133)
2. Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits (SLUA105)
3. PowerPad Thermally Enhanced Package (SLMA002)
4. PowerPAD Made Easy (SLMA004)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

12 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (September 2018) to Revision K (November 2023) Page

• Changed ESD HBM value from 4000 V to 2000 V in ESD Ratings................................................................... 5
• Changed input threshold voltage values, deleted VOH output high level and VOL output low level, changed
output resistance high and output resistance low values in Electrical Characteristics....................................... 6
• Changed Figure 6-4 ...........................................................................................................................................8
Changes from Revision I (July 2016) to Revision J (September 2018) Page

• Changed NC description from "No connection: must be grounded” to “No Internal Connection"...................... 4
Changes from Revision H (May 2013) to Revision I (July 2016) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................. 1
• Deleted Power Dissipation rows from Absolute Maximum Ratings ...................................................................5
Changes from Revision G (March 2010) to Revision H (May 2013) Page

• Changed DSCHOTTKY diode direction and voltage of zener diode from 5.5 to 4.5 V in Figure 8-3 ................... 12
• Added three paragraphs after first paragraph of Operational Waveforms and Circuit Layout section before
Figure 8-5 ........................................................................................................................................................ 15
13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 27-Sep-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
UCC27323D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 27323

UCC27323DGN OBSOLETE HVSSOP DGN 8 TBD Call TI Call TI -40 to 125 27323
UCC27323DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 125 27323 Samples
UCC27323DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27323 Samples
UCC27323P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 UCC27323P Samples

UCC27324DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27324 Samples
UCC27324DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 27324 Samples
UCC27324PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 UCC27324P Samples

UCC27325PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 UCC27325P Samples
UCC37323D OBSOLETE SOIC D 8 TBD Call TI Call TI 0 to 70 37323

UCC37323DGN OBSOLETE HVSSOP DGN 8 TBD Call TI Call TI 0 to 70 37323
UCC37323DGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM 0 to 70 37323 Samples
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
UCC37323DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 37323 Samples
UCC37323P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC37323P Samples

UCC37324PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 UCC37324P Samples

UCC37325DGNRG4 ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 37325 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 2
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UCC27324 :
• Automotive : UCC27324-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC27323DGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
UCC27323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC27325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC37323DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37324DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
UCC37325DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC27323DGNR HVSSOP DGN 8 2500 364.0 364.0 27.0
UCC27323DR SOIC D 8 2500 353.0 353.0 32.0
UCC27323DR SOIC D 8 2500 353.0 353.0 32.0
UCC27324DR SOIC D 8 2500 353.0 353.0 32.0
UCC27324DR SOIC D 8 2500 353.0 353.0 32.0
UCC27324DR SOIC D 8 2500 356.0 356.0 35.0
UCC27325DR SOIC D 8 2500 340.5 338.1 20.6
UCC27325DR SOIC D 8 2500 353.0 353.0 32.0
UCC37323DR SOIC D 8 2500 353.0 353.0 32.0
UCC37323DR SOIC D 8 2500 353.0 353.0 32.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC37324DR SOIC D 8 2500 353.0 353.0 32.0
UCC37324DR SOIC D 8 2500 353.0 353.0 32.0
UCC37325DR SOIC D 8 2500 353.0 353.0 32.0
UCC37325DR SOIC D 8 2500 340.5 338.1 20.6
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
UCC27323P P PDIP 8 50 506 13.97 11230 4.32
UCC27324P P PDIP 8 50 506 13.97 11230 4.32
UCC27324PE4 P PDIP 8 50 506 13.97 11230 4.32
UCC27325P P PDIP 8 50 506 13.97 11230 4.32
UCC27325PE4 P PDIP 8 50 506 13.97 11230 4.32
UCC37323P P PDIP 8 50 506 13.97 11230 4.32
UCC37324P P PDIP 8 50 506 13.97 11230 4.32
UCC37324PE4 P PDIP 8 50 506 13.97 11230 4.32
UCC37325P P PDIP 8 50 506 13.97 11230 4.32
GENERIC PACKAGE VIEW
DGN 8 PowerPAD VSSOP - 1.1 mm max height
3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225482/A
www.ti.com
PACKAGE OUTLINE
TM
DGN0008D SCALE 4.000
PowerPAD VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE
C
5.05
A TYP
4.75 0.1 C
PIN 1 INDEX AREA SEATING
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
1.89
1.63 9 1.1 MAX
8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
1.57
TYPICAL
1.28
4225481/A 11/2019
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.
www.ti.com
EXAMPLE BOARD LAYOUT
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
(2)
NOTE 9
METAL COVERED
BY SOLDER MASK (1.57)
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(3)
9 SYMM NOTE 9
(1.89)
6X (0.65) (1.22)
5
4
( 0.2) TYP
VIA (0.55) SEE DETAILS
(4.4)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X
SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING
EXPOSED METAL EXPOSED METAL
0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND
NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4225481/A 11/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.
www.ti.com
EXAMPLE STENCIL DESIGN
TM
DGN0008D PowerPAD VSSOP - 1.1 mm max height
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(1.89)
SYMM BASED ON
0.125 THICK
STENCIL
6X (0.65)
4 5
METAL COVERED SEE TABLE FOR

BY SOLDER MASK DIFFERENT OPENINGS
(4.4) FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE

EXPOSED PAD 9:
100% PRINTED SOLDER COVERAGE BY AREA
SCALE: 15X
STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.76 X 2.11
0.125 1.57 X 1.89 (SHOWN)
0.15 1.43 X 1.73
0.175 1.33 X 1.60
4225481/A 11/2019
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
TM
DGN0008G SCALE 4.000
C
5.05
A TYP
4.75 0.1 C
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
EXPOSED THERMAL PAD
4
5
0.25
GAGE PLANE
2.15
1.95 9 1.1 MAX
8
1 0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
1.846
TYPICAL
1.646
4225480/B 12/2022
NOTES:
per ASME Y14.5M.
www.ti.com
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
(2)
NOTE 9
METAL COVERED
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(3)
9 SYMM NOTE 9
(1.89)
6X (0.65) (1.22)
5
4
( 0.2) TYP
(4.4)

EXPOSED METAL SHOWN
SCALE: 15X

METAL
0.05 MAX 0.05 MIN


DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4225480/B 12/2022
NOTES: (continued)

www.ti.com
TM
DGN0008G PowerPAD VSSOP - 1.1 mm max height
(1.57)
BASED ON
0.125 THICK
STENCIL
SYMM
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(1.89)
SYMM BASED ON
0.125 THICK
STENCIL
6X (0.65)
4 5

THICKNESSES

EXPOSED PAD 9:
SCALE: 15X

THICKNESS OPENING
0.1 1.76 X 2.11
0.125 1.57 X 1.89 (SHOWN)
0.15 1.43 X 1.73
0.175 1.33 X 1.60
4225480/B 12/2022
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
TM
DGN0008H SCALE 4.000
C
5.05
A TYP
4.75 0.1 C
PLANE
6X 0.65
8
1
2X
3.1
1.95
2.9
NOTE 3
4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4
0.23
0.13
SEE DETAIL A
(0.48) MAX EXPOSED THERMAL PAD

(0.205) MAX NOTE 6
NOTE 6
4
5
0.25
GAGE PLANE
1.8
1.1 9 1.1 MAX
1 8
0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20
1.71
TYPICAL
1.01
4229130/B 05/2024
NOTES:
per ASME Y14.5M.
6. Features may differ or may not be present.
www.ti.com
TM
DGN0008H PowerPAD VSSOP - 1.1 mm max height
(2)
NOTE 10
METAL COVERED
SYMM SOLDER MASK
DEFINED PAD
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(3)
9 SYMM NOTE 10
(1.8)
6X (0.65) (1.22)
5
4
( 0.2) TYP
(4.4)

EXPOSED METAL SHOWN
SCALE: 15X

METAL
0.05 MAX 0.05 MIN


DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000
4229130/B 05/2024
NOTES: (continued)

www.ti.com
TM
DGN0008H PowerPAD VSSOP - 1.1 mm max height
(1.71)
BASED ON
0.125 THICK
STENCIL
SYMM
8X (1.4) (R0.05) TYP
8
8X (0.45) 1
(1.8)
SYMM
BASED ON
0.125 THICK
STENCIL
6X (0.65)
4 5

THICKNESSES

EXPOSED PAD 9:
SCALE: 15X

THICKNESS OPENING
0.1 1.91 X 2.01
0.125 1.71 X 1.80 (SHOWN)
0.15 1.56 X 1.64
0.175 1.45 X 1.52
4229130/B 05/2024
NOTES: (continued)
www.ti.com
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)

www.ti.com
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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Ucc27324 (Mosfet Gate Driver)

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UCC27323, UCC27324, UCC27325, UCC37323, UCC37324, UCC37325

SLUS492K – JUNE 2001 – REVISED NOVEMBER 2023

UCCx732x Dual 4-A Peak High-Speed Low-Side Power-MOSFET Drivers

(1) For all available packages, see the orderable addendum at

INA 2 INA OUTA 7

INB 4 INB OUTB 5

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Simplified Application Diagram

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

4 Device Comparison Table

–40°C to +125°C UCC27323D UCC27323DGN UCC27323P

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5 Pin Configuration and Functions

Table 5-1. Pin Functions

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

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6.5 Electrical Characteristics

Static Operating INA = 0 V, INB = HIGH 300 450

(1) Parameter not tested in production

6.6 Switching Characteristics

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

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6.7 Typical Characteristics

tD2 - Delay Time - ns

Figure 6-4. Input Threshold vs Supply Voltage

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

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7.3 Feature Description

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

8 Application and Implementation

8.1 Application Information

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8.2 Typical Application

INA 2 INA OUTA 7

INB 4 INB OUTB 5

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Figure 8-1. UCCx732x Driving Two Independent MOSFETs

8.2.1 Design Requirements

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

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Figure 8-2. Current Sink Capability Test

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Figure 8-3. Current Source Capability Test

8.2.2.2 Parallel Outputs

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Figure 8-4. Parallel Operation of UCCx7323 and UCCx7324

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Product Folder Links: UCC27323 UCC27324 UCC27325 UCC37323 UCC37324 UCC37325

P = 10 nF × (12 V)2 × (300 kHz) = 0.432 W (4)

With a 12-V supply, this equates to a current of (see Equation 5):