Embedded Linux Conference 2020:
Linux on RISC-V with open source hardware and open source FPGA tools
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, the Reform laptop and more.
I will also talk about the importance of the open RISC-V instruction set and free software FPGA toolchains. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a SoC capable of running Linux.
Finally, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
OmniXtend is an open source cache coherence protocol that runs over Ethernet. It allows for a unified memory fabric that scales beyond what is possible with traditional CPU-centric architectures. OmniXtend implements the TileLink cache coherence protocol over Ethernet frames, eliminating the need to rewrite software and enabling new data-centric architectures by decoupling compute from memory. The CHIPS Alliance is developing OmniXtend as an open standard with the goal of driving more collaboration in the hardware development community.
This document proposes a no-human-in-the-loop open-source "idea to manufacturing" SoC compiler. It consists of SoCGen, which generates RTL from a JSON description, and OpenLANE, which produces a clean GDSII layout from the RTL with no human intervention. SoCGen includes a library of open-source verified IP cores and supports multiple bus architectures. OpenLANE uses carefully-curated open-source EDA tools tuned for an open PDK. The goal is to streamline and automate the entire custom SoC design process from concept to silicon to enable more widespread adoption.
The document discusses developing applications for the PolarFire® System on Chip (SoC) field programmable gate array (FPGA). It notes that developing for the PolarFire SoC is less complicated than it seems. It covers the functionality of the application and monitor cores, how to develop bare metal applications using SoftConsole IDE, and how to develop FPGA applications using the Libero SoC Design Suite. Examples of driver code and build systems are also provided to simplify the development process for the PolarFire SoC.
This document summarizes a presentation given at the London Open Source Meetup for RISC-V on April 19, 2021. The presentation introduced the RISC-V Online Tutor, an online course for learning RISC-V fundamentals from digital logic to C programming. It provided an overview of the course structure and lessons, which take students through RISC-V assembly, processor design, and application development. It also demonstrated the online learning platform and its ability to interact with remote FPGA hardware during lessons. The goal is to invite community participation and collaboration to further develop the Online Tutor.
This document discusses emulating systems-on-chip (SoCs) on Amazon Web Services (AWS) field-programmable gate arrays (FPGAs). It describes how the author validated a RISC-V CPU design by running Linux on it within an AWS F1 FPGA instance. It provides details on using Bluespec System Verilog (BSV) to model CPU cores, the AWS FPGA shell, Connectal for connecting hardware and software, and virtio device models to emulate I/O without custom drivers. The document shows how the approach allows running different RISC-V processor designs from the DARPA SSITH program securely in the cloud for security evaluation.
The document discusses the Linaro Hardware Group's Open Embedded layer strategy and current status of implementation. The strategy proposes meta layers for integrating established recipes, hosting Linaro recipes, and building reference images. Current status reports successful builds of Weston, multimedia, and Chromium images on Dragonboard 410c and BeagleBone Black. Meta-backports are used to backport components like Wayland from the latest OpenEmbedded release to the current stable release for reference builds.
The document discusses several single board computers that can be used for IoT and Tizen development including the Raspberry Pi, Odroid, Minnowboard Max, and Samsung's new ARTIK boards. It provides guidance on installing Tizen or building from source using Yocto Project on various boards. Graphics support can sometimes be challenging for boards without 3D acceleration. IoTivity allows interacting with other IoT devices and products across different operating systems and hardware platforms.
LAS16-106: GNU Toolchain Development LifecycleLinaro
LAS16-106: GNU Toolchain Development Lifecycle
Speakers: Ryan Arnold
Date: September 26, 2016
★ Session Description ★
This presentation will examine the lifecycle of toolchain development from inception of the micro-architecture, to development of the ISA, to delivery of OS enablement in FOSS projects, to adoption in Linux Distributions. It will examine the behaviors of successful silicon vendors as well as behaviors of vendors that struggle to get their platform fully enabled in the GNU/Linux OS.
★ Resources ★
Etherpad: pad.linaro.org/p/las16-106
Presentations & Videos: http://connect.linaro.org/resource/las16/las16-106/
★ Event Details ★
Linaro Connect Las Vegas 2016 – #LAS16
September 26-30, 2016
http://www.linaro.org
http://connect.linaro.org
BKK16-100K1 George Grey, Linaro CEO Opening KeynoteLinaro
George Grey, Linaro CEO, gives the opening keynote on Monday morning. He will discuss Linaro’s activities across the ARM ecosystem from sensor devices to the data-center. New initiatives including end-to-end open source software platform solutions will be announced and demonstrated.
The document provides an overview of IoTivity, an open source framework for connecting devices. It discusses how IoTivity implements the Open Connectivity Foundation standard to provide seamless discovery and communication between devices. Examples are shown of building an IoTivity server on Arduino and clients on Tizen to create a multi-controlled binary switch that can be read and written to by multiple connected clients. The document encourages exploring IoT development and discusses how IoTivity supports connectivity across various hardware platforms.
The document discusses porting OpenJ9 JDK to RISC-V architecture. It involves preparing the software toolchain for cross-compilation to RISC-V, preparing hardware like the HiFive Unleashed development board, and developing OpenJ9 JDK through a mix of local and cross compilation. The status shows OpenJ9 JDK can execute in interpreter mode on the RISC-V emulator and HiFive board running Debian, with future work planned on JIT support, different GC strategies, and supporting other Java versions.
MultiZone is an IoT firmware that provides a trusted execution environment (TEE) for securing IoT applications on RISC-V processors. It includes pre-integrated libraries for TCP/IP, TLS, ECC and FreeRTOS to handle basic and advanced IoT requirements. MultiZone provides four separated execution environments called zones that are enforced by hardware to isolate trusted applications from untrusted third party code and libraries. It allows for building secure IoT devices, remote firmware updates, and real-time device monitoring and management without needing proprietary hardware extensions.
NAB 2019 Latest Technical and Business Progress with AV1Karan "Kay" Singh
The document summarizes the progress of AV1, an open video codec standard. It discusses concerns raised at NAB 2018 regarding AV1's adoption, including that the bitstream was not frozen and hardware support was lacking. It then outlines key milestones in 2018-2019, such as the dav1d optimized decoder project and its integration in browsers. The document concludes by noting compression gains of AV1 vs other standards but higher encoding complexity compared to alternatives like H.264.
This document discusses porting the Tock operating system to the OpenTitan project. It provides background on OpenTitan and Tock, describes the status of the porting work, and highlights a deep dive into implementing USB and CTAP support on Tock running on OpenTitan hardware. Key points covered include OpenTitan using the Ibex RISC-V core, Tock being designed for small platforms without MMUs and enforcing security through Rust, the interface for Tock applications, and modules already supported through the mainline Tock project.
BKK16-310 The HiKey AOSP collaborative experience Linaro
An overview of collaborative effort done by Builds and Baselines, LMG, 96boards and HiKey landing team in getting HiKey integrated into AOSP. Covers work on the AOSP common.git branches, cross kernel/bootloader feature work that provides more form-factor like integration not commonly found on devboards, lessons learned, etc.
Slides for my presentation on RISC-V and open source chip design at PumpingStation1 hackerspace tonight https://github.com/pdp7/talks/blob/master/nerp-riscv.pdf
Berlin Embedded Linux meetup: How to Linux on RISC-VDrew Fustini
Berlin Embedded Linux meetup: How to Linux on RISC-V... with open hardware and open source FPGA tools.
I will introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the important of free software FPGA tools like yosys for synthesis, and nextpnr for place and route, and how SymbiFlow is leveraging bitstream documentation from Project IceStrom (iCE40), Project Trellis (ECP5), and Project X-Ray (Xilinix).
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
In conclusion, I will explore the landscape of open source chip design projects and the Linux-capable RISC-V silicon chips on horizon for 2020.
Linux on RISC-V with Open Source Hardware (Open Source Summit Japan 2020)Drew Fustini
Want to run Linux on open hardware? This talk will explore how the RISC-V, an open instruction set (ISA), and open source FPGA tools can be leveraged to achieve that goal. I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on a RISC-V soft-core in the ECP5 FPGA on the conference badge. I will introduce Migen, LiteX and Vexriscv, and explain how they enabled us to quickly implement an SoC in the FPGA capable of running Linux. I will also explore other Linux-capable open source RISC-V implementations, and how some are being used in industry. Finally, I will look at what Linux-capable "hard" RISC-V SoC's currently exist, and what is on the horizon for 2021. This talk is should be relevant to people who are interested in building open hardware systems capable of running Linux. It should also be useful to people who are curious about RISC-V. Software engineers may find it exciting to learn how Python can be used to for chip-level design with Migen and LiteX, and simplify building a System-on-Chip (SoC) for an FPGA.
Google Slides link https://tinyurl.com/y6j8lfyz
The document discusses Fedora on RISC-V, including:
1) The history and status of Fedora on RISC-V, including bootstrapping efforts and supported targets like QEMU and various RISC-V boards.
2) Details on the toolchain, QEMU, libvirt/VM tools, and development environment for building and running Fedora on RISC-V.
3) The boot flow and build process for firmware like OpenSBI and U-Boot when creating Fedora images for RISC-V platforms.
Linux on Open Source Hardware with Open Source chip design (36c3)Drew Fustini
Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.
Presented at the 36th Chaos Communication Congress (36c3) in Leipzig, Germany:
https://fahrplan.events.ccc.de/congress/2019/Fahrplan/events/10549.html
Video: https://media.ccc.de/v/36c3-10549-linux_on_open_source_hardware_with_open_source_chip_design
YouTube: https://www.youtube.com/watch?v=mnOBTD9dgsg
Embedded Fest 2019. Wei Fu. Linux on RISC-V--Fedora and Firmware in practiceEmbeddedFest
The document discusses Fedora and firmware development for RISC-V platforms. It provides an overview of boot processes, toolchains, and images for running Fedora natively on RISC-V hardware. Key points include: the current boot flow uses OpenSBI and U-Boot firmware with EDK2; toolchain and QEMU packages are available to build Fedora via cross-compilation or natively; and Fedora images have been tested on various RISC-V boards running on QEMU or directly on hardware like the SiFive Unleashed.
From Make 'n Tell at xHain hackerspace in Berlin, I introduce the open RISC-V instruction set architecture (ISA) and explain how it is enabling a new generation of open source chip design. I will also discuss the importance of free software FPGA tools.
I will explain how myself and others at Hackaday Supercon teamed up to get Linux running on RISC-V core in the ECP5 FPGA badge. I will explain what LiteX is and how it enabled us to quickly build a System-on-Chip (SoC) capable of running Linux.
I finish by talking about how Fomu is a great FPGA board to get started with!
Video and slides synchronized, mp3 and slide download available at URL http://bit.ly/2X8uz92.
Alex Bradbury gives an overview of the status and development of RISC-V as it relates to modern operating systems, highlighting major research strands, controversies, and opportunities to get involved. Filmed at qconlondon.com.
Alex Bradbury is co-founder of lowRISC CIC, aiming to bring the benefits of open source development to the hardware industry by producing a high quality, secure, and open source SoC and associated infrastructure. He is a well-known member of the LLVM community, and is code owner and primary author of the upstream RISC-V back-end.
CPU Diversity is growing: POWER and RISC-V OpenISA are real option with FPGA, ASIC and Motherboard available next year
Which are Open Hardware Power Architecture real options? Microwatt and LibreSoc have samples of low power Open ISA Power chip. The Power Progress Community released the Prototypes of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. What happen around OpenPower Foundations with project like PowerPI and LibreBMC.
Making Open Source Hardware IoT with Raspberry PiLeon Anavi
This document discusses how to create open source hardware for IoT using Raspberry Pi. It introduces Raspberry Pi add-on boards like HATs and pHATs, which have standard form factors and interface with the 40-pin GPIO header. The document outlines the requirements and specifications for HATs and pHATs, and how to design hardware following these standards. It also discusses open source hardware licenses, designing PCBs using tools like KiCAD, prototyping boards, and providing software support for open hardware projects.
Open Source Hardware and Libre SiliconDrew Fustini
My Open Source Hardware and Libre Silicon talk for Penguicon 2017.
Open Source Hardware (OSHW) designs are made publicly available so that anyone can study, modify, distribute, make or sell designs or hardware based on that design. This talk will explore the shared values with Open Source software and the specifics of publishing a hardware project under an Open Source license.
It will include examples of Linux running on OSHW with projects like BeagleBone, CHIP, MinnowBoard and more. The role of the Open Source Hardware Association and annual Open Hardware Summit will also be discussed, along with important OSHW projects for scientific researchers.
There are exciting new developments within the last year for OSHW at the chip level. Projects like lowRISC, J-Core, OnChip and SiFive are working to produce true Open Source silicon processors. The FOSSi Foundation and LibreCores are helping to organize and promote this exciting new ecosystem.
Introduction to Open Source Hardware, OSHWA and Open Hardware SummitDrew Fustini
The document provides an overview of open source hardware, including definitions of open source, examples like Arduino, required documentation for electronics projects, licenses, and resources like the Open Hardware Summit and Open Source Hardware Association. It discusses open hardware principles, certification, and the use of Linux on open hardware boards and single-board computers.
This document summarizes the evolution of the RISC-V software ecosystem from 2015 to 2020. It describes how initial ports of key software in 2015, like GCC and Linux, have expanded to include upstream support in most open source software projects today. It outlines remaining priorities like completing support for specifications and filling gaps in programming language and application software support. The document concludes by encouraging continued collaboration to further mature the RISC-V software ecosystem.
Cytoscape and External Data Analysis ToolsKeiichiro Ono
This document summarizes Keiichiro Ono's lab meeting presentation about developing a RESTful API for Cytoscape. The presentation covered the motivation for external tools to programmatically access Cytoscape, the design of a new Cytoscape module that exposes a RESTful API, and a proof-of-concept demo. The goal is to make Cytoscape more accessible for hardcore users to embed in automated workflows from languages like R and Python.
Embedded Recipes 2019 - Linux on Open Source Hardware and Libre SiliconAnne Nicolas
This talk will explore Open Source Hardware projects relevant to Linux, including boards like BeagleBone, Olimex OLinuXino, Giant board and more. Looking at the benefits and challenges of designing Open Source Hardware for a Linux system, along with BeagleBoard.org’s experience of working with community, manufacturers, and distributors to create an Open Source Hardware platform. In closing also looking at the future, Libre Silicon like RISC-V designs, and where this might take Linux.
Drew Fustini
This document summarizes information about the $9 CHIP computer created by Next Thing Co. It discusses the company's participation in the HAX accelerator program, their successful Kickstarter campaign to fund CHIP, and their efforts to integrate CHIP into the mainline Linux kernel through working with Free Electrons developers. It also provides links to resources on the CHIP hardware design, software documentation, and community forums for developing applications and exploring the GPIO pins on CHIP.
Automotive Grade Linux on Raspberry Pi: How Does It Work?Leon Anavi
Talk by Leon Anavi at Embedded Linux Conference North America 2020
Automotive Grade Linux (AGL) is a leading embedded Linux distribution for the automotive industry. The AGL Unified Code Base (UCB), using the Yocto Project and OpenEmbedded, has been already adopted by automotive manufacturers and it is present in vehicles like Toyota Camry and all-new 2020 Subaru Outback and Subaru Legacy.
Since 2016 AGL has been ported to Raspberry Pi which nowadays is a prefer getting started platform among the community. The presentation will explore the current status of AGL on Raspberry Pi, reveal war stories and practical experiences for supporting Wayland, PipeWire, libostree for software over the air updates as well as various hardware peripherals.
Guidelines and step by step instructions for building AGL image for Raspberry Pi will be revealed. We will do a deep dive in internals, such as integration of meta-raspberrypi BSP layer, Linux kernel and Mesa versions with firmware KMS to support both HDMI and the official Raspberry Pi touch screen DSI display.
The talk is appropriate for anyone, including beginners. No previous experience is required. Hopefully, the presentation will encourage more people to try AGL on Raspberry Pi and join our community.
PPC64 Open ISA and A2I Core along with the PPC64 Open Hardware Notebook PCB and Libre-Soc project.
This year IBM released the A2I POWER processor core design and associated FPGA environment. In 2019 IBM opened the POWER Instruction Set Architecture (ISA). The Power Progress Community released the PCB of the Notebook Motherboard based on Power Architecture with Cern Open Hardware License. Libre-SOC is a software-hardware project that aims to deliver a physical POWER compliant SOC that comes complete with a CPU, GPU, VPU, and DDR controller. We will discover these concrete projects.
Redfish is an IPMI replacement standardized by the DMTF. It provides a RESTful API for server out of band management and a lightweight data model specification that is scalable, discoverable and extensible. (Cf: http://www.dmtf.org/standards/redfish). This presentation will start by detailing its role and the features it provides with examples. It will demonstrate the benefits it provides to system administrator by providing a standardized open interface for multiple servers, and also storage systems.
We will then cover various tools such as the DMTF ones and the python-redfish library (Cf: https://github.com/openstack/python-redfish) offering Redfish abstractions.
The document discusses software-defined networking (SDN) and an alternative paradigm called hybrid open (HOpen) architecture. HOpen architecture separates the control plane from the forwarding plane, like in SDN, but also leverages existing vendor code while allowing operators to develop new features independently. The author provides examples of how Comcast has added new protocols and capabilities to the HOpen platform to innovate more quickly without relying solely on vendors or standards bodies. HOpen represents a middle ground between traditional vendor-controlled networks and pure open SDN and could change how new protocols are developed and adopted.
Open Source Hardware, Linux and RISC-VDrew Fustini
Open Source Hardware "Birds of a Feather” (BoF) session at Embedded Linux Conference 2018 in Portland. Topics include elements of open source hardware designs, applications in science, open source hardware that can run Linux, and recent libre silicon efforts including RISC-V architecture and SiFive.
Overview of Open Source, Free Software and Open Source Hardware (OSHW). Survey of Open Source licenses that can used for OSHW projects. Highlight OSHW projects that are democratizing scientific research equipment and enabling citizen science efforts. Review OSHW projects that have become commercial products. Discussion of different OSHW boards that can run Linux.
OSH Park is a community PCB ordering service that offers high quality, lead free boards manufactured in the USA for inexpensive prices due to shared panel costs. Customers can directly upload Autodesk EAGLE .brd files to OSH Park's website for ordering. It is recommended that customers run design rule checks on their files using OSH Park's Eagle Design Rules files prior to uploading to check for any issues.
The document introduces the BeagleBone Blue, a new single-board computer that combines the capabilities of the BeagleBone Black Wireless and Robotics Cape. It evolves from previous BeagleBone models with ARM processors and is designed for industrial applications. Key features include WiFi/Bluetooth connectivity, on-board microcontrollers, and interfaces integrated onto a single board to simplify building robotics and IoT projects.
Introduction to Open Source Hardware (OSHW) including: the philosophy, best practices, CERN Open Hardware License, Open Hardware Summit, Open Source Hardware Association (OSHWA), Open Source Hardware Certification Program, OSHW Products, Linux on OSHW, and OSHW in Science.
Google Summer of Code and BeagleBoard.orgDrew Fustini
Slides for my Maker Faire New York 2016 talk:
Google Summer of Code and BeagleBoard.org
https://drive.google.com/file/d/0B_NI2VDamOOfOU9MV2lCd2dVSjg/view?usp=sharing
Taking the BeagleBone Cookbook recipes beyond BeagleBone BlackDrew Fustini
NOTE: Slides by Jason Kridner and Mark Yoder
Source: http://event.lvl3.on24.com/event/11/07/48/2/rt/1/documents/resourceList1454015491443/cookbookbeyondblack_draft.pdf
This document discusses software defined radio (SDR) and various low-cost SDR devices that can be used for experimenting with radio signals, including RTL-SDR USB dongles, HackRF, NooElec SDR sticks, and FUNcube Dongles. It provides information on software like GNU Radio, Gqrx, rtl-sdr library, ViewRF, and OpenBTS for processing radio signals on devices like the BeagleBone Black.
Espruino - JavaScript for MicrocontrollersDrew Fustini
Espurino allows programming microcontrollers with JavaScript. It runs on an STM32 board with a Cortex M3 CPU, Flash memory, GPIO pins and other interfaces. JavaScript can be used without compiling, modified during runtime, and has widespread usage and tutorials available. The Espruino board costs $40 and can be programmed over USB or via an online IDE. Examples show blinking LEDs, controlling strings of LEDs, and using timers. Tessel is another JavaScript board aimed at internet-connected devices with built-in WiFi. Micro Python brings the Python language to microcontrollers in a lean and optimized implementation.
The Eudyptula Challenge is a series of programming exercises that teaches Linux kernel development skills. It starts with basic "Hello World" kernel modules and gets progressively more complex, with tasks like submitting patches to the mainline kernel. Over 172 people have had their patches accepted into the kernel as a result of the challenge. It requires basic C skills and patience for working with large open source projects. The challenge is modeled after the Matasano Crypto Challenge and aims to help people learn and contribute to the Linux kernel.
The 5th Annual Open Hardware Summit was held in Rome, Italy in 2014. It was organized by the Open Source Hardware Association to discuss the growing open hardware movement. Key topics included the Ada Lovelace Fellowship for women in open technology, workshops on open hardware manufacturing and licensing, and presentations from leaders in the field such as Adrian Bowyer of RepRap and Eric Pan of Seeed Studio. The Summit aimed to advance open sharing of hardware knowledge and collaboration on technology development.
Drew Fustini is a software developer and embedded systems engineer seeking a new opportunity where he can apply his expertise in Linux, software development, and embedded systems. He has over 15 years of experience developing software and working with technologies like Arduino, Raspberry Pi, BeagleBone, and Linux. His experience includes roles at element14, Subnetworx, eMvoy Search Engine, UIC, and other companies where he has developed applications, maintained infrastructure, and provided technical support.
The BeagleBone Black is a $45 open source Linux computer developed by the BeagleBoard.org community. It has a 1GHz ARM Cortex A8 processor, 512MB of RAM, and built-in networking and storage. As an open source hardware device, its schematics, board layout, and bill of materials are all publicly available. It runs various Linux distributions from a microSD card or built-in flash and can interface with sensors, motors and other devices through its GPIO pins and capes add-on boards, making it well suited for physical computing projects.
I did an overview of Embedded Linux topics (arch, SoCs, SBCs, kernel dev community, real-time, device tree, building root filesystem, etc) in 2014 for the Embedded Systems meetup at my hackerspace: http://www.meetup.com/NERP-Not-Exclusively-Raspberry-Pi/events/183068212/
An Internet Protocol address (IP address) is a logical numeric address that is assigned to every single computer, printer, switch, router, tablets, smartphones or any other device that is part of a TCP/IP-based network.
Types of IP address-
Dynamic means "constantly changing “ .dynamic IP addresses aren't more powerful, but they can change.
Static means staying the same. Static. Stand. Stable. Yes, static IP addresses don't change.
Most IP addresses assigned today by Internet Service Providers are dynamic IP addresses. It's more cost effective for the ISP and you.
Unblocking The Main Thread - Solving ANRs and Frozen FramesSinan KOZAK
In the realm of Android development, the main thread is our stage, but too often, it becomes a battleground where performance issues arise, leading to ANRS, frozen frames, and sluggish Uls. As we strive for excellence in user experience, understanding and optimizing the main thread becomes essential to prevent these common perforrmance bottlenecks. We have strategies and best practices for keeping the main thread uncluttered. We'll examine the root causes of performance issues and techniques for monitoring and improving main thread health as wel as app performance. In this talk, participants will walk away with practical knowledge on enhancing app performance by mastering the main thread. We'll share proven approaches to eliminate real-life ANRS and frozen frames to build apps that deliver butter smooth experience.
Social media management system project report.pdfKamal Acharya
The project "Social Media Platform in Object-Oriented Modeling" aims to design
and model a robust and scalable social media platform using object-oriented
modeling principles. In the age of digital communication, social media platforms
have become indispensable for connecting people, sharing content, and fostering
online communities. However, their complex nature requires meticulous planning
and organization.This project addresses the challenge of creating a feature-rich and
user-friendly social media platform by applying key object-oriented modeling
concepts. It entails the identification and definition of essential objects such as
"User," "Post," "Comment," and "Notification," each encapsulating specific
attributes and behaviors. Relationships between these objects, such as friendships,
content interactions, and notifications, are meticulously established.The project
emphasizes encapsulation to maintain data integrity, inheritance for shared behaviors
among objects, and polymorphism for flexible content handling. Use case diagrams
depict user interactions, while sequence diagrams showcase the flow of interactions
during critical scenarios. Class diagrams provide an overarching view of the system's
architecture, including classes, attributes, and methods .By undertaking this project,
we aim to create a modular, maintainable, and user-centric social media platform that
adheres to best practices in object-oriented modeling. Such a platform will offer users
a seamless and secure online social experience while facilitating future enhancements
and adaptability to changing user needs.
A brand new catalog for the 2024 edition of IWISS. We have enriched our product range and have more innovations in electrician tools, plumbing tools, wire rope tools and banding tools. Let's explore together!
Literature Reivew of Student Center DesignPriyankaKarn3
It was back in 2020, during the COVID-19 lockdown Period when we were introduced to an Online learning system and had to carry out our Design studio work. The students of the Institute of Engineering, Purwanchal Campus, Dharan did the literature study and research. The team was of Prakash Roka Magar, Priyanka Karn (me), Riwaz Upreti, Sandip Seth, and Ujjwal Dev from the Department of Architecture. It was just a scratch draft made out of the initial phase of study just after the topic was introduced. It was one of the best teams I had worked with, shared lots of memories, and learned a lot.
Exploring Deep Learning Models for Image Recognition: A Comparative Reviewsipij
Image recognition, which comes under Artificial Intelligence (AI) is a critical aspect of computer vision,
enabling computers or other computing devices to identify and categorize objects within images. Among
numerous fields of life, food processing is an important area, in which image processing plays a vital role,
both for producers and consumers. This study focuses on the binary classification of strawberries, where
images are sorted into one of two categories. We Utilized a dataset of strawberry images for this study; we
aim to determine the effectiveness of different models in identifying whether an image contains
strawberries. This research has practical applications in fields such as agriculture and quality control. We
compared various popular deep learning models, including MobileNetV2, Convolutional Neural Networks
(CNN), and DenseNet121, for binary classification of strawberry images. The accuracy achieved by
MobileNetV2 is 96.7%, CNN is 99.8%, and DenseNet121 is 93.6%. Through rigorous testing and analysis,
our results demonstrate that CNN outperforms the other models in this task. In the future, the deep
learning models can be evaluated on a richer and larger number of images (datasets) for better/improved
results.
A brief introduction to quadcopter (drone) working. It provides an overview of flight stability, dynamics, general control system block diagram, and the electronic hardware.
Response & Safe AI at Summer School of AI at IIITHIIIT Hyderabad
Talk covering Guardrails , Jailbreak, What is an alignment problem? RLHF, EU AI Act, Machine & Graph unlearning, Bias, Inconsistency, Probing, Interpretability, Bias
How to Manage Internal Notes in Odoo 17 POSCeline George
In this slide, we'll explore how to leverage internal notes within Odoo 17 POS to enhance communication and streamline operations. Internal notes provide a platform for staff to exchange crucial information regarding orders, customers, or specific tasks, all while remaining invisible to the customer. This fosters improved collaboration and ensures everyone on the team is on the same page.
1. Linux on RISC-V
Drew Fustini
drew@beagleboard.org
Twitter: @pdp7
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
with open source hardware and open source FPGA tools
Embedded Linux Conference 2020
2. Open Source Hardware designer at OSH Park
(PCB manufacturing service in the USA)
drew@oshpark.com / Twitter: @oshpark
Board of Directors, BeagleBoard.org Foundation
drew@beagleboard.org
Board of Directors, Open Source Hardware Assoc.
Certification Program:
https://certification.oshwa.org/
RISC-V Ambassador for RISC-V International
https://riscv.org/
6. RISC-V at ELC
●
RISC-V: Instruction Sets Want to be Free
– Krste Asanovic (UC Berkeley)
– Wednesday, 10:35am: https://sched.co/c4PV
●
State of RISC-V Software Development Tools
– Khem Raj (Comcast)
– Wednesday 12:15pm: https://sched.co/c3Yn
●
Ask the Expert Session with Calista Redmond
– CEO of RISC-V International
– Thursday 11:45am: https://sched.co/cosw
7. Statement of Principles:
Hardware whose design is
made publicly available so
that anyone can study,
modify, distribute, make,
and sell the design or
hardware based on that design
8. Documentation required for electronics:
Schematics Board Layout
Editable source files for CAD software such as KiCad or EAGLE
Bill of Materials (BoM)
Not strict requirement, but best practice is for all components available from
distributors in low quantity
11. ●
When you write a C or C++ program, it is
compiled into instructions for the
microprocessor (CPU) to execute.
●
How does the compiler know what instructions
the CPU understands?
– defined by the Instruction Set Architecture
– The ISA is a standard, a set of rules that define
the tasks the processor can perform.
– Examples: x86 (Intel/AMD) and ARM
●
Both are proprietary and need commercial licensing
12. ●
RISC-V: Free & Open RISC Instruction Set Arch
– “new instruction set architecture (ISA) that was originally
designed to support computer architecture research and
education and is now set to become a standard open
architecture for industry”
– The 5th RISC instruction to come out out UC Berkeley
– RISC = Reduced Instruction Set Computer
13. ●
OSS+ELC 2020 Keynote:
“RISC-V: Instruction Sets Want to be Free”
– Krste Asanovic, UC Berkeley
– https://sched.co/c4PV
●
Instruction Sets Want To Be Free: A Case for RISC-V
– David Patterson, UC Berekely (co-creator of the original RISC)
– youtube.com/watch?v=mD-njD2QKN0
21. Is RISC-V Open Source?
●
RISC-V is an open ISA specification
– Creative Commons Attribution 4.0 International
●
An open ISA spec is required to implement an
open source processor
●
Not possible to design an open source processor
for a proprietary ISA such as x86 and ARM
●
Implementations of RISC-V ISA can be both
open source and proprietary
23. RISC-V at ELC
●
Go RISC-V Go:
State of Software Development Tools for RISC-V
– Khem Raj
– Wednesday 12:15pm
– https://sched.co/c3Yn
“Clang/LLVM has newly added backends for RISC-V. In addition, there
is now a golang port, which is still out of tree but headed towards
upstream acceptance. Additionally, GCC is working towards the GCC-
10 release, with several new enhancements to its RISC-V backend.
The LLVM backend also means Rust can now cross-compile to the
RISC-V architecture. The MUSL C library also has a new RISCV 64-bit
port. Additionally, we will discuss the state of tools on the RV32
ecosystem, progress on the glibc port for RV32, and Yocto Project
support for RV32 in its core, where QEMU RV32 port is usable for
doing application port.”
30. RISC-V and Industry
●
Designed to be extensible from microcontroller to
supercomputer!
●
RISC-V International now controls specifications:
riscv.org
– Over 400 members: companies, universities and more
– RISC-V Foundation transitioning to Swiss-based
RISC-V International
– YouTube channel has hundreds of talks!
●
Companies like Nvidia and Western Digital will
ship millions of devices with RISC-V cores
31. RISC-V and Industry
●
Avoid ISA licensing and royalty fees
●
Freedom to choose micro-architecture
implementation
– only a few companies like Apple, Samsung and
Qualcomm have ARM architecture licenses which
allows them to do a custom implementation
●
Freedom to leverage existing open source
implementations
– Berkeley’s Rocket and BOOM, ETH Zurich’s PULP
cores, Western Digital SweRV
32. ●
lowRISC is a not-for-profit organization whose goal
is to produce a fully open source System-on-Chip
(SoC) in volume
– “We will produce a SoC design to populate a low-cost
community development board and to act as an ideal
starting point for derivative open-source and
commercial designs”
●
OpenTitan project with Google
– Announcing OpenTitan, the First Transparent Silicon Root of Trust
33. SiFive
●
“founded by the creators of the free and open
RISC-V architecture as a reaction to the end of
conventional transistor scaling and escalating
chip design costs”
36. ●
SiFive Freedom FU540 SoC
– FOSDEM 2018 talk: “Igniting the Open Hardware
Ecosystem with RISC-V”
37. ●
SiFive Freedom FU540 SoC
– HiFive Unleashed board:
●
powerful but expensive ($1,000) and very limited
quantity
38. “Fedora on RISC-V”, Wei Fu (RV Summit 2019)
https://www.youtube.com/watch?v=WC6e3g8uWdk
40. Kendryte 210
●
400MHz dual core RV64GC
●
8MB SRAM
●
Sipeed MAix BiT for RISC-V is only $13!
●
Damien Le Moal at Linux Plumbers 2019
– “RISC-V NOMMU and M-mode Linux”
●
Full support coming in Linux 5.8
●
Buildroot with busybox
– https://git.io/JJflC
41. Kendryte 210
●
need NOMMU/FDPIC support for better
userspace
– https://youtu.be/GydyykyNjxs (Maciej W. Rozycki)
– 8MB runs out very quick!
●
there is a MMU but an earlier spec which is not
supported by Linux
●
u-boot patch series
– [PATCH v14 00/20] riscv: Add Sipeed Maix support
– Sean Anderson (June 24th)
43. Microchip PolarFire SoC FPGA
●
Hard RISC-V cores with FPGA fabric, similar to Xilinx
Zynq for ARM. Coming 2nd half 2020.
45. OpenHW Group: Core-V Chassis SoC
●
similar to NXP iMX but with RISC-V cores
●
tape-out 2nd half of 2020
47. ●
Keynote at Hackday Supercon 2019 by
Dr. Megan Wachs of SiFive
●
“RISC-V and FPGAs: Open Source Hardware
Hacking”
– https://www.youtube.com/watch?v=vCG5_nxm2G4
49. ●
Project IceStorm for Lattice iCE40
●
“A Free and Open Source Verilog-to-Bitstream Flow for iC
E40 FPGAs”
by Claire Wolf (oe1cxw) at 32c3
Open Source toolchains for FPGAs
50. ●
Project Trellis for Lattice ECP5
– “Project Trellis and nextpnr FOSS FPGA flow for the
Lattice ECP5”
- David Shah (@fpga_dave)
●
youtube.com/watch?v=0se7kNes3EU
Open Source toolchains for FPGAs
51. ●
Project X-Ray & SymbiFlow for Xilinix Series 7
– Timothy ‘mithro’ Ansell: “Xilinx Series 7 FPGAs Now
Have a Fully Open Source Toolchain!” (almost)
●
youtube.com/watch?v=EHePto95qoE
Open Source toolchains for FPGAs
52. Hackspace Magazine column on how
open source FPGA tools developed by
Claire Wolf (oe1cxw), David Shah and others
have made FPGAs more accessible than ever
before to makers and hackers:
hackspace.raspberrypi.org/issues/26/
Open Source and FPGAs
53. Section:
Linux on the Hackaday Badge
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
54. Hackaday 2019 Supercon badge
●
RISC-V “soft” core on ECP5 FPGA
●
Gigantic FPGA In A Game Boy Form Factor
56. “Team Linux on Badge”
●
Blog post: Hackaday Supercon badge boots
Linux using SDRAM cartridge
●
Michael Welling (@QwertyEmedded), Tim
Ansell (@mithro), Sean Cross (@xobs), Jacob
Creedon (@jacobcreedon)
●
First attempt: use the built-in 16MB SRAM…
no luck :(
57. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
58. “Team Linux on Badge”
●
Second attempt:
– Jacob Creedon designed an a cartridge board that
adds 32MB of SDRAM to the Hackaday Supercon
badge… before the event!
60. Designing Hardware in Python?
●
Yes!
●
“Using Python for creating hardware to record
FOSS conferences!”
●
Tim “mithro” Ansell
●
youtube.com/watch?v=MkVX_mh5dOU
62. ●
LiteX used to build cores, create SoCs and full
FPGA designs.
●
LiteX is based on Migen
●
Migen lets you do FPGA design in Python!
●
https://github.com/enjoy-digital/litex
64. Linux on LiteX-VexRiscv
●
VexRiscv: 32-bit Linux Capable RISC-V CPU
●
SoC built using VexRiscv core and LiteX
modules like LiteDRAM, LiteEth, LiteSDCard, ...
– github.com/litex-hub/linux-on-litex-vexriscv
66. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
67. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
68. ●
upstream support for Hackaday Supercon badge:
– https://github.com/litex-hub/litex-boards/pull/31
74. ●
Greg Davill got the screen working with LiteVideo!
– twitter.com/GregDavill/status/1231082623633543168
75. Open Source boards with
ECP5 FPGA
(can run Linux)
Slides: https://github.com/pdp7/talks/blob/master/rv-elc.pdf
91. RISC-V at ELC
●
RISC-V: Instruction Sets Want to be Free
– Krste Asanovic (UC Berkeley)
– Wednesday, 10:35am: https://sched.co/c4PV
●
State of RISC-V Software Development Tools
– Khem Raj (Comcast)
– Wednesday 12:15pm: https://sched.co/c3Yn
●
Ask the Expert Session with Calista Redmond
– CEO of RISC-V International
– Thursday 11:45am: https://sched.co/cosw