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This paper presents an ADC architecture comprising a pipelined cyclic ADC and continuous-time delta-sigma ADC; it provides high resolution at medium speed, with small power requirements. It is also reconfigurable for different... more
This paper presents an ADC architecture comprising a pipelined cyclic ADC and continuous-time delta-sigma ADC; it provides high resolution at medium speed, with small power requirements. It is also reconfigurable for different combinations of speed, precision, and power consumption. The cyclic ADC produces a residue after the final cycle, and the following delta-sigma ADC converts it to a digital value (the residue is then noise-shaped). The ADC output combines the digital outputs of the cyclic ADC and the delta-sigma ADC so as to achieve high resolution. The delta-sigma ADC can be implemented simply with continuous-time analog circuitry. We describe the overall ADC architecture and operation, show simulation results, as well as features such as its potential for reconfiguration and one of ADC architecture candidates with good tradeoff for high resolution, medium speed and small power.
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This paper describes a high-precision strain measurement system using modern ADC and digital technology to provide real-time compensation for parasitic capacitance effects. In recent applications, strain gauges used for strain measurement... more
This paper describes a high-precision strain measurement system using modern ADC and digital technology to provide real-time compensation for parasitic capacitance effects. In recent applications, strain gauges used for strain measurement often have to be located far from strain measuring instruments, requiring long connecting cables with associated parasitic capacitance; in such cases the parasitic capacitance degrades measurement accuracy significantly, and
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This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing... more
This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.
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This paper presents circuit design to implement our proposed data-weighted averaging (DWA) algorithm to improve the SNR and resolution of multi-bit complex bandpass ∆ΣADCs for wireless communica- tion systems such as cellular phone,... more
This paper presents circuit design to implement our proposed data-weighted averaging (DWA) algorithm to improve the SNR and resolution of multi-bit complex bandpass ∆ΣADCs for wireless communica- tion systems such as cellular phone, wireless LAN and Bluetooth applications. Oversampling and noise-shaping are used to achieve high accuracy of a ∆ΣAD modulator. However when a multi-bit internal DAC is used inside a modulator, nonlinearities of the DAC are not noise-shaped and the SNR of the ∆ΣADC degrades. For the conversion of complex intermediate frequency (IF) input signals, a complex bandpass ∆ΣAD modulator can provide superior performance to a pair of real bandpass ∆ΣAD modulators of the same order. Hence we have already proposed a new noise-shaping algorithm to reduce the effects of nonlinearities in multi-bit DACs of complex bandpass ∆ΣAD modulators, and in this paper, we will describe its circuit design to implement a whole multi-bit complex bandpass ∆ΣADC. キーワード: マルチビット,複素バンドパス...
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This paper proposes state-transition plane and error plane methods to identify the ADC error type (such as additive noise, multiplicative noise, jitter and harmonics) in the sine wave ADC testing, and the theoretical analysis and... more
This paper proposes state-transition plane and error plane methods to identify the ADC error type (such as additive noise, multiplicative noise, jitter and harmonics) in the sine wave ADC testing, and the theoretical analysis and simulation results demonstrate their effectiveness. Also an ADC output waveform reconstruction algorithm which is applicable for an incoherent sampling ADC testing is proposed. These results would be useful for developing new error correction algorithms and analyzing the sine wave ADC testing theoretically as well as identifying ADC error sources