Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Skip to main content

    L. Mariucci

    Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical... more
    Polysilicon thin-film transistors are of great interest for their application in large area microelectronics and especially for their circuit applications. A successful circuit design requires a proper understanding of the electrical characteristics and in the present work some specific aspects related to the presence of high electric fields at the drain end of the channel are presented.
    Research Interests:
    Research Interests:
    ABSTRACT This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution.... more
    ABSTRACT This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Data on single devices and elementary complementary digital circuits (inverters and ring oscillators) are presented, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices.
    ABSTRACT Control of the source-drain contact properties in amorphous InGaZnO semiconductor active layer is relevant since a high series resistance in the source-drain contacts causes degradation of electrical performance, particularly... more
    ABSTRACT Control of the source-drain contact properties in amorphous InGaZnO semiconductor active layer is relevant since a high series resistance in the source-drain contacts causes degradation of electrical performance, particularly affecting short channel devices. We developed a method to extract the current-voltage characteristics of the injection contact, assuming that contact effects are negligible in long channel devices and by introducing a modified gradual channel approximation (quasi-two-dimensional model), to take into account for short channel effects. The present method allows to extract the parasitic resistance by using devices with only two different channel lengths. Assuming a transmission line scheme for the contact resistance and SCLC transport for the current density flowing along the vertical direction though the IGZO bulk, we have been able to evaluate the variation with ${\rm V}_{{\rm ds}}$ of contact resistance at source and drain electrodes.
    Contact effects in staggered SBTs with three different active layers (organic semiconductor (pentacene derivative), a-Si:H and IGZO) have been analyzed by using numerical simulations. In general, in staggered SBTs the presence of a... more
    Contact effects in staggered SBTs with three different active layers (organic semiconductor (pentacene derivative), a-Si:H and IGZO) have been analyzed by using numerical simulations. In general, in staggered SBTs the presence of a Schottky barrier at the source severely limits the carrier injection, thus substantially reducing the on-current and, consequently, the on-off ratio, if compared to conventional TFT structures. On the other hand, depending upon barrier height and barrier lowering mechanisms, staggered SBTs can show interesting features, such as: 1) very low saturation voltage, resulting in much lower operating drain voltages and power dissipation; 2) increased output impedance, leading to larger voltage gain; 3) simpler fabrication, as doped regions are not necessary. Device characteristics of these devices are seriously influenced by contact effects, with the parasitic voltage drops at the contacts reducing the effective voltages applied to the channel of the transistor....
    The transfer and output electrical characteristics of polysilicon thin film transistors have been measured in the temperature range from 400 to 80 K. The devices, with the active layer made by excimer laser crystallization of amorphous... more
    The transfer and output electrical characteristics of polysilicon thin film transistors have been measured in the temperature range from 400 to 80 K. The devices, with the active layer made by excimer laser crystallization of amorphous silicon, show high field-effect mobility values (>200 cm2/Vs), even at low temperature. The electrical characteristics have been analyzed using a uniformly distributed density of
    ... Corresponding Author Contact Information , E-mail The Corresponding Author , a , L. Mariucci a , M. Stanizzi a , V. Privitera b , S ... Scaling critical dimension below 0.13 μm for complementary metal–oxide–semiconductor (CMOS)... more
    ... Corresponding Author Contact Information , E-mail The Corresponding Author , a , L. Mariucci a , M. Stanizzi a , V. Privitera b , S ... Scaling critical dimension below 0.13 μm for complementary metal–oxide–semiconductor (CMOS) devices, will require formation of source/drain (S/D ...
    High densities of self-catalyzed Si nanowires have been grown at temperatures down to 320 degrees C on different Si substrates, whose surfaces have been roughened by simple physical or chemical treatments. The particular substrates are... more
    High densities of self-catalyzed Si nanowires have been grown at temperatures down to 320 degrees C on different Si substrates, whose surfaces have been roughened by simple physical or chemical treatments. The particular substrates are Si(110) cleavage planes, chemically etched Si(111) surfaces and microcrystalline Si obtained by laser annealing thin amorphous Si layers. The NW morphology depends on the growth surface. Transmission electron microscopy indicates that the NWs are made of pure Si with a crystalline core structure. Reflectivity measurements confirm this latter finding.
    The effect of excimer laser annealing (ELA) and rapid thermal annealing (RTA) on B redistribution in B-implanted Si has been studied by secondary ion mass spectrometry (SIMS) and spreading resistance probe (SRP). B has been implanted with... more
    The effect of excimer laser annealing (ELA) and rapid thermal annealing (RTA) on B redistribution in B-implanted Si has been studied by secondary ion mass spectrometry (SIMS) and spreading resistance probe (SRP). B has been implanted with an energy of 1keV and a dose of 1016cm−2 forming a distribution with a width of 20–30nm and a peak concentration of ∼5
    The space-charge density variation induced by illumination in metal-insulator-amorphous-semiconductor structures has been observed for the first time by monitoring the transient photocurrent. The dependence of the charge variation on the... more
    The space-charge density variation induced by illumination in metal-insulator-amorphous-semiconductor structures has been observed for the first time by monitoring the transient photocurrent. The dependence of the charge variation on the gate voltage provides a useful tool for the flatband voltage determination. >
    We have investigated the effect of excimer laser annealing (ELA) on transient enhanced diffusion (TED) and activation of boron implanted in Si during subsequent rapid thermal annealing (RTA). It is observed that ELA with partial melting... more
    We have investigated the effect of excimer laser annealing (ELA) on transient enhanced diffusion (TED) and activation of boron implanted in Si during subsequent rapid thermal annealing (RTA). It is observed that ELA with partial melting of the implanted region causes reduction of TED in the region that remains solid during ELA, where the diffusion length of boron is reduced
    ABSTRACT The effects of hot carriers on the electrical characteristics of polycrystalline silicon p-channel thin film transistors have been analyzed, combining experimental data and numerical simulations. The transfer characteristics... more
    ABSTRACT The effects of hot carriers on the electrical characteristics of polycrystalline silicon p-channel thin film transistors have been analyzed, combining experimental data and numerical simulations. The transfer characteristics showed minor variations upon application of prolonged bias stress, while the output characteristics presented a reduction of kink effect. These results have been explained by using a self-consistent model based on the trapping of injected hot electrons. The authors’ charge injection model provided a precise evaluation of the extension of the trapped charge regions, at both front and back interfaces. By using such trapped charge distributions, it was possible to reproduce the output characteristics variations as well as the minor on-current increase observed in the transfer characteristics after bias stress.
    ABSTRACT Recently, we proposed asymmetric fingered polysilicon thin film transistors, where the transistor channel region is split into two zones with different lengths separated by a floating n(+) region, which allows an effective... more
    ABSTRACT Recently, we proposed asymmetric fingered polysilicon thin film transistors, where the transistor channel region is split into two zones with different lengths separated by a floating n(+) region, which allows an effective reduction of the kink effect. In this work, we analysed the experimental electrical characteristics by using numerical simulations for a specific channel configuration and then we studied the effects of prolonged bias stress on these devices and conventional non self-aligned thin film transistors. We found that asymmetric fingered transistors are characterized by a substantial reduction of the transconductance degradation induced by hot carrier effect, if compared to conventional thin film transistors. By modeling the device with two transistor in series, we could explain the reduced effects of hot carrier-induced degradation. (C) 2005 Elsevier B.V. All rights reserved.
    ... 6M. A. El Khakani, V. Le Borgne, B. Aïssa, F. Rosei, C. Scilletta, E. Speiser, M. Scarselli, P. Castrucci, and M. De Crescenzi, Appl. Phys. Lett. ... 17M. Glatthaar, M. Riede, N. Keegan, K.Sylvester-Hvid, B. Zimmermann, M. Niggemann,... more
    ... 6M. A. El Khakani, V. Le Borgne, B. Aïssa, F. Rosei, C. Scilletta, E. Speiser, M. Scarselli, P. Castrucci, and M. De Crescenzi, Appl. Phys. Lett. ... 17M. Glatthaar, M. Riede, N. Keegan, K.Sylvester-Hvid, B. Zimmermann, M. Niggemann, A. Hinsch, and A. Gombert, Sol. Energy Mater. ...
    The effects of the laser irradiation on metal-oxide-semiconductor structures are investigated by means of a phase-field methodology. We numerically solved the model equations in one-and two-dimensional structures also containing... more
    The effects of the laser irradiation on metal-oxide-semiconductor structures are investigated by means of a phase-field methodology. We numerically solved the model equations in one-and two-dimensional structures also containing /amorphous-Si/crystalline-Si stacks. The ...
    Output characteristics of poly-Si thin film transistors (TFTs) have been measured for different channel length and temperature and a... more
    Output characteristics of poly-Si thin film transistors (TFTs) have been measured for different channel length and temperature and a ``kink'' is observed similar to the one reported for SOI MOSFETs. The effect is explained using a new analytical model which is possible to implement in a circuit simulator.
    ABSTRACT
    ABSTRACT
    A novel fabrication process for low-temperature (
    ABSTRACT Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 m) LDD regions, have been analyzed by using... more
    ABSTRACT Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 m) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to ex- plain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices.
    Applications of polycrystalline silicon (polysilicon) thin film transistors (TFTs) to active matrix organic light emitting displays require further performance improvement. The biggest leverage in circuit performance can be obtained by... more
    Applications of polycrystalline silicon (polysilicon) thin film transistors (TFTs) to active matrix organic light emitting displays require further performance improvement. The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6μm to 1μm, or less. However, short channel effects and hot-carrier induced instability in scaled down conventional self-aligned polysilicon TFTs can substantially degrade the device characteristics. To reduce these effects and allow proper operation of the circuits, drain field relief architectures have to be introduced. In this work we show that a fully self-aligned gate overlapped lightly doped drain (LDD) structure, with submicron LDD regions, can provide an excellent solution, allowing effective short channel effect control and improved electrical stability.
    ABSTRACT Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics.... more
    ABSTRACT Experimental measurements and full-2D numerical simulations show that velocity saturation effects in polysilicon thin-film transistor (TFTs) cannot be neglected in order to obtain a precise modelling of output characteristics. Since full-2D numerical simulations are time consuming and unpractical for circuit simulations, we have developed a new quasi-2D model, that takes into account both velocity saturation effects and the presence of a longitudinal electric field in the Poisson's equation, and includes the effect of parasitic bipolar transistor (PBT) action to reproduce kink effect. The agreement of the quasi-2D model with experimental data from p-channel polysilicon TFTs is very satisfactory even for short channel device, and the presence of a velocity-saturated region with a nearly constant free carrier concentration is reproduced without introducing further assumptions.
    In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by... more
    In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current
    ABSTRACT Polycrystalline silicon thin-film transistors (TFTs) have been fabricated by using a combined fast solid phase crystallization (SPC) process followed by excimer laser annealing (ELA). The electrical characteristics of the... more
    ABSTRACT Polycrystalline silicon thin-film transistors (TFTs) have been fabricated by using a combined fast solid phase crystallization (SPC) process followed by excimer laser annealing (ELA). The electrical characteristics of the devices, after post-hydrogenation, show average field effect mobilities > 100 cm(2)/Vs and better noise performance, if compared to conventional SPC-polysilicon TFTs. A main advantage of the presented technique is the reduced sensitivity of the device performances to the energy density used during ELA.
    The application of bias-stress with high source-drain voltage and negative gate voltage (transistor in off-status) produces a marked reduction in the off-current as well as a transconductance degradation. These effects have been explained... more
    The application of bias-stress with high source-drain voltage and negative gate voltage (transistor in off-status) produces a marked reduction in the off-current as well as a transconductance degradation. These effects have been explained in terms of hotholes injection into the gate insulator and formation of interface states near the drain.

    And 26 more