100N50F FDL Mosfet N PDF
100N50F FDL Mosfet N PDF
100N50F FDL Mosfet N PDF
May 2009
UniFETTM
FDL100N50F
N-Channel MOSFET,FRFET
500V, 100A, 0.055
Features Description
RDS(on) = 0.043 ( Typ.)@ VGS = 10V, ID = 50A These N-Channel enhancement mode power field effect
transistors are produced using Fairchilds proprietary, planar
Low gate charge ( Typ. 238nC) stripe, DMOS technology.
Low Crss ( Typ. 64pF) This advanced technology has been especially tailored to
Fast switching minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
100% avalanche tested and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
Improved dv/dt capability
correction.
RoHS Compliant
TO-264
G D S FDL Series
S
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250A, VGS = 0V, TC = 25oC 500 - - V
BVDSS Breakdown Voltage Temperature
ID = 250A, Referenced to 25oC - 0.5 - V/oC
TJ Coefficient
VDS = 500V, VGS = 0V - - 10
IDSS Zero Gate Voltage Drain Current A
VDS = 400V, TC = 125oC - - 100
IGSS Gate to Body Leakage Current VGS = 30V, VDS = 0V - - 100 nA
On Characteristics
VGS(th) Gate Threshold Voltage VGS = VDS, ID = 250A 3.0 - 5.0 V
RDS(on) Static Drain to Source On Resistance VGS = 10V, ID = 50A - 0.043 0.055
gFS Forward Transconductance VDS = 20V, ID = 50A (Note 4) - 95 - S
Dynamic Characteristics
Ciss Input Capacitance - 12000 - pF
VDS = 25V, VGS = 0V
Coss Output Capacitance - 1700 - pF
f = 1MHz
Crss Reverse Transfer Capacitance - 64 - pF
Qg(tot) Total Gate Charge at 10V - 238 - nC
VDD = 400V, ID = 50A
Qgs Gate to Source Gate Charge - 74 - nC
VGS = 10V
Qgd Gate to Drain Miller Charge - 95 - nC
Switching Characteristics
td(on) Turn-On Delay Time - 63 - ns
tr Turn-On Rise Time VDD = 250V, ID = 50A - 186 - ns
RG = 4.7
td(off) Turn-Off Delay Time - 202 - ns
tf Turn-Off Fall Time - 105 - ns
Notes:
1. Repetitive Rating: Pulse width limited by maximum junction temperature
2. L = 1mH, IAS = 100A, VDD = 50V, RG = 25, Starting TJ = 25C
3. ISD 100A, di/dt 200A/s, VDD BVDSS, Starting TJ = 25C
4. Pulse Test: Pulse width 300s, Duty Cycle 2%
5. Essentially Independent of Operating Temperature Typical Characteristics
*Notes: *Notes:
1. 250s Pulse Test 1. VDS = 20V
1 o
2. TC = 25 C 2. 250s Pulse Test
0.5 1
0.1 1 10 4 6 8 10
VDS, Drain-Source Voltage[V] VGS, Gate-Source Voltage[V]
100
Drain-Source On-Resistance
0.06 o
150 C
RDS(ON) [],
VGS = 10V
0.05
o
25 C
VGS = 20V 10
0.04
*Notes:
1. VGS = 0V
o
*Note: TC = 25 C 2. 250s Pulse Test
0.03 1
0 50 100 150 200 250 0.0 0.5 1.0 1.5
ID, Drain Current [A] VSD, Body Diode Forward Voltage [V]
20000 *Note:
Capacitances [pF]
1. VGS = 0V 6
2. f = 1MHz
15000 Ciss
4
10000
Crss
2
5000
*Note: ID = 50A
0 0
10
-1
1 10 30 0 50 100 150 200 250
VDS, Drain-Source Voltage [V] Qg, Total Gate Charge [nC]
2.5
Drain-Source On-Resistance
1.1
BVDSS, [Normalized]
RDS(on), [Normalized]
2.0
1.0 1.5
1.0
0.9
*Notes: *Notes:
0.5
1. VGS = 0V 1. VGS = 10V
2. ID = 1mA 2. ID = 50A
0.8 0.0
-100 -50 0 50 100 150 200 -100 -50 0 50 100 150 200
o o
TJ, Junction Temperature [ C] TJ, Junction Temperature [ C]
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
1000 120
30s
100s
100
100 1ms
ID, Drain Current [A]
10ms
DC
ID, Drain Current [A]
80
10
60
Operation in This Area
1 is Limited by R DS(on)
40
*Notes:
o
0.1 1. TC = 25 C
20
o
2. TJ = 150 C
3. Single Pulse
0.01 0
1 10 100 1000 25 50 75 100 125 150
o
VDS, Drain-Source Voltage [V] TC, Case Temperature [ C]
0.1
Thermal Response [ZJC]
0.5
0.01 0.2
0.1
PDM
0.05
t1
0.02 t2
0.001 0.01 *Notes:
Single pulse o
1. ZJC(t) = 0.05 C/W Max.
2. Duty Factor, D= t1/t2
3. TJM - TC = PDM * ZJC(t)
0.0001
-5 -4 -3 -2 -1
10 10 10 10 10 1
Rectangular Pulse Duration [sec]
DUT +
V DS
I SD
L
D r iv e r
R G
S am e T ype
as DUT V DD
V GS d v / d t c o n t r o lle d b y R G
I S D c o n t r o lle d b y p u ls e p e r io d
G a t e P u ls e W id t h
V GS D = --------------------------
G a t e P u ls e P e r io d 10V
( D r iv e r )
I F M , B o d y D io d e F o r w a r d C u r r e n t
I SD
( DUT ) d i/d t
IR M
B o d y D io d e R e v e r s e C u r r e n t
V DS
( DUT ) B o d y D io d e R e c o v e r y d v / d t
V SD V DD
B o d y D io d e
F o r w a r d V o lta g e D r o p
Dimensions in Millimeters
Sync-Lock VisualMax
FlashWriter * PDP SPM
* XS
FPS Power-SPM
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILDS WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.