LNK3604D TL v2
LNK3604D TL v2
LNK3604D TL v2
LinkSwitch-XT2 Family
Energy Efficient, Low Power Off-Line Switcher IC
With Integrated System Level Protection
Product Highlights
+ DC +
Easy to Design OUT
• Lowest component count switcher solution
• Selectable device current limit
• Fully integrated auto-restart for short-circuit and open-loop
protection Wide Range LinkSwitch-XT2
• Optional self-biased supply High-Voltage D
• Frequency jittering greatly reduces EMI DC Input FB
• Meets HV creepage requirements between DRAIN and all other pins BP/M
both on the PCB and at the package
S
• Pin-out simplifies PCB heat sinking
Features Superior to Linear/RCC
• Output overvoltage protection (OVP) Flyback converter with LNK3604 PI-8118-102516
• Input overvoltage line protection (OVL)
Figure 1. Typical Application with LinkSwitch-XT2.
• Hysteretic over-temperature protection (OTP)
• Extended creepage between DRAIN pin and all other pins improves
field reliability
• 725 V MOSFET rating series for excellent surge withstand
• 900 V MOSFET rating series for industrial design or extra safety
margin
• Extremely low component count enhances reliability
• Allows single-sided PCB and full SMD manufacturability
BYPASS DRAIN
(BP/M) (D)
REGULATOR
5.0 V
-
VI
LIMIT
JITTER
CLOCK THERMAL
SHUTDOWN
DCMAX
OSCILLATOR
S Q
FEEDBACK
(FB) R Q
2.0 V -VT
LEADING
EDGE
BLANKING
OVP
DETECT
SOURCE
(S)
PI-7879-102318
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LNK3604, LNK3694 & 3696
600
LinkSwitch-XT2 Functional Description
PI-4047-090718
LinkSwitch-XT2 IC combines a high-voltage power MOSFET switch 500 V
with a power supply controller in one device. Unlike conventional DRAIN
PWM (pulse width modulator) controllers, LinkSwitch-XT2 ICs use 400
a simple ON/OFF control to regulate the output voltage. The
Voltage (V)
LinkSwitch-XT2 controller consists of an oscillator, feedback (sense 300
and logic) circuit, 5.0 V regulator, BYPASS pin undervoltage circuit,
over-temperature protection, line and output overvoltage protection, 200
frequency jittering, current limit circuit, leading edge blanking and a
high-voltage power MOSFET. The LinkSwitch-XT2 incorporates 100
additional circuitry for auto-restart.
0
Oscillator 136.5 kHz
The typical oscillator frequency is internally set to an average of 127.5 kHz
fOSC (66 kHz or 132 kHz). Two signals are generated from the
oscillator: the maximum duty cycle signal (DCMAX) and the clock signal
that indicates the beginning of each cycle. 0 5 10
Time (µs)
The LinkSwitch-XT2 oscillator incorporates circuitry that introduces a
small amount of frequency jitter, typically 4 kHz peak-to-peak (LNK369X) Figure 5a. Frequency Jitter (LNK3604).
and 8 kHz peak-to-peak (LNK3604), to minimize EMI emission. The
modulation rate of the frequency jitter is set to 1 kHz to optimize EMI
reduction for both average and quasi-peak emissions. The frequency 600
PI-3660-091018
jitter should be measured with the oscilloscope triggered at the falling
edge of the DRAIN waveform. The waveform in Figure 5 illustrates 500 V
the frequency jitter of the LinkSwitch-XT2 IC. DRAIN
400
Feedback Input Circuit
Voltage (V)
The feedback input circuit at the FEEDBACK pin consists of a low 300
impedance source follower output set at VFB (2.0 V). When the
current delivered into this pin exceeds IFB (49 μA), a low logic level 200
(disable) is generated at the output of the feedback circuit. This
output is sampled at the beginning of each cycle on the rising edge of 100
the clock signal. If high, the power MOSFET is turned on for that
cycle (enabled), otherwise the power MOSFET remains off (disabled). 0
The sampling is done only at the beginning of each cycle. Subse- 68 kHz
quent changes in the FEEDBACK pin voltage or current during the 64 kHz
remainder of the cycle do not impact the MOSFET enable/disable
status. If a current greater than IFB(SD) is injected into the FEEDBACK
pin while the power MOSFET is enabled for at least two consecutive 0 10 20
cycles the part will stop switching and enter auto-restart off-time. Time (µs)
Normal switching resumes after the auto-restart off-time expires.
This shutdown function allows implementing line overvoltage Figure 5b. Frequency Jitter (LNK369X).
protection (see Figure 7). The current into the FEEDBACK pin should
be limited to less than 1.2 mA.
BYPASS Pin Undervoltage
5.0 V Regulator and 5.2 V Shunt Voltage Clamp
The BYPASS pin undervoltage circuitry disables the power MOSFET
The 5.0 V regulator charges the bypass capacitor connected to the
when the BYPASS pin voltage drops below VBP–VBP(H) (approximately
BYPASS pin to VBP by drawing a current from the voltage on the
4.5 V). Once the BYPASS pin voltage drops below this threshold, it
DRAIN, whenever the power MOSFET is off. The BYPASS pin is the
must rise back to VBP to enable (turn-on) the power MOSFET.
internal supply voltage node for the LinkSwitch-XT2 IC. When the
power MOSFET is on, the LinkSwitch-XT2 IC runs off of the energy Over-Temperature Protection
stored in the bypass capacitor. Extremely low power consumption of The thermal shutdown circuitry senses the die temperature. The
the internal circuitry allows the LinkSwitch-XT2 IC to operate threshold is set at TSD (142 °C typical) with a 75 °C (TSD(H)) hyster-
continuously from the current drawn from the DRAIN pin. A bypass esis. When the die temperature rises above TSD the power MOSFET is
capacitor value of 0.1 μF is sufficient for both high frequency disabled and remains disabled until the die temperature falls to
decoupling and energy storage. TSD –TSD(H), at which point it is re-enabled.
In addition, there is a shunt regulator clamping the BYPASS pin at Current Limit
VBP(SHUNT) (5.2 V) when current is provided to the BYPASS pin through The current limit circuit senses the current in the power MOSFET.
an external resistor. This facilitates powering of LinkSwitch-XT2 When this current exceeds the internal threshold (ILIMIT), the power
externally through a bias winding to decrease the no-load consump- MOSFET is turned off for the remainder of that cycle. The leading
tion to about 10 mW (flyback). The device stops switching instantly edge blanking circuit inhibits the current limit comparator for a short
and enters auto-restart when a current ≥IBP(SD) is delivered into the time (tLEB) after the power MOSFET is turned on. This leading edge
BYPASS pin. Adding an external Zener diode from the output voltage blanking time has been set so that current spikes caused by capaci-
to the BYPASS pin allows implementing an hysteretic OVP function tance and rectifier reverse recovery time will not cause premature
(see Figure 6). The current into the BYPASS pin should be limited to termination of the switching pulse. Current limit can be selected
less than 16 mA.
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using the BYPASS pin capacitor (0.1 μF for normal current limit / 1 μF Zener diode. The resistor in series with the OVP Zener diode also
for reduced current limit). LinkSwitch-XT2 ICs select between normal limits the maximum current into the BYPASS pin. The current should
and reduced current limit at power-up prior to switching. be limited to less than 16 mA.
Auto-Restart During a fault condition resulting from loss of feedback, the output
In the event of a fault condition such as output overload, output voltage will rapidly rise above the nominal voltage. A voltage at the
short, or an open-loop condition, LinkSwitch-XT2 ICs enter into output that exceeds the sum of the voltage rating of the Zener diode
auto-restart operation. An internal counter clocked by the oscillator connected from the output to the BYPASS pin and bypass voltage,
gets reset every time the FEEDBACK pin is pulled high. If the will cause a current in excess of IBP(SD) injected into the BYPASS pin,
FEEDBACK pin is not pulled high for t AR(ON) (50 ms), the power which will trigger the auto-restart and protect the power supply from
MOSFET switching is disabled for a time equal to the auto-restart overvoltage.
off-time. The first time a fault is asserted the off-time is 150 ms
Line Overvoltage Protection
(t AR(OFF) First Off Period). If the fault condition persists, subsequent
In a flyback converter the LinkSwitch-XT2 IC senses indirectly the DC
off-times are 1500 ms long (t AR(OFF) Subsequent Periods). The
bus overvoltage condition during the power MOSFET on-time by
auto-restart alternately enables and disables the switching of the
monitoring the current flowing into the FEEDBACK pin. Figure 7
power MOSFET until the fault condition is removed. The auto-restart
shows one possible circuit implementation. During the power
counter is gated by the switch oscillator.
MOSFET on-time, the voltage across the secondary winding is propor-
Hysteretic Output Overvoltage Protection tional to the voltage across the input winding. The current flowing
The output overvoltage protection provided by the LinkSwitch-XT2 IC through transistor Q3 is therefore representing VBUS. Indirect line
uses auto-restart that is triggered by a current >IBP(SD) into the sensing minimizes power dissipation and is used for line OV protection.
BYPASS pin. In addition to an internal filter, the BYPASS pin capacitor The LinkSwitch-XT2 IC will go into auto-restart mode if the FEEDBACK
forms an external filter providing noise immunity from inadvertent pin current exceeds the line overvoltage threshold current IFB(SD) for at
triggering. For the bypass capacitor to be effective as a high frequency least 2 consecutive switching cycles.
filter, the capacitor should be located as close as possible to the
In order to have accurate line OV threshold voltage and also for good
SOURCE pin and BYPASS pins of the device.
efficiency, regulation performance and stability, the transformer
The OVP function can be realized by connecting a Zener diode from leakage inductance should be minimized. Low leakage will minimize
the output supply to the BYPASS pin. The circuit example shown in ringing on the secondary winding which can introduce an error in the
Figure 6 describes simple method for implementing the output line OV sampling. In some designs, a RC snubber across the rectifier
overvoltage protection. Adding additional filtering can be achieved by diode may be needed to damp the ringing at the secondary winding
inserting a low value (10 Ω to 47 Ω) resistor in series with the OVP when line voltage is sampled.
T1
+
VO
+
VBUS
D VOV = VBP + VDOVP
FB
LinkSwitch-XT2 BP
RBP
S CBP
DOVP
PI-8119-112816
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LNK3604, LNK3694 & 3696
T1
+
R3* VO
n:1
VR3
PI-8120-102616
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LNK3604, LNK3694 & 3696
Applications Example
C5
1 nF R4
L2 50 V 16 Ω
C6 C7
Ferrite Bead T1 470 µF 470 µF
(3.5 × 4.45 mm) EE13 10 V 10 V 5 V, 500 mA
5 6
D3 TP3
SS24-E3/52T
4 10
RTN
1
TP4
BR1
B10S-G C3
1000 V D1
RF1 DFLR1200-7 22 µF
8.2 Ω 2 200 V 25 V
L 2W VO
R5
TP1 C1 C2 3.57 kΩ
3.3 µF 3.3 µF 1% R8
R2 R7
85 - 265 400 V 400 V 20 kΩ 200 Ω
1/8 w 4.7 kΩ
VAC 1% 1/8 w
N LinkSwitch-XT2 Q2
MMST4403-7-F
U1
TP2 LNK3604D
D FB
FB
VR2
BP/M MMSZ4687T1G
RTN 4.3 V
S R6
C4 2.49 kΩ
1 µF 1% <10 mW no-load input power can be
L1 50 V achieved with Zener diode feedback
1 mH
PI-8148-102716
The rectified and filtered input voltage is applied to the primary The LinkSwitch-XT2 ICs can be completely self-powered from the
winding of T1. The other side of the primary is driven by the integrated DRAIN pin, requiring only a small ceramic capacitor C3 connected to
power MOSFET in U1. No primary clamp is required as the low value the BYPASS pin. Resistor R2 supplies the BYPASS pin externally from
and tight tolerance of the LNK3604D IC’s internal current limit allows the auxiliary winding for significantly lower no-load input power and
the primary winding capacitance of the transformer and drain-source increased efficiency over all load conditions. To achieve lowest
capacitance of the power MOSFET in the LNK3604D to provide no-load power consumption, the current fed into the BYPASS pin
adequate clamping of the leakage inductance drain voltage spike. should be slightly higher than 120 mA. For the best full load efficiency
The secondary of the flyback transformer T1 is rectified by D3, a and thermal performance, the current fed into the BYPASS pin should
Schottky diode, and filtered by C6, C7, low ESR capacitor. The output be slightly higher than 257 mA.
voltage is sensed via resistor divider R5 and R6. Output voltage is
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LNK3604, LNK3694 & 3696
Key Application Considerations **VOR is the secondary output plus output diode forward voltage
drop that is reflected to the primary via the turns ratio of the
LinkSwitch-XT2 Design Considerations transformer during the diode conduction time. The VOR adds to the
Output Power Table DC bus voltage and the leakage spike to determine the peak drain
voltage.
The data sheet maximum output power table (Table 1) represents the
maximum practical continuous output power level that can be Audible Noise
obtained under the following assumed conditions: The cycle skipping mode of operation used in LinkSwitch-XT2 ICs can
generate audio frequency components in the transformer. To limit
1. The minimum DC input voltage is 90 V or higher for 85 VAC input,
this audible noise generation, the transformer should be designed
or 240 V or higher for 230 VAC input or 115 VAC with a voltage
such that the peak core flux density is below 1500 gauss (150 mT).
doubler. The value of the input capacitance should be large
Following this guideline and using the standard transformer produc-
enough to meet these criteria for AC input designs.
tion technique of dip varnishing practically eliminates audible noise.
2. Secondary output of 6 V with a fast PN rectifier diode.
Vacuum impregnation of the transformer should not be used due to
3. Assumed efficiency of 70%.
the high primary capacitance and increased losses that result. Higher
4. Voltage only output (no secondary-side constant current circuit).
flux densities are possible, however careful evaluation of the audible
5. A primary clamp (RCD or Zener) is used.
noise performance should be made using production transformer
6. The part is board mounted with SOURCE pins soldered to a
samples before approving the design.
sufficient area of copper to keep the SOURCE pin temperature at
or below 100 °C. Ceramic capacitors that use dielectrics, such as Z5U, when used in
7. Ambient temperature of 50 °C for open frame designs and an clamp circuits may also generate audio noise. If this is the case, try
internal enclosure temperature of 60 °C for adapter designs. replacing them with a capacitor having a different dielectric or
construction, for example a film type.
Discontinuous mode operation (KP > 1) is recommended for LNK3604.
Below a value of 1, KP is the ratio of ripple to peak primary current. LinkSwitch-XT2 Layout Considerations
Above a value of 1, KP is the ratio of primary power MOSFET
OFF-time to the secondary diode conduction time. Due to the flux See Figures 9, 10 and 11 for a recommended circuit board layout for
density requirements described below, typically a LinkSwitch-XT2 LinkSwitch-XT2 (D, P and G packages).
design will be discontinuous, which also has the benefits of allowing Single Point Grounding
fast (instead of ultrafast) output diodes and reducing EMI. Use a single point ground connection from the input filter capacitor to
Clampless Designs the area of copper connected to the SOURCE pins.
Clampless designs rely solely on the drain node capacitance to limit Bypass Capacitor CBP
the leakage inductance induced peak drain-to-source voltage. The BYPASS pin capacitor should be located as near as possible to
Therefore, the maximum AC input line voltage, the value of VOR, the the BYPASS and SOURCE pins.
leakage inductance energy, a function of leakage inductance and
peak primary current, and the primary winding capacitance determine Primary Loop Area
the peak drain voltage. With no significant dissipative element The area of the primary loop that connects the input filter capacitor,
present, as is the case with an external clamp, the longer duration of transformer primary and LinkSwitch-XT2 IC together should be kept
the leakage inductance ringing can increase EMI. as small as possible.
The following requirements are recommended for a universal input or Primary Clamp Circuit
230 VAC only clampless design: A clamp is used to limit peak voltage on the DRAIN pin at turn-off.
This can be achieved by using an RCD clamp or a Zener (~200 V) and
1. A clampless design should only be used for PO ≤ 2.5 W, using the diode clamp across the primary winding. In all cases, to minimize
reduced current limit mode (CBP = 1 mF) and a VOR** ≤ 90 V. EMI, care should be taken to minimize the circuit path from the clamp
2. For designs where PO ≤ 2 W, a two-layer primary should be used components to the transformer and LinkSwitch-XT2 IC.
to ensure adequate primary intra-winding capacitance in the
range of 25 pF to 50 pF. Thermal Considerations
3. For designs where 2 < PO ≤ 2.5 W, a bias winding should be The copper area underneath the LinkSwitch-XT2 IC acts not only as a
added to the transformer using a standard recovery rectifier single point ground, but also as a heat sink. As this area is connected
diode to act as a clamp. This bias winding may also be used to to the quiet source node, it should be maximized for good heat
externally power the device by connecting a resistor from the sinking of LinkSwitch-XT2 IC. The same applies to the cathode of the
bias-winding capacitor to the BYPASS pin. This inhibits the output diode.
internal high-voltage current source, reducing device dissipation
Y Capacitor
and no-load consumption.
Y capacitor is generally not used for this power level. If you want to
4. For designs where PO > 2.5 W clampless designs are not practical
use, the placement of the Y type capacitor should be directly from
and an external RCD or Zener clamp should be used.
the primary input filter capacitor positive terminal to the common/
5. Ensure that worst-case high line, peak drain voltage is below the
return terminal of the transformer secondary. Such a placement will
BVDSS specification of the internal power MOSFET and ideally
route high magnitude common mode surge currents away from the
< VDSS × 0.9 to allow margin for design variation.
LinkSwitch-XT2 device. Note that if an input pi (C, L, C) EMI filter is
†For 110 VAC only input designs it may be possible to extend the used, then the inductor in the filter should be placed between the
power range of clampless designs to include the standard current negative terminals of the input filter capacitors.
limit mode. However, the increased leakage ringing may degrade
EMI performance.
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LNK3604, LNK3694 & 3696
Figure 9. Recommended Printed Circuit Layout for LinkSwitch-XT2 using D Package in a Flyback Converter Configuration (Bottom Left, Top Right).
Figure 10. Recommended Printed Circuit Layout for LinkSwitch-XT2 using G Package in a Flyback Converter Configuration (Bottom Left, Top Right).
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Figure 11. Recommended Printed Circuit Layout for LinkSwitch-XT2 using P Package in a Flyback Converter Configuration (Bottom Left, Top Right).
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LNK3604, LNK3694 & 3696
Thermal Resistance
Thermal Resistance: P or G Package: Notes:
(qJA) ..................................... 70 °C/W(2); 60 °C/W(3) 1. Measured on pin 8 (SOURCE) close to plastic interface.
(qJC)(1) ....................................................... 11 °C/W 2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
D Package: 3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
(qJA) ................................... 100 °C/W(2); 80 °C/W(3)
(qJC)(1) ....................................................... 30 °C/W
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 12 Min Typ Max Units
(Unless Otherwise Specified)
Control Functions
LNK3604 66
Maximum Duty Cycle DCMAX S2 Open %
LNK3694 / LNK3696 65
VFB = 2.1 V
IS1 75 mA
(MOSFET Not Switching) See Note A
DRAIN Pin LNK3604 150
Supply Current FEEDBACK Open
IS2 (MOSFET Switching) LNK3694 120 mA
See Notes A, B
LNK3696 205
VBP = 0 V
ICH1 -11 -7 -3
BYPASS Pin TJ = 25 °C
mA
Charge Current VBP = 4 V
ICH2 -7.5 -5 -2.5
TJ = 25 °C
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LNK3604, LNK3694 & 3696
Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 12 Min Typ Max Units
(Unless Otherwise Specified)
BYPASS Pin
VBP(SHUNT) IBP = 2 mA 4.95 5.2 5.45 V
Shunt Voltage
BYPASS Pin
VBP(H) 0.47 V
Voltage Hysteresis
BYPASS Pin
IBP(SC) See Note C 55 mA
Supply Current
Circuit Protection
di/dt = 65 mA/ms
240 257 275
TJ = 25 °C
LNK3604
di/dt = 415 mA/ms
278 317 356
TJ = 25 °C
di/dt = 33 mA/ms
Standard Current Limit 240.5 260 279.5
TJ = 25 °C
(CBP = 0.1 mF, ILIMIT LNK3694 mA
See Note D, H) di/dt = 210 mA/ms
265.5 287 308.5
TJ = 25 °C
di/dt = 60 mA/ms
446 482 518
TJ = 25 °C
LNK3696
di/dt = 385 mA/ms
496 535 575
TJ = 25 °C
di/dt = 65 mA/ms
180 205 230
TJ = 25 °C
LNK3604
di/dt = 415 mA/ms
227 258 289
TJ = 25 °C
di/dt = 33 mA/ms
Reduced Current Limit 189 205 220
TJ = 25 °C
(CBP = 1 mF, ILIMIT(RED) LNK3694 mA
See Note D, H) di/dt = 210 mA/ms
212 230 247
TJ = 25 °C
di/dt = 60 mA/ms
347 375 404
TJ = 25 °C
LNK3696
di/dt = 385 mA/ms
388.5 420 451.5
TJ = 25 °C
Thermal Shutdown
TSD See Note F 135 142 150 °C
Temperature
Thermal Shutdown
TSD(H) See Note F 75 °C
Hysteresis
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Conditions
SOURCE = 0 V; TJ = -40 to 125 °C
Parameter Symbol See Figure 12 Min Typ Max Units
(Unless Otherwise Specified)
Output
TJ = 25 °C 24 27.6
LNK3604
ID = 25 mA TJ = 100 °C 38 44.2
TJ = 25 °C 17 19.6
ON-State LNK3694
RDS(ON) W
Resistance ID = 86 mA TJ = 100 °C 27 31
TJ = 25 °C 5.3 6.1
LNK3696
ID = 163 mA TJ = 100 °C 8.4 9.7
LNK3604 725
VBP = 5.4 V, VFB ≥2.1 V,
Breakdown Voltage BVDSS V
TJ = 25 °C LNK3694 / LNK3696 900
DRAIN Pin
TJ = 25 °C 50 V
Supply Voltage
Auto-Restart TJ = 25 °C
t AR(ON) 50 ms
ON-Time See Note G
Auto-Restart
DC AR Subsequent Periods 3 %
Duty Cycle
Notes:
A. Total current consumption is the sum of IS1 and IDSS when FEEDBACK pin voltage is = 2.1 V (MOSFET not switching) and the sum of IS2 and
IDSS when FEEDBACK pin is shorted to SOURCE (MOSFET switching).
B. Since the output MOSFET is switching, it is difficult to isolate the switching current from the supply current at the DRAIN. An alternative is
to measure the BYPASS pin current at 5.1 V.
C. This current is only intended to supply an optional optocoupler connected between the BYPASS and FEEDBACK pins and not any other
external circuitry.
D. For current limit at other di/dt values, refer to Figures 22, 23, 32 and 33.
E. This parameter is guaranteed by design.
F. This parameter is derived from characterization.
G. Auto-restart on time has the same temperature characteristics as the oscillator (inversely proportional to frequency).
H. The BP/M capacitor value tolerance should be equal or better than indicated below across the ambient temperature range of the target
application.
I. Measured using circuit in Figure 14 with 50 W drain pull-up. The width of the drain pulse is measured as the time from VFALL = 42 V to
VRISE = 40 V (VDR = 50 V).
Tolerance Relative to
Nominal BP/M Pin Minimal Capacitor Value
Capacitor Value
Min Max
0.1 mF -60% +100%
1 mF -50% +100%
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LNK3604, LNK3694 & 3696
470 kΩ
470 Ω
5W
S2
S1
FB
BP/M
50 V 0.1 µF 50 V
S
S
PI-7850-033016
50 Ω FB BP/M
D S
0.1 µF
VDR
PI-7899-031816
Figure 13. LinkSwitch-XT2 Duty Cycle Measurement. Figure 14. LinkSwitch-XT2 Minimum On-Time Test Circuit.
T1 T2
VDR
VFALL VRISE
TON_MIN = T2 - T1
0V
PI-7898-031716
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LNK3604, LNK3694 & 3696
1.1 1.4
PI-8814-090618
PI-8813-090618
1.2
1.0
0.8
LNK3604 LNK3604
1.0 LNK369X
0.6
0.4
0.2
0.9 0
-50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800
Junction Temperature (°C) Drain Voltage VDS (V)
Figure 16. Breakdown vs. Temperature. Figure 17. Maximum Allowable Drain Current vs. Drain Voltage.
0.6
1000
PI-8815-090618
PI-8816-090618
0.5
Drain Current IDS (A)
LNK3604
0.2 10
0.1
0 1
0 2 4 6 8 10 12 14 16 18 20 0 50 100 150 200 250 300 350 400 450
Drain Voltage VDS (V) Drain Voltage (V)
Figure 18. Output Characteristics. Figure 19. COSS vs. Drain Voltage.
1.0 1.0
Reduced Current Limit
(Normalized to 25 °C)
(Normalized to 25 °C)
Default Current Limit
0.8 0.8
Normalized ILIM = 1 Normalized ILIM = 1
Scaling Factors: Scaling Factors:
0.6 0.6
LNK3604 65 mA/µs 257 mA LNK3604 65 mA/µs 205 mA
LNK3604 415 mA/µs 317 mA LNK3604 415 mA/µs 258 mA
0.4 0.4
0.2 0.2
0.0 0.0
-50 0 50 100 150 -50 0 50 100 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 20. Default Current Limit vs. Junction Temperature. Figure 21. Reduced Current Limit vs. Junction Temperature.
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1.4 1.4
PI-8151-102616
PI-8150-102616
1.2
1.0 1.0
0.8 0.8
Scaling Normalized Normalized Scaling Normalized Normalized
0.6 Factors: di/dt = 1 ILIM = 1 0.6 Factors: di/dt = 1 ILIM = 1
LNK3604 65 mA/µs 257 mA LNK3604 65 mA/µs 205 mA
0.4 0.4
0.2 0.2
0.0 0.0
1 3 3 4 5 6 1 3 3 4 5 6
Normalized di/dt Normalized di/dt
Figure 22. Default Current Limit vs. di/dt. Figure 23. Reduced Current Limit vs. di/dt.
1.2
PI-8817-090618
1.0
(Normalized to 25 °C)
Output Frequency
LNK3604
0.8
0.6
0.4
0.2
0.0
-50 0 50 100 150
Junction Temperature (°C)
Figure 24. Output Frequency vs. Junction Temperature.
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LNK3604, LNK3694 & 3696
1.2 0.6
PI-8802-090518
PI-8803-090518
Scaling Factors: Scaling Factors:
LNK3694 1.0 LNK3694 1.0
1.0 LNK3696 3.3 0.5 LNK3696 3.3
Drain Current IDS (A)
0.8 0.4
100 °C
0.6 0.3
0.4 0.2
0.2 0.1
0 0
0 125 250 375 500 625 750 875 1000 0 5 10 15 20
Drain Voltage VDS (V) Drain Voltage VDS (V)
Figure 25. Maximum Allowable Drain Current vs. Drain Voltage. Figure 26. Output Characteristics.
1.2
PI-8805-090518
Scaling Factors:
LNK3694 1.0
LNK3696 3.3 1.0
Drain Capacitance (pF)
10 0.6
Normalized ILIM = 1
Scaling Factors:
0.4 LNK3694 33 mA/µs 260 mA
10 LNK3696 60 mA/µs 482 mA
0.2
1 0.0
0 100 200 300 400 500 -50 -30 -10 10 30 50 70 90 110 130 150
Drain Voltage (V) Junction Temperature (°C)
Figure 27. COSS vs. Drain Voltage. Figure 28. Default Current Limit vs. Junction Temperature.
Default Current Limit at High di/dt
1.2
PI-8806-090518
1.0
(Normalized to 25 °C)
0.8
0.6
Normalized ILIM = 1
Scaling Factors:
0.4 LNK3694 210 mA/µs 287 mA
LNK3696 385 mA/µs 535 mA
0.2
0.0
-50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature (°C)
Figure 29. Default Current Limit vs. Junction Temperature.
16
Rev. E 09/18 www.power.com
LNK3604, LNK3694 & 3696
1.2 1.2
PI-8807-090518
PI-8808-090518
1.0 1.0
(Normalized to 25 °C)
(Normalized to 25 °C)
0.8 0.8
0.6 0.6
Normalized ILIM = 1 Normalized ILIM = 1
Scaling Factors: Scaling Factors:
0.4 LNK3694 33 mA/µs 205 mA
0.4 LNK3694 210 mA/µs 230 mA
LNK3696 60 mA/µs 375 mA LNK3696 385 mA/µs 420 mA
0.2 0.2
0.0 0.0
-50 -30 -10 10 30 50 70 90 110 130 150 -50 -30 -10 10 30 50 70 90 110 130 150
Junction Temperature (°C) Junction Temperature (°C)
Figure 30. Reduced Current Limit vs. Junction Temperature. Figure 31. Reduced Current Limit vs. Junction Temperature.
Normalized Standard Current Limit
PI-8811-090618
1.0 1.0
0.8 0.8
0.6 0.6
Scaling Normalized Normalized Scaling Normalized Normalized
Factors: di/dt = 1 ILIM = 1 Factors: di/dt = 1 ILIM = 1
0.4 0.4
LNK3694 33 mA/µs 260 mA LNK3694 33 mA/µs 205 mA
LNK3696 60 mA/µs 482 mA LNK3696 60 mA/µs 375 mA
0.2 0.2
0.0 0.0
1 2 3 4 5 6 7 1 2 3 4 5 6 7
Normalized di/dt Normalized di/dt
Figure 32. Standard Current Limit vs. di/dt. Figure 33. Reduced Current Limit vs. di/dt.
1.2
PI-8809-090618
1.0
(Normalized to 25 °C)
LNK369X
Output Frequency
0.8
0.6
0.4
0.2
0.0
-50 0 50 100 150
Junction Temperature (°C)
Figure 34. Output Frequency vs. Junction Temperature.
17
www.power.com Rev. E 09/18
LNK3604, LNK3694 & 3696
PDIP-8C (P Package)
⊕ D S .004 (.10) Notes:
-E- 1. Package dimensions conform to JEDEC specification
MS-001-AB (Issue B 7/85) for standard dual-in-line (DIP)
package with .300 inch row spacing.
2. Controlling dimensions are inches. Millimeter sizes are
shown in parentheses.
.240 (6.10) 3. Dimensions shown do not include mold flash or other
.260 (6.60) protrusions. Mold flash or protrusions shall not exceed
.006 (.15) on any side.
4. Pin locations start with Pin 1, and continue counter-clock-
wise to Pin 8 when viewed from the top. The notch and/or
dimple are aids in locating Pin 1. Pin 3 is omitted.
Pin 1 5. Minimum metal to metal spacing at the package body for
the omitted lead location is .137 inch (3.48 mm).
.356 (9.05) 6. Lead width measured at package body.
-D-
.387 (9.83)
7. Lead spacing measured with the leads constrained to be
.057 (1.45) perpendicular to plane T.
.068 (1.73)
(NOTE 6)
.125 (3.18) .015 (.38)
.145 (3.68) MINIMUM
-T-
SEATING .008 (.20)
PLANE .118 (3.00) .015 (.38)
.140 (3.56)
SMD-8C (G Package)
Notes:
⊕ D S .004 (.10) .046 .060 .060 .046 1. Controlling dimensions are
inches. Millimeter sizes are
-E- shown in parentheses.
.080 2. Dimensions shown do not
include mold flash or other
protrusions. Mold flash or
.086 protrusions shall not exceed
.186 .006 (.15) on any side.
.372 (9.45) 3. Pin locations start with Pin 1,
.240 (6.10)
.388 (9.86) .286 .420 and continue counter-clock-
.260 (6.60)
⊕ E S .010 (.25) wise to Pin 8 when viewed
from the top. Pin 3 is omitted.
4. Minimum metal to metal
spacing at the package body
for the omitted lead location
is .137 inch (3.48 mm).
Pin 1 Pin 1 5. Lead width measured at
.137 (3.48) package body.
MINIMUM Solder Pad Dimensions 6. D and E are referenced
.100 (2.54) (BSC) datums on the package
body.
.356 (9.05)
-D-
.387 (9.83)
.057 (1.45)
.125 (3.18) .068 (1.73)
.145 (3.68) (NOTE 5)
.004 (.10)
.032 (.81) .048 (1.22)
.053 (1.35)
.009 (.23) .004 (.10) .036 (0.91) 0 °- 8°
.037 (.94)
.012 (.30) .044 (1.12) G08C
PI-4015-081716
18
Rev. E 09/18 www.power.com
LNK3604, LNK3694 & 3696
SO-8C (D Package)
0.10 (0.004) C A-B 2X
2 DETAIL A
4 B
4.90 (0.193) BSC
A 4
D
8 5
GAUGE
PLANE
SEATING
PLANE
2 3.90 (0.154) BSC 6.00 (0.236) BSC o
C 0-8
0.25 (0.010)
1.04 (0.041) REF
BSC
0.10 (0.004) C D
0.40 (0.016)
2X 1
Pin 1 ID 4 0.20 (0.008) C 1.27 (0.050)
1.27 (0.050) BSC 2X
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) M C A-B D
C 0.17 (0.007)
0.25 (0.010)
Reference
Solder Pad +
Dimensions
Notes:
1. JEDEC reference: MS-012.
2.00 (0.079) 4.90 (0.193) 2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
+ + + 5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
1.27 (0.050) 0.60 (0.024)
D07C PI-4526-012315
19
www.power.com Rev. E 09/18
LNK3604, LNK3694 & 3696
A
1630
LNK3604P C
3Z380J D
PI-8127-100516
A
1630
LNK3604D C
4D426E D
PI-8126-100516
20
Rev. E 09/18 www.power.com
LNK3604, LNK3694 & 3696
MSL Table
LNK3604P N/A
LNK3694P N/A
LNK3696P N/A
LNK3604G 4
LNK3694G 4
LNK3696G 4
LNK3604D 1
Latch-up at 125 °C EIA/JESD78 > ±100 mA or > 1.5 × VMAX on all pins
21
www.power.com Rev. E 09/18
Revision Notes Date
A Code B. 10/16
B Code S. 11/16
C Code A. 11/16
D Corrected DRAIN Pin Peak Current to match Figure 17 and Corrected Note 2 in Absolute Maximum Ratings. 01/06/17
D Corrected Notes 1 and 2 in Table 1, updated Figure 5 and Reference Designator on page 5. 01/16/17
E Added LNK3694 and LNK3696 parts. 09/18
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