research-article

Content-Aware Bit Shuffling for Maximizing PCM Endurance

Authors:

Il ParkAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 22, Issue 3

Article No.: 48, Pages 1 - 26

https://doi.org/10.1145/3017445

Published: 23 May 2017 Publication History

Abstract

Recently, phase change memory (PCM) has been emerging as a strong replacement for DRAM owing to its many advantages such as nonvolatility, high capacity, low leakage power, and so on. However, PCM is still restricted for use as main memory because of its limited write endurance. There have been many methods introduced to resolve the problem by either reducing or spreading out bit flips. Although many previous studies have significantly contributed to reducing bit flips, they still have the drawback that lower bits are flipped more often than higher bits because the lower bits frequently change their bit values. Also, interblock wear-leveling schemes are commonly employed for spreading out bit flips by shifting input data, but they increase the number of bit flips per write. In this article, we propose a noble content-aware bit shuffling (CABS) technique that minimizes bit flips and evenly distributes them to maximize the lifetime of PCM at the bit level. We also introduce two additional optimizations, namely, addition of an inversion bit and use of an XOR key, to further reduce bit flips. Moreover, CABS is capable of recovering from stuck-at faults by restricting the change in values of stuck-at cells. Experimental results showed that CABS outperformed the existing state-of-the-art methods in the aspect of PCM lifetime extension with minimal overhead. CABS achieved up to 48.5% enhanced lifetime compared to the data comparison write (DCW) method only with a few metadata bits. Moreover, CABS obtained approximately 9.7% of improved write throughput than DCW because it significantly reduced bit flips and evenly distributed them. Also, CABS reduced about 5.4% of write dynamic energy compared to DCW. Finally, we have also confirmed that CABS is fully applicable to BCH codes as it was able to reduce the maximum number of bit flips in metadata cells by 32.1%.

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Cited By

Chen YWu CChang YKuo T(2023)Energy Efficiency Enhancement of SCM-Based Systems: Write-Friendly CodingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320423142:5(1425-1437)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3204231
Mercier RKillian CKritikakou AHelen YChillet D(2022)BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults MitigationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310140641:7(2276-2289)Online publication date: Jul-2022
https://doi.org/10.1109/TCAD.2021.3101406
Rai STalawar B(2022)Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory SystemsIETE Technical Review10.1080/02564602.2022.212794540:4(498-520)Online publication date: 13-Oct-2022
https://doi.org/10.1080/02564602.2022.2127945
Show More Cited By

Index Terms

Content-Aware Bit Shuffling for Maximizing PCM Endurance
1. Hardware
  1. Emerging technologies
    1. Memory and dense storage
  2. Integrated circuits
    1. Semiconductor memory
      1. Non-volatile memory
2. Information systems
  1. Information storage systems
    1. Information storage technologies
      1. Storage class memory
        Phase change memory

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 22, Issue 3

July 2017

440 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3062395

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

Issue’s Table of Contents

Copyright © 2017 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 23 May 2017

Accepted: 01 November 2016

Revised: 01 October 2016

Received: 01 June 2016

Published in TODAES Volume 22, Issue 3

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Cited By

Chen YWu CChang YKuo T(2023)Energy Efficiency Enhancement of SCM-Based Systems: Write-Friendly CodingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.320423142:5(1425-1437)Online publication date: 1-May-2023
https://dl.acm.org/doi/10.1109/TCAD.2022.3204231
Mercier RKillian CKritikakou AHelen YChillet D(2022)BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults MitigationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.310140641:7(2276-2289)Online publication date: Jul-2022
https://doi.org/10.1109/TCAD.2021.3101406
Rai STalawar B(2022)Challenges in Design, Data Placement, Migration and Power-Performance Trade-offs in DRAM-NVM-based Hybrid Memory SystemsIETE Technical Review10.1080/02564602.2022.212794540:4(498-520)Online publication date: 13-Oct-2022
https://doi.org/10.1080/02564602.2022.2127945
Kulandai ARose JSchwarz T(2022)Gray counters for non-volatile memoriesMemories - Materials, Devices, Circuits and Systems10.1016/j.memori.2022.1000142(100014)Online publication date: Oct-2022
https://doi.org/10.1016/j.memori.2022.100014
Majumdar S(2021)LEnS: Lifetime Enhancement Coding Scheme for Non-volatile Memory Processors2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)10.1109/MWSCAS47672.2021.9531891(365-368)Online publication date: 9-Aug-2021
https://doi.org/10.1109/MWSCAS47672.2021.9531891
Mercier RKillian CKritikakou AHelen YChillet D(2020)Multiple Permanent Faults Mitigation Through Bit-Shuffling for Network-an-Chip Architecture2020 IEEE 38th International Conference on Computer Design (ICCD)10.1109/ICCD50377.2020.00046(205-212)Online publication date: Oct-2020
https://doi.org/10.1109/ICCD50377.2020.00046
Kulandai AJ SRose JSchwarz T(2020)Balanced Gray Codes for Reduction of Bit-Flips in Phase Change MemoriesModelling, Analysis, and Simulation of Computer and Telecommunication Systems10.1007/978-3-030-68110-4_11(159-171)Online publication date: 17-Nov-2020
https://dl.acm.org/doi/10.1007/978-3-030-68110-4_11
Bittman DAlvaro PLong DMiller EMerchant AWeatherspoon H(2019)Optimizing systems for byte-addressable NVM by reducing bit flippingProceedings of the 17th USENIX Conference on File and Storage Technologies10.5555/3323298.3323301(17-30)Online publication date: 25-Feb-2019
https://dl.acm.org/doi/10.5555/3323298.3323301
Namba KLombardi F(2019)Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)IEEE Transactions on Computers10.1109/TC.2018.286892868:2(301-306)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1109/TC.2018.2868928
Namba KLombardi F(2018)On Coding for Endurance Enhancement and Error Control of Phase Change Memories With Write Latency ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.276636226:2(230-238)Online publication date: 1-Feb-2018
https://dl.acm.org/doi/10.1109/TVLSI.2017.2766362
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