Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
research-article

Rapid Triggering Capability Using an Adaptive Overlay during FPGA Debug

Published: 06 December 2018 Publication History
  • Get Citation Alerts
  • Abstract

    Field Programmable Gate Array (FPGA) technology is rapidly gaining traction in a wide range of applications. Nonetheless, FPGAs still require long design and debug cycles. To debug hardware circuits, trace-based instrumentation is inserted into the design that enables capturing data during the circuit execution into on-chip memories for later offline analysis. Since on-chip memories are limited, a trigger circuitry is used to only record data related to specific events during the execution. However, during debugging, a circuit recompilation is required on modifying these instruments. This can be very slow, reducing debug productivity. In this article, we propose a non-intrusive and rapid triggering solution with a tailored overlay fabric and mapping algorithm that seeks to enable fast debug iterations without performing a recompilation. This overlay is specialized for small combinational and sequential circuits with a single output; such circuits are typical of common trigger functions. We present an adaptive strategy to construct the overlay fabric using spare FPGA resources at compile time. At debug time, our proposed trigger mapping algorithms adapt to this specialized overlay to rapidly implement combinational and sequential trigger circuits. Our results show that the overlay fabric can be reconfigured to map different triggering scenarios in less than 40s instead of recompiling the circuit during debug iterations, increasing debug productivity.

    References

    [1]
    Elias Ahmed and Jonathan Rose. 2004. The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. VLSI Syst. 12, 3 (2004), 288--298.
    [2]
    Amazon. 2016. Amazon EC2 F1 Instances: Run Customizable FPGAs in the AWS Cloud. Retrieved from https://aws.amazon.com/ec2/instance-types/f1/.
    [3]
    Ehab Anis and Nicola Nicolici. 2007. On using lossless compression of debug data in embedded logic analysis. In Proceedings of the International Test Conference. IEEE, 1--10.
    [4]
    Vaughn Betz, Jonathan Rose, and Alexander Marquardt (Eds.). 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic.
    [5]
    Marc Boule, Jean-Samuel Chenard, and Zeljko Zilic. 2007. Assertion checkers in verification, silicon debug and in-field diagnosis. In Proceedings of the International Symposium on Quality Electronic Design. IEEE, 613--620.
    [6]
    Alexander Brant and Guy G. F. Lemieux. 2012. ZUMA: An open FPGA overlay architecture. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, 93--96.
    [7]
    Nazanin Calagar, Stephen D. Brown, and Jason H. Anderson. 2014. Source-level debugging for FPGA high-level synthesis. In Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE, 1--8.
    [8]
    Jason Cong, Hui Huang, and Xin Yuan. 2005. Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ACM Trans. Des. Autom. Electron. Syst. 10, 1 (2005), 3--23.
    [9]
    Jason Cong, John Peck, and Yuzheng Ding. 1996. RASP: A general logic synthesis system for SRAM-based FPGAs. In Proceedings of the International Symposium on Field-programmable Gate Arrays. ACM, 137--143.
    [10]
    James Coole and Greg Stitt. 2010. Intermediate fabrics: Virtual architectures for circuit portability and fast placement and routing. In Proceedings of the 8th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. ACM, 13--22.
    [11]
    Fatemeh Eslami, Eddie Hung, and Steven J. E. Wilton. 2016. Enabling effective FPGA debug using overlays: Opportunities and challenges. In Proceedings of the International Workshop on Overlay Architectures for FPGAs.
    [12]
    Fatemeh Eslami and Steven J. E. Wilton. 2014. Incremental distributed trigger insertion for efficient FPGA debug. In Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE, 1--4.
    [13]
    Fatemeh Eslami and Steven J. E. Wilton. 2015. An adaptive virtual overlay for fast trigger insertion for FPGA debug. In Proceedings of the International Conference on Field Programmable Technology. IEEE, 32--39.
    [14]
    Fatemeh Eslami and Steven J. E. Wilton. 2017. An improved overlay and mapping algorithm supporting rapid triggering for FPGA debug. SIGARCH Comput. Arch. News 44, 4 (2017), 20--25.
    [15]
    Harry D. Foster. 2015. Trends in functional verification: A 2014 industry study. In Proceedings of the Design Automation Conference. ACM, 48.
    [16]
    Jeffrey Goeders and Steven J. E. Wilton. 2017. Signal-tracing techniques for in-system FPGA debugging of high-level synthesis circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 36, 1 (2017), 83--96.
    [17]
    Paul Graham, Brent Nelson, and Brad Hutchings. 2001. Instrumenting bitstreams for debugging FPGA circuits. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, 41--50.
    [18]
    H. J. Hoover, M. M. Klawe, and N. J. Pippenger. 1984. Bounding fan-out in logical networks. J. ACM 31, 1 (1984), 13--18.
    [19]
    Eddie Hung, Fatemeh Eslami, and Steven J. E. Wilton. 2013. Escaping the academic sandbox: Realizing VPR circuits on Xilinx devices. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, 45--52.
    [20]
    Eddie Hung, Tim Todman, and Wayne Luk. 2014. Transparent insertion of latency-oblivious logic onto FPGAs. In Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE, 1--8.
    [21]
    Eddie Hung and Steven J. E. Wilton. 2013. Towards simulator-like observability for FPGAs: A virtual overlay network for trace-buffers. In Proceedings of the International Symposium on Field Programmable Gate Arrays. ACM, 19--28.
    [22]
    Eddie Hung and Steven J. E. Wilton. 2014a. Accelerating FPGA debug: Increasing visibility using a runtime reconfigurable observation and triggering network. ACM Trans. Des. Autom. Electr. Syst. 19, 2 (2014), 14.
    [23]
    Eddie Hung and Steven J. E. Wilton. 2014b. Incremental trace-buffer insertion for FPGA debug. IEEE Trans. VLSI Syst. 22, 4 (2014), 850--863.
    [24]
    Brad L. Hutchings and Jared Keeley. 2014. Rapid post-map insertion of embedded logic analyzers for Xilinx FPGAs. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, 72--79.
    [25]
    Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, and Derek G. Corneil. 1998. Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 17, 10 (1998), 985--996.
    [26]
    Intel Corporation. 2015. Intel completes acquisition of altera. Retrieved from https://newsroom.intel.com/news-releases/intel-completes-acquisition-of-altera/.
    [27]
    Intel Corporation. 2017. Quartus Prime Standard Edition Handbook, Volume 3: Verification; 13. Design Debugging with the SignalTap II Logic Analyzer.
    [28]
    Nachiket Kapre, Nikil Mehta, Raphael Rubin, Henry Barnor, Michael J. Wilson, Michael Wrighton, Andre DeHon, and others. 2006. Packet switched vs. time multiplexed FPGA overlay networks. In Proceedings of the International Symposium on Field-Programmable Custom Computing Machines. IEEE, 205--216.
    [29]
    Ho Fai Ko and Nicola Nicolici. 2009. Algorithms for state restoration and trace-signal selection for data acquisition in silicon debug. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 28, 2 (2009), 285--297.
    [30]
    Dirk Koch, Christian Beckhoff, and Guy G. F. Lemieux. 2013. An efficient FPGA overlay for portable custom instruction set extensions. In Proceedings of the International Conference on Field Programmable Logic and Applications. IEEE, 1--8.
    [31]
    Alexandra Kourfali and Dirk Stroobandt. 2016. Efficient hardware debugging using parameterized FPGA reconfiguration. In Proceedings of the International Parallel and Distributed Processing Symposium Workshops. IEEE, 277--282.
    [32]
    Paul D. Kundarewich and Jonathan Rose. 2004. Synthetic circuit generation using clustering and iteration. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 23, 6 (2004), 869--887.
    [33]
    Aaron Landy and Greg Stitt. 2012. A low-overhead interconnect architecture for virtual reconfigurable fabrics. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems. ACM, 111--120.
    [34]
    Olav Lindtjorn, Robert Clapp, Oliver Pell, Haohuan Fu, Michael Flynn, and Oskar Mencer. 2011. Beyond traditional microprocessors for geoscience high-performance computing applications. Micro 31, 2 (2011), 41--49.
    [35]
    Jason Luu and others. 2014. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Trans. Reconfig. Technol. Syst. 7, 2 (2014), 6.
    [36]
    Alexander Marquardt, Vaughn Betz, and Jonathan Rose. 2000. Timing-driven placement for FPGAs. In Proceedings of the International Symposium on Field Programmable Gate Arrays. ACM, 203--213.
    [37]
    Larry McMurchie and Carl Ebeling. 1995. PathFinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the International Symposium on Field-programmable Gate Arrays. ACM, 111--117.
    [38]
    Mishchenko et al. 2012. ABC: A system for sequential synthesis and verification. Retrieved from http://www.eecs.berkeley.edu/∼alanmi/abc/.
    [39]
    Subhasish Mitra, Sanjit A. Seshia, and Nicola Nicolici. 2010. Post-silicon validation opportunities, challenges and recent advances. In Proceedings of the Design Automation Conference. ACM, 12--17.
    [40]
    Andrew Putnam, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, and others. 2014. A reconfigurable fabric for accelerating large-scale datacenter services. In Proceedings of the International Symposium on Computer Architecture. IEEE, 13--24.
    [41]
    John E. Savage. 1987. The Complexity of Computing. Krieger Publishing Co., Inc., Melbourne, FL.
    [42]
    Scott Sirowy and Alessandro Forin. 2008. Where’s the Beef? Why FPGAs Are So Fast. Technical Report MSR-TR-2008-130. Microsoft Research, Microsoft Corp., Redmond, WA.
    [43]
    Synopsys. 2017. Identify: Simulator-like Visibility into Hardware Debug. Retrieved from https://www.synopsys.com/content/dam/synopsys/implementation8signoff/datasheets/identify-rtl-debugger-ds.pdf.
    [44]
    Shashidhar Thakur and D. F. Wong. 1995. On designing ULM-based FPGA logic modules. In Proceedings of the International Symposium on Field-programmable Gate Arrays. ACM, 3--9.
    [45]
    Steven J. E. Wilton, Noha Kafafi, James C. H. Wu, Kimberly A. Bozman, Victor O. Aken’Ova, and Resve Saleh. 2005. Design considerations for soft embedded programmable logic cores. J. Solid-State Circ. 40, 2 (2005), 485--497.
    [46]
    Xilinx. 2017. Programming and Debugging, Vivado Design Suite User Guide UG908 (v2017.1). San Jose, CA.

    Cited By

    View all
    • (2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
    • (2021)Improved design debugging architecture using low power serial communication protocols for signal processing applicationsInternational Journal of Speech Technology10.1007/s10772-020-09784-x24:2(291-302)Online publication date: 1-Jun-2021

    Recommendations

    Comments

    Information & Contributors

    Information

    Published In

    cover image ACM Transactions on Design Automation of Electronic Systems
    ACM Transactions on Design Automation of Electronic Systems  Volume 23, Issue 6
    Special Issue on Internet of Things System Performance, Reliability, and Security
    November 2018
    288 pages
    ISSN:1084-4309
    EISSN:1557-7309
    DOI:10.1145/3291062
    • Editor:
    • Naehyuck Chang
    Issue’s Table of Contents
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

    Publisher

    Association for Computing Machinery

    New York, NY, United States

    Journal Family

    Publication History

    Published: 06 December 2018
    Accepted: 01 July 2018
    Revised: 01 April 2018
    Received: 01 August 2017
    Published in TODAES Volume 23, Issue 6

    Permissions

    Request permissions for this article.

    Check for updates

    Author Tags

    1. FPGA debug
    2. debug instruments
    3. overlay fabric
    4. trace buffers
    5. trigger

    Qualifiers

    • Research-article
    • Research
    • Refereed

    Contributors

    Other Metrics

    Bibliometrics & Citations

    Bibliometrics

    Article Metrics

    • Downloads (Last 12 months)2
    • Downloads (Last 6 weeks)0

    Other Metrics

    Citations

    Cited By

    View all
    • (2021)Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future ProspectsACM Transactions on Reconfigurable Technology and Systems10.1145/346966014:4(1-39)Online publication date: 13-Sep-2021
    • (2021)Improved design debugging architecture using low power serial communication protocols for signal processing applicationsInternational Journal of Speech Technology10.1007/s10772-020-09784-x24:2(291-302)Online publication date: 1-Jun-2021

    View Options

    Get Access

    Login options

    Full Access

    View options

    PDF

    View or Download as a PDF file.

    PDF

    eReader

    View online with eReader.

    eReader

    Media

    Figures

    Other

    Tables

    Share

    Share

    Share this Publication link

    Share on social media